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1. 发明申请

US20050062507A1 System and method to adjust voltage 失效
标题翻译：系统和方法来调节电压
公开(公告)号：US20050062507A1
公开(公告)日：2005-03-24
申请号：US10648570
申请日：2003-08-26
申请人： Samuel Naffziger , Shahram Ghahremani , Christopher Poirier
发明人： Samuel Naffziger , Shahram Ghahremani , Christopher Poirier
IPC分类号： G05F1/10 , H02M3/00 , H03L7/07 , H03L7/087 , H03L7/099 , H03L1/00
CPC分类号： H03L7/087 , H03L7/07 , H03L7/0992
摘要： A system and method that can be utilized to implement voltage adjustment (e.g., for an integrated circuit). In one embodiment, the system comprises a frequency generator that provides a clock signal having a frequency that varies based on an operating voltage. The system also includes a controller that provides a control signal to adjust the operating voltage based on adjustments to the frequency of the clock signal.
摘要翻译：可用于实现电压调整（例如，用于集成电路）的系统和方法。在一个实施例中，该系统包括提供具有基于工作电压而变化的频率的时钟信号的频率发生器。该系统还包括控制器，其提供控制信号以根据对时钟信号的频率的调整来调整工作电压。

2. 发明授权

US6072346A Metastable protected latch 失效
标题翻译：平稳保护闩锁
公开(公告)号：US6072346A
公开(公告)日：2000-06-06
申请号：US999212
申请日：1997-12-29
申请人： Shahram Ghahremani
发明人： Shahram Ghahremani
IPC分类号： H03K3/037 , H03K3/356 , H03K3/3565 , H03K3/02
CPC分类号： H03K3/356121 , H03K3/0375 , H03K3/3565
摘要： The present invention provides a level sensitive circuit connected to the output portion of a register, which synchronizes an asynchronous input to a clocked network driven by the CPU system clock. The level sensitive circuit ensures that the output of the synchronizing register will always be a definite binary signal, i.e. logical 0 (ground, or absence of voltage) or logical 1 (voltage). The present invention not only minimizes the occurrence of a metastable condition, but also recognizes that metastability may occur. The present invention is optimized to prevent metastability and includes a synchronizing latch having an output circuit with a feedback mechanism that effectively causes the output voltage of the register to be a valid signal only when any metastable condition has resolved itself. More particularly, the non-inverted output of the register is utilized as feedback to the level sensitive circuit. Based on the various threshold voltages of the transistors in the level sensitive circuit, the output of the register will switch only when a sufficiently stable voltage (high or low) is present as the output of the level sensitive circuit.
摘要翻译：本发明提供一种连接到寄存器的输出部分的电平敏感电路，其将异步输入同步到由CPU系统时钟驱动的时钟网络。电平敏感电路确保同步寄存器的输出始终是确定的二进制信号，即逻辑0（接地或不存在电压）或逻辑1（电压）。本发明不仅使亚稳态的发生最小化，而且还认识到可能发生亚稳态。本发明被优化以防止亚稳态，并且包括同步锁存器，其具有具有反馈机制的输出电路，其仅在任何亚稳态已经解决时有效地使寄存器的输出电压为有效信号。更具体地，寄存器的非反相输出被用作对电平敏感电路的反馈。基于电平敏感电路中的晶体管的各种阈值电压，寄存器的输出只有在存在足够稳定的电压（高或低）电压作为电平敏感电路的输出时才会切换。

3. 发明授权

US07148755B2 System and method to adjust voltage 失效
标题翻译：系统和方法来调节电压
公开(公告)号：US07148755B2
公开(公告)日：2006-12-12
申请号：US10648570
申请日：2003-08-26
申请人： Samuel D. Naffziger , Shahram Ghahremani , Christopher A. Poirier
发明人： Samuel D. Naffziger , Shahram Ghahremani , Christopher A. Poirier
IPC分类号： H01L7/16 , H03J7/04
CPC分类号： H03L7/087 , H03L7/07 , H03L7/0992
摘要： A system and method that can be utilized to implement voltage adjustment (e.g., for an integrated circuit). In one embodiment, the system comprises a frequency generator that provides a clock signal having a frequency that varies based on an operating voltage. The system also includes a controller that provides a control signal to adjust the operating voltage based on adjustments to the frequency of the clock signal.
摘要翻译：可用于实现电压调整（例如，用于集成电路）的系统和方法。在一个实施例中，该系统包括提供具有基于工作电压而变化的频率的时钟信号的频率发生器。该系统还包括控制器，其提供控制信号以根据对时钟信号的频率的调整来调整工作电压。

4. 发明授权

US07068081B2 Frequency synthesizer with digital phase selection 失效
标题翻译：具有数字相位选择的频率合成器
公开(公告)号：US07068081B2
公开(公告)日：2006-06-27
申请号：US10838395
申请日：2004-05-04
申请人： Samuel David Naffziger , Shahram Ghahremani
发明人： Samuel David Naffziger , Shahram Ghahremani
IPC分类号： H03B21/00
CPC分类号： H03L7/16 , H03L7/081 , H03L7/0812
摘要： Systems, methodologies, media, and other embodiments associated with making a frequency change through frequency synthesis and digital selection of out-of-phase synthesized signals are described. One exemplary system embodiment includes a locked loop logic (e.g., phase locked, delay locked) that may receive a reference clock signal, process the reference clock signal into signals with different phases, and make those signals available to a selection logic. The exemplary system may also include a state logic that stores frequency divisors that facilitate selecting and tracking output signals provided by the selection logic. The exemplary system may also include a phase logic that stores output signal phase data associated with computing, describing, and/or selecting an output signal.
摘要翻译：描述了通过频率合成和异相合成信号的数字选择进行频率改变的系统，方法，媒体和其它实施例。一个示例性系统实施例包括可以接收参考时钟信号的锁定环路逻辑（例如，锁相，延迟锁定），将参考时钟信号处理成具有不同相位的信号，并使这些信号可用于选择逻辑。示例性系统还可以包括状态逻辑，其存储有助于选择和跟踪由选择逻辑提供的输出信号的频率因数。示例性系统还可以包括相位逻辑，其存储与计算，描述和/或选择输出信号相关联的输出信号相位数据。

5. 发明申请

US20050248373A1 Frequency synthesizer with digital phase selection 失效
标题翻译：具有数字相位选择的频率合成器
公开(公告)号：US20050248373A1
公开(公告)日：2005-11-10
申请号：US10838395
申请日：2004-05-04
申请人： Samuel Naffziger , Shahram Ghahremani
发明人： Samuel Naffziger , Shahram Ghahremani
IPC分类号： G06F1/12 , G06F1/08 , H02M3/315 , H03L7/08 , H03L7/081 , H03L7/16
CPC分类号： H03L7/16 , H03L7/081 , H03L7/0812
摘要： Systems, methodologies, media, and other embodiments associated with making a frequency change through frequency synthesis and digital selection of out-of-phase synthesized signals are described. One exemplary system embodiment includes a locked loop logic (e.g., phase locked, delay locked) that may receive a reference clock signal, process the reference clock signal into signals with different phases, and make those signals available to a selection logic. The exemplary system may also include a state logic that stores frequency divisors that facilitate selecting and tracking output signals provided by the selection logic. The exemplary system may also include a phase logic that stores output signal phase data associated with computing, describing, and/or selecting an output signal.
摘要翻译：描述了通过频率合成和异相合成信号的数字选择进行频率改变的系统，方法，媒体和其它实施例。一个示例性系统实施例包括可以接收参考时钟信号的锁定环路逻辑（例如，锁相，延迟锁定），将参考时钟信号处理成具有不同相位的信号，并使这些信号可用于选择逻辑。示例性系统还可以包括状态逻辑，其存储有助于选择和跟踪由选择逻辑提供的输出信号的频率因数。示例性系统还可以包括相位逻辑，其存储与计算，描述和/或选择输出信号相关联的输出信号相位数据。

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