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1. 发明授权

US07898306B1 High bandwidth phase locked loop (PLL) with feedback loop including a frequency divider 有权
标题翻译：具有反馈环路的高带宽锁相环（PLL）包括分频器
公开(公告)号：US07898306B1
公开(公告)日：2011-03-01
申请号：US12235507
申请日：2008-09-22
申请人： Chi Fung Cheng
发明人： Chi Fung Cheng
IPC分类号： H03L7/16
CPC分类号： H03L7/081
摘要： A phase locked loop (PLL) is provided. In one implementation, the PLL includes a multiphase voltage controlled oscillator (VCO) operable to generate an output signal containing one or more phase signals, a programmable divider operable to divide a frequency of the output signal of the multiphase VCO to produce a divided frequency output signal, and a fractional divider to fractionally divide an input phase signal. The fractional divider can include an integer divider operable to receive the input phase signal and divide the input phase signal in accordance with an integer divisor to produce a divided signal as an input to the multiphase VCO, and a phase interpolator operable to select a phase signal from among the one or more phase signals output by the multiphase VCO, to produce an interpolated output signal having a desired frequency resolution.
摘要翻译：提供锁相环（PLL）。在一个实现中，PLL包括可操作以产生包含一个或多个相位信号的输出信号的多相压控振荡器（VCO），可编程分频器，可操作以分频多相VCO的输出信号的频率以产生分频输出信号和一个分数分频器来对输入相位信号进行分数分频。分数除法器可以包括一个整数除法器，可操作用于接收输入相位信号，并根据整数除数分频输入相位信号，以产生分频信号作为多相VCO的输入;以及相位插值器，可操作以选择相位信号从由多相VCO输出的一个或多个相位信号中产生具有期望频率分辨率的内插输出信号。

2. 发明授权

US07825737B1 Apparatus for low-jitter frequency and phase locked loop and associated methods 有权
标题翻译：低抖动频率和锁相环及相关方法的设备
公开(公告)号：US07825737B1
公开(公告)日：2010-11-02
申请号：US12334701
申请日：2008-12-15
申请人： Steve Fang , Chi Fung Cheng
发明人： Steve Fang , Chi Fung Cheng
IPC分类号： H03L7/087
CPC分类号： H03L7/081 , H03L7/085 , H03L7/087
摘要： A frequency phase locked loop (FPLL) includes a first feedback loop coupled to a second feedback loop. The first feedback loop is configured to correct a phase offset of an output signal of the FPLL. The second feedback loop is configured to correct a frequency offset of the output signal of the FPLL.
摘要翻译：频率锁相环（FPLL）包括耦合到第二反馈环路的第一反馈环路。第一个反馈回路被配置为校正FPLL的输出信号的相位偏移。第二反馈回路被配置为校正FPLL的输出信号的频率偏移。

3. 发明授权

US07589649B1 Apparatus, method, and system for correction of baseline wander 有权
标题翻译：用于校正基线漂移的装置，方法和系统
公开(公告)号：US07589649B1
公开(公告)日：2009-09-15
申请号：US11800554
申请日：2007-05-04
申请人： Arshan Aga , Chi Fung Cheng , Hongxin Song
发明人： Arshan Aga , Chi Fung Cheng , Hongxin Song
IPC分类号： H03M1/06
CPC分类号： H03M1/1295 , G11B7/005
摘要： Apparatuses, methods, and systems for compensating baseline offset in a read channel of an analog storage device. The apparatus generally includes an AC-coupling circuit configured to transfer an analog signal from an analog storage device to the read channel, a configurable current device coupled to the AC-coupling circuit, comparator coupled to the AC-coupling circuit, and logic coupled to the configurable current device and the comparator, wherein the logic is adapted to configure said current device in response to an output of at least one of the AC-coupling circuit and the comparator. The method generally includes the steps of coupling an analog storage device and the read channel with an AC-coupling circuit, detecting a baseline or a component of an analog signal at a node downstream from the AC-coupling circuit, and configuring a current device to modify the analog signal in response to detecting the baseline or a component of the analog signal, wherein the current device is coupled to a node downstream from the AC-coupling circuit and upstream from a signal processor configured to operate on the analog signal.
摘要翻译：用于补偿模拟存储设备的读通道中的基线偏移的装置，方法和系统。该装置通常包括被配置为将模拟信号从模拟存储设备传送到读通道的AC耦合电路，耦合到AC耦合电路的可配置电流器件，耦合到AC耦合电路的比较器，以及耦合到所述可配置电流装置和所述比较器，其中所述逻辑适于响应于所述AC耦合电路和所述比较器中的至少一个的输出来配置所述当前装置。该方法通常包括以下步骤：将模拟存储设备和读取通道与AC耦合电路耦合，检测AC耦合电路下游节点处的模拟信号的基线或分量，并将当前设备配置为响应于检测到模拟信号的基线或分量来修改模拟信号，其中当前设备耦合到从AC耦合电路下游的节点并且被配置为对模拟信号进行操作的信号处理器的上游。

4. 发明授权

US06721114B1 Precompensation circuit for magnetic recording 有权
标题翻译：磁记录预补偿电路
公开(公告)号：US06721114B1
公开(公告)日：2004-04-13
申请号：US09874949
申请日：2001-06-05
申请人： Pantas Sutardja , Chi Fung Cheng
发明人： Pantas Sutardja , Chi Fung Cheng
IPC分类号： G11B509
CPC分类号： G11B20/10194 , G11B5/012 , G11B5/09 , G11B20/1403 , G11B2005/001
摘要： In a precompensation circuit for magnetic recording of data signals, a clock produces clock signals at a predetermined rate to clock the recording of the data signals. A clock delay generator generates clock delay data relative to the generated clock signals for successive data signals to be recorded. The clock delay data for each data signal is formed according to the states of a set of adjacent data signals. n>1 programmable clock delay units operate sequentially to control the recording times of the successive data signals. Each clock delay unit receives the clock delay data for one data signal in each sequence of n successive data signals and determines recording time of the one data signal according to the clock delay data for the one data signal in the sequence.
摘要翻译：在用于数据信号的磁记录的预补偿电路中，时钟以预定速率产生时钟信号以对数据信号的记录进行时钟。时钟延迟发生器相对于所记录的连续数据信号产生的时钟信号产生时钟延迟数据。根据一组相邻数据信号的状态，形成每个数据信号的时钟延迟数据。 n> 1个可编程时钟延迟单元依次操作以控制连续数据信号的记录时间。每个时钟延迟单元在n个连续数据信号的每个序列中接收一个数据信号的时钟延迟数据，并根据序列中的一个数据信号的时钟延迟数据确定一个数据信号的记录时间。

5. 发明授权

US08319524B1 Deglitch circuit removing glitches from input clock signal 有权
标题翻译： Deglitch电路从输入时钟信号中去除毛刺
公开(公告)号：US08319524B1
公开(公告)日：2012-11-27
申请号：US10752785
申请日：2004-01-05
申请人： Chi Fung Cheng , Pantas Sutardja
发明人： Chi Fung Cheng , Pantas Sutardja
IPC分类号： G01R29/02
CPC分类号： H03K5/156 , G11B5/09 , G11B20/10222 , G11B2220/2516 , H03K5/1252
摘要： An apparatus, method, and system for removing glitches from a clock signal, including a duty cycle lock loop (DCLL) circuit. A glitch, which may produce errors in the clock signal, may occur when a read channel transitions from an acquired clock signal to an adjusted clock signal. In one embodiment of the inventive deglitch circuit, a first capacitor is charged and discharged in response to an input clock signal, and an output clock signal is provided depending upon the first capacitor's voltage. The output clock signal further charges and discharges a second capacitor whose ratio of charge to discharge currents provides a signal to bias the discharge current of the first capacitor. A second DCLL circuit may be provided to restore the output clock signal duty cycle to the original clock signal duty cycle.
摘要翻译：一种用于从时钟信号中去除毛刺的装置，方法和系统，包括占空比锁定环路（DCLL）电路。当读取通道从所获取的时钟信号转换到经调整的时钟信号时，可能发生可能在时钟信号中产生错误的毛刺。在本发明的切口电路的一个实施例中，响应于输入时钟信号对第一电容器进行充电和放电，并且根据第一电容器的电压提供输出时钟信号。输出时钟信号还对第二电容器进行充电和放电，其中充电与放电电流的比率提供信号以偏置第一电容器的放电电流。可以提供第二DCLL电路以将输出时钟信号占空比恢复到原始时钟信号占空比。

6. 发明授权

US07427883B1 High bandwidth phase locked pool (PLL) 有权
标题翻译：高带宽锁相环（PLL）
公开(公告)号：US07427883B1
公开(公告)日：2008-09-23
申请号：US11542961
申请日：2006-10-03
申请人： Chi Fung Cheng
发明人： Chi Fung Cheng
IPC分类号： H03L7/16
CPC分类号： H03L7/081
摘要： A phase locked loop (PLL) is provided. In one implementation, the PLL includes a feedback loop having a frequency multiplier and an integer divider to generate a divided signal. The PLL includes a re-sampling circuit operable to re-sample one or more digital pulses of the divided signal using one or more phase signals if a multiplication factor of the frequency multiplier does not divide evenly into the integer divisor.
摘要翻译：提供锁相环（PLL）。在一个实现中，PLL包括具有倍频器和整数除法器的反馈回路，以产生分频信号。 PLL包括重采样电路，其可操作以如果倍频器的乘法因子不均匀地划分成整数除数，则使用一个或多个相位信号重新采样分频信号的一个或多个数字脉冲。

7. 发明申请

US20080204074A1 DEDICATED INTERFACE ARCHITECTURE FOR A HYBRID INTEGRATED CIRCUIT 有权
标题翻译：用于混合集成电路的专用接口架构
公开(公告)号：US20080204074A1
公开(公告)日：2008-08-28
申请号：US12114143
申请日：2008-05-02
申请人： King W. Chan , William C.T. Shu , Sinan Kaptanoglu , Chi Fung Cheng
发明人： King W. Chan , William C.T. Shu , Sinan Kaptanoglu , Chi Fung Cheng
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , G06F15/7867
摘要： An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.
摘要翻译：用于混合IC的接口设计，其利用专用接口轨道来允许信号与FPGA部分的逻辑块分布地接口，从而提供混合IC的FPGA和ASIC部分之间的更快更有效的通信。

8. 发明授权

US07184231B1 Precompensation circuit for magnetic recording 有权
标题翻译：磁记录预补偿电路
公开(公告)号：US07184231B1
公开(公告)日：2007-02-27
申请号：US11250373
申请日：2005-10-17
申请人： Pantas Sutardja , Chi Fung Cheng
发明人： Pantas Sutardja , Chi Fung Cheng
IPC分类号： G11B5/09
CPC分类号： G11B20/10009 , G11B5/09 , H03L7/06
摘要： In a precompensation circuit for magnetic recording of data signals, a clock produces clock signals at a predetermined rate to clock the recording of the data signals. A clock delay generator generates clock delay data relative to the generated clock signals for successive data signals to be recorded. The clock delay data for each data signal is formed according to the states of a set of adjacent data signals. n>1 programmable clock delay units operate sequentially to control the recording times of the successive data signals. Each clock delay unit receives the clock delay data for one data signal in each sequence of n successive data signals and determines recording time of the one data signal according to the clock delay data for the one data signal in the sequence.
摘要翻译：在用于数据信号的磁记录的预补偿电路中，时钟以预定速率产生时钟信号以对数据信号的记录进行时钟。时钟延迟发生器相对于所记录的连续数据信号产生的时钟信号产生时钟延迟数据。根据一组相邻数据信号的状态，形成每个数据信号的时钟延迟数据。 n> 1个可编程时钟延迟单元依次操作以控制连续数据信号的记录时间。每个时钟延迟单元在n个连续数据信号的每个序列中接收一个数据信号的时钟延迟数据，并根据序列中的一个数据信号的时钟延迟数据确定一个数据信号的记录时间。

9. 发明授权

US08990757B2 Dedicated interface architecture for a hybrid integrated circuit 有权
标题翻译：专用于混合集成电路的接口架构
公开(公告)号：US08990757B2
公开(公告)日：2015-03-24
申请号：US12114143
申请日：2008-05-02
申请人： King W. Chan , William C. T. Shu , Sinan Kaptanoglu , Chi Fung Cheng
发明人： King W. Chan , William C. T. Shu , Sinan Kaptanoglu , Chi Fung Cheng
IPC分类号： G06F17/50 , H03K19/177 , G06F15/78
CPC分类号： H03K19/177 , G06F15/7867
摘要： An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.
摘要翻译：用于混合IC的接口设计，其利用专用接口轨道来允许信号与FPGA部分的逻辑块分布地接口，从而提供混合IC的FPGA和ASIC部分之间的更快更有效的通信。

10. 发明授权

US08358478B1 Method and apparatus for write precompensation in a magnetic recording system 有权
标题翻译：磁记录系统中的写入预补偿方法和装置
公开(公告)号：US08358478B1
公开(公告)日：2013-01-22
申请号：US13012422
申请日：2011-01-24
申请人： Chi Fung Cheng
发明人： Chi Fung Cheng
IPC分类号： G11B5/02
CPC分类号： G11B5/09 , G11B20/10194 , G11B20/10222 , G11B2220/2516
摘要： A device is provided that, in one implementation, includes interpolators to generate interpolated phase shifted signals, and a precompensation circuit to provide precompensated versions of data bits in accordance with the interpolated phase shifted signals. Each of the interpolators is assigned a bit pattern different from that assigned to remaining ones of the interpolators.
摘要翻译：提供了一种装置，其在一个实现中包括内插器以产生内插相移信号，以及预补偿电路，以根据内插相移信号提供预补偿版本的数据位。每个内插器被分配与分配给剩余的内插器的位模式不同的位模式。

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