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131. 发明授权

US07064387B2 Silicon-on-insulator (SOI) substrate and method for manufacturing the same 有权
标题翻译：绝缘体上硅（SOI）衬底及其制造方法
公开(公告)号：US07064387B2
公开(公告)日：2006-06-20
申请号：US10874403
申请日：2004-06-22
申请人： Tae-Ho Jang
发明人： Tae-Ho Jang
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/76243 , H01L21/76264 , H01L21/76267
摘要： A silicon-on-insulator (SOI) substrate includes a silicon substrate including an active region defined by a field region that surrounds the active region for device isolation. The field region includes a first oxygen-ion-injected isolation region and a second oxygen-ion-injected isolation region. The first oxygen-ion-injected isolation region has a first thickness and is disposed under the active region, a center of the first oxygen-ion-injected isolation region being at a first depth from a top surface of the silicon substrate. The second oxygen-ion-injected isolation region has a second thickness that is greater than the first thickness, the second oxygen-ion-injected isolation region disposed at sides of the active region and formed from a ton surface of the silicon substrate, a center of the second oxygen-ion-injected region disposed at a second depth from the top surface of the silicon substrate.
摘要翻译：绝缘体上硅（SOI）衬底包括硅衬底，其包括由围绕用于器件隔离的有源区域的场区限定的有源区。场区域包括第一氧离子注入隔离区域和第二氧离子注入隔离区域。第一氧离子注入隔离区具有第一厚度并且设置在有源区下方，第一氧离子注入隔离区的中心处于距离硅衬底顶表面的第一深度。所述第二氧离子注入隔离区具有大于所述第一厚度的第二厚度，所述第二氧离子注入隔离区域设置在所述有源区的侧面并由所述硅衬底的ton表面形成，的第二氧离子注入区域设置在距离硅衬底的顶表面的第二深度。

132. 发明申请

US20060024931A1 Dual SIMOX hybrid orientation technology (HOT) substrates 失效
标题翻译：双SIMOX混合取向技术（HOT）底物
公开(公告)号：US20060024931A1
公开(公告)日：2006-02-02
申请号：US10902557
申请日：2004-07-29
申请人： Kevin Chan , Joel de Souza , Alexander Reznicek , Devendra Sadana , Katherine Saenger
发明人： Kevin Chan , Joel de Souza , Alexander Reznicek , Devendra Sadana , Katherine Saenger
IPC分类号： H01L21/20 , H01L21/425 , H01L21/762 , H01L21/84
CPC分类号： H01L21/84 , H01L21/76243 , H01L21/76267 , H01L27/1203 , H01L27/1207
摘要： This invention provides a separation by implanted oxygen (SIMOX) method for forming planar hybrid orientation semiconductor-on-insulator (SOI) substrates having different crystal orientations, thereby making it possible for devices to be fabricated on crystal orientations providing optimal performance. The method includes the steps of selecting a substrate having a base semiconductor layer having a first crystallographic orientation separated by a thin insulating layer from a top semiconductor layer having a second crystallographic orientation; replacing the top semiconductor layer in selected regions with an epitaxially grown semiconductor having the first crystallographic orientation; then using an ion implantation and annealing method to (i) form a buried insulating region within the epitaxially grown semiconductor material, and (ii) thicken the insulating layer underlying the top semiconductor layer, thereby forming a hybrid orientation substrate in which the two semiconductor materials with different crystallographic orientations have substantially the same thickness and are both disposed on a common buried insulator layer. In a variation of this method, an ion implantation and annealing method is instead used to extend an auxiliary buried insulator layer (initially underlying the base semiconductor layer) upwards (i) into the epitaxially grown semiconductor, and (ii) up to the insulating layer underlying the top semiconductor layer.
摘要翻译：本发明提供了通过注入氧（SIMOX）分离方法，用于形成具有不同晶体取向的平面杂化取向绝缘体上半导体（SOI）衬底，从而使得可以以提供最佳性能的晶体取向来制造器件。该方法包括以下步骤：从具有第二晶体取向的顶部半导体层选择具有由薄绝缘层分离的第一晶体取向的基底半导体层的衬底; 用具有第一晶体取向的外延生长的半导体代替选定区域中的顶部半导体层; 然后使用离子注入和退火方法来（i）在外延生长的半导体材料内形成掩埋绝缘区，并且（ii）加厚顶部半导体层下面的绝缘层，从而形成混合取向基板，其中两个半导体材料具有不同的晶体取向具有基本上相同的厚度并且均设置在公共掩埋绝缘体层上。在该方法的变型中，替代地使用离子注入和退火方法将辅助掩埋绝缘体层（最初在基底半导体层下面）向上（i）延伸到外延生长的半导体中，以及（ii）直到绝缘层在顶部半导体层下面。

133. 发明授权

US06946358B2 Method of fabricating shallow trench isolation by ultra-thin SIMOX processing 失效
标题翻译：通过超薄SIMOX处理制造浅沟槽隔离的方法
公开(公告)号：US06946358B2
公开(公告)日：2005-09-20
申请号：US10250053
申请日：2003-05-30
申请人： Bruce B. Doris , Mark C. Hakey , Akihisa Sekiguchi
发明人： Bruce B. Doris , Mark C. Hakey , Akihisa Sekiguchi
IPC分类号： H01L21/762 , H01L21/76 , H01L21/20 , H01L21/31 , H01L21/36
CPC分类号： H01L21/76237 , H01L21/76243 , H01L21/76267
摘要： The present invention provides a cost effective and simple method of forming isolation regions, such as shallow trench isolation regions, in a semiconductor substrate that avoids etching into the trench. In the present invention, the isolation regions are formed by utilizing a selective ion implantation process that creates an oxygen implant region near the upper surface of the substrate. Upon a subsequent anneal step, the oxygen implant region is converted into an isolation region that has an upper surface that is substantially coplanar with the upper surface of the substrate.
摘要翻译：本发明提供了在半导体衬底中形成隔离区域（例如浅沟槽隔离区域）的成本有效和简单的方法，其避免了蚀刻到沟槽中。在本发明中，通过利用在衬底的上表面附近产生氧注入区的选择性离子注入工艺来形成隔离区。在随后的退火步骤中，氧注入区域被转换成具有与衬底的上表面基本上共面的上表面的隔离区域。

134. 发明申请

US20050189610A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050189610A1
公开(公告)日：2005-09-01
申请号：US11064001
申请日：2005-02-24
申请人： Koji Usuda , Shinichi Takagi
发明人： Koji Usuda , Shinichi Takagi
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/092 , H01L27/10 , H01L29/10 , H01L29/51 , H01L29/786 , H01L31/0328
CPC分类号： H01L21/76267 , H01L21/76243 , H01L21/823878 , H01L21/84 , H01L29/1054 , H01L29/51
摘要： A method of manufacturing a semiconductor device, includes selectively forming a mask having an opening on a semiconductor substrate, ion-implanting oxygen to a predetermined depth position of the substrate from a surface of the substrate exposed in the opening of the mask, carrying out annealing with respect to the substrate to oxidize an ion implantation region so that an insulating layer is formed, and forming a first semiconductor element on a region of the semiconductor substrate on the insulating layer, and forming a second semiconductor element on a region other than the region formed with the insulating layer.
摘要翻译：一种制造半导体器件的方法，包括：选择性地形成在半导体衬底上具有开口的掩模，从暴露在掩模开口中的衬底的表面离子注入到衬底的预定深度位置，进行退火相对于所述基板氧化离子注入区域，从而形成绝缘层，并且在所述绝缘层上的所述半导体基板的区域上形成第一半导体元件，并且在所述区域以外的区域上形成第二半导体元件形成有绝缘层。

135. 发明申请

US20040241459A1 Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal 失效
标题翻译：通过整体高温SIMOX-Ge相互扩散退火形成绝缘体上硅锗（SGOI）
公开(公告)号：US20040241459A1
公开(公告)日：2004-12-02
申请号：US10448947
申请日：2003-05-30
申请人： International Business Machines Corporation
发明人： Stephen W. Bedell , Keith E. Fogel , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： B32B009/04
CPC分类号： H01L21/76243 , H01L21/26506 , H01L21/76267 , Y10T428/12674 , Y10T428/12681
摘要： A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implant rich region in the Si-containing substrate. The implant rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.
摘要翻译：提供了使用SIMOX和Ge相互扩散形成基本上松弛的，优质的绝缘体上硅衬底材料的方法。该方法包括首先将离子注入到含Si衬底中以在含Si衬底中形成富含注入区的区域。注入富含区域具有足够的离子浓度，使得在随后的高温退火期间，形成耐Ge扩散的阻挡层。接下来，在含Si衬底的表面上形成Ge含有层，然后在允许形成阻挡层和Ge的相互扩散的温度下进行加热步骤，从而形成基本上松弛的单晶SiGe层阻挡层顶部。

136. 发明申请

US20040235273A1 Silicon-on-insulator (SOI) substrate and method for manufacturing the same 有权
公开(公告)号：US20040235273A1
公开(公告)日：2004-11-25
申请号：US10874403
申请日：2004-06-22
申请人： Samsung Electronics Co., Ltd.
发明人： Tae-Ho Jang
IPC分类号： H01L021/8234 , H01L021/20 , H01L021/76
CPC分类号： H01L21/76243 , H01L21/76264 , H01L21/76267
摘要： Disclosed are an SOI substrate and a method for manufacturing the same. The SOI substrate comprises a silicon substrate including an active region defined by a field region. The field region includes a first oxygen-ion-injected isolation region having a first thickness and being formed under the active region. The center of the first region is at a first depth from a top surface of the silicon substrate. The field region of the SOI substrate further includes a second oxygen-ion-injected region having a second thickness greater than the first thickness. The second region is formed at sides of the active region and is also formed from a top surface of the silicon substrate. The center of the second ion injected region is at a second depth from the top surface of the silicon substrate. The first and second ion injected regions surround the active region for device isolation. The SOI substrate is formed by implementing two sequential ion injecting processes. Because the isolation of the active regions can be achieved by implementing the ion injecting process using the sacrificial blocking layer pattern, active regions having various shapes can be obtained with simple and less-costly methods.

137. 发明授权

US06664146B1 Integration of fully depleted and partially depleted field effect transistors formed in SOI technology 失效
标题翻译：在SOI技术中形成的完全耗尽和部分耗尽的场效应晶体管的集成
公开(公告)号：US06664146B1
公开(公告)日：2003-12-16
申请号：US09873170
申请日：2001-06-01
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L2184
CPC分类号： H01L21/76264 , H01L21/76267 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： For fabricating field effect transistors with a semiconductor substrate in SOI (semiconductor on insulator) technology, a first hardmask is formed on a first area of the semiconductor substrate, and a first dielectric forming dopant is implanted into a second area of the semiconductor substrate that is not covered by the first hardmask. The first hardmask is removed from the first area of the semiconductor substrate. A second hardmask is formed on the second area of the semiconductor substrate, and a second dielectric forming dopant is implanted into the first area of the semiconductor substrate that is not covered by the second hardmask. A thermal anneal is performed to form a first buried insulating structure from the second dielectric forming dopant reacting within the first area of the semiconductor substrate and to form a second buried insulating structure from the first dielectric forming dopant reacting within the second area of the semiconductor substrate. A first semiconductor structure remains on top of the first buried insulating structure and has a different thickness from a second semiconductor structure remaining on top of the second buried insulating structure.
摘要翻译：为了在SOI（绝缘体上半导体）技术中制造具有半导体衬底的场效应晶体管，在半导体衬底的第一区域上形成第一硬掩模，并且将第一电介质形成掺杂剂注入到半导体衬底的第二区域没有被第一个硬掩模覆盖。第一硬掩模从半导体衬底的第一区域去除。第二硬掩模形成在半导体衬底的第二区域上，并且第二电介质形成掺杂剂注入到半导体衬底的未被第二硬掩模覆盖的第一区域中。进行热退火，以形成第一掩埋绝缘结构，从第二电介质形成掺杂剂在半导体衬底的第一区域内反应，并形成第二掩埋绝缘结构，从第一电介质形成掺杂剂在半导体衬底的第二区域内反应。第一半导体结构保留在第一掩埋绝缘结构的顶部，并且具有与保留在第二掩埋绝缘结构的顶部上的第二半导体结构不同的厚度。

138. 发明申请

US20030219954A1 Manufacturing method of semiconductor substrate 有权
标题翻译：半导体衬底的制造方法
公开(公告)号：US20030219954A1
公开(公告)日：2003-11-27
申请号：US10425619
申请日：2003-04-30
发明人： Tomoya Baba
IPC分类号： H01L021/331
CPC分类号： H01L21/76243 , H01L21/76264 , H01L21/76267 , H01L21/76283
摘要： A manufacturing method of a semiconductor substrate comprising the steps of: (a) forming a SiGe layer on a substrate of which the surface is made of silicon; (b) further forming a semiconductor layer on the SiGe layer; and (c) implanting ions into regions of the SiGe layer in the substrate that become element isolation formation regions, and carrying out a heat treatment.
摘要翻译：一种半导体衬底的制造方法，包括以下步骤：（a）在其表面由硅制成的衬底上形成SiGe层; （b）在SiGe层上进一步形成半导体层; 和（c）将离子注入到成为元件隔离形成区域的衬底中的SiGe层的区域中，并进行热处理。

139. 发明授权

US06627511B1 Reduced stress isolation for SOI devices and a method for fabricating 失效
标题翻译：降低SOI器件的应力隔离和制造方法
公开(公告)号：US06627511B1
公开(公告)日：2003-09-30
申请号：US08508874
申请日：1995-07-28
申请人： Marco Racanelli , Hyungcheol Shin , Heemyong Park
发明人： Marco Racanelli , Hyungcheol Shin , Heemyong Park
IPC分类号： H01L2176
CPC分类号： H01L21/76264 , H01L21/32 , H01L21/76267 , H01L21/76275 , H01L21/76281
摘要： A method for forming an isolation structure (22) on a SOI substrate (11) is provided. A three layer stack of an etchant barrier layer (16), a stress relief layer (17), and an oxide mask layer (18) is formed on the SOI substrate (11). The three layer stack is patterned and etched to expose portions of the etchant barrier layer (16). The silicon layer (13) below the exposed portions of the etchant barrier layer (16) is oxidized to form the isolation structure (22). The isolation structure (22) comprises a bird's head region (21) with a small encroachment which results in higher edge threshold voltage. The method requires minimum over-oxidation and provides for an isolation structure (22) that leaves the SOI substrate (11) planar. Minimal over-oxidation reduces the number of dislocations formed during the oxidation process and improves the source to drain leakage of the device.
摘要翻译：提供了一种在SOI衬底（11）上形成隔离结构（22）的方法。在SOI衬底（11）上形成蚀刻剂阻挡层（16），应力消除层（17）和氧化物掩模层（18）的三层堆叠。图案化和蚀刻三层堆叠以暴露蚀刻剂阻挡层（16）的部分。在蚀刻剂阻挡层（16）的暴露部分下面的硅层（13）被氧化以形成隔离结构（22）。隔离结构（22）包括具有小的侵入的鸟头区域（21），其导致较高的边缘阈值电压。该方法需要最小的过氧化并提供使SOI衬底（11）平坦离开的隔离结构（22）。最小的过氧化减少了在氧化过程中形成的位错数，并且改善了器件的源漏漏。

140. 发明授权

US06613639B1 Forming a semiconductor on implanted insulator 有权
标题翻译：在植入绝缘体上形成半导体
公开(公告)号：US06613639B1
公开(公告)日：2003-09-02
申请号：US10060867
申请日：2002-01-30
申请人： Matthew J. Comard
发明人： Matthew J. Comard
IPC分类号： H01L21331
CPC分类号： H01L21/76264 , H01L21/76267 , H01L21/76283
摘要： A method of forming a semiconductor on insulator structure in a monolithic semiconducting substrate with a bulk semiconductor structure. A first portion of a surface of the monolithic semiconducting substrate is recessed without effecting a second portion of the surface of the monolithic semiconducting substrate. An insulator precursor species is implanted beneath the surface of the recessed first portion of the monolithic semiconducting substrate, and a trench is etched around the implanted and recessed first portion of the monolithic semiconducting substrate. The insulator precursor species is activated to form an insulator layer beneath the surface of the recessed first portion of the monolithic semiconducting substrate. The semiconductor on insulator structure is formed in the first portion of the monolithic semiconducting substrate, and the bulk semiconductor structure is formed in the second portion of the monolithic semiconducting substrate.
摘要翻译：一种在具有体半导体结构的单片半导体衬底中形成绝缘体上半导体结构的方法。单片半导体衬底的表面的第一部分是凹入的，而不影响单片半导体衬底的表面的第二部分。在单片半导体衬底的凹入的第一部分的表面下方注入绝缘体前体物质，并且在单片半导体衬底的注入和凹入的第一部分周围蚀刻沟槽。绝缘体前体物质被激活以在单片半导体衬底的凹入的第一部分的表面下方形成绝缘体层。半导体绝缘体结构形成在单片半导体衬底的第一部分中，并且体半导体结构形成在单片半导体衬底的第二部分中。

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