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131. 发明授权

US08912601B2 Double diffused drain metal oxide semiconductor device and manufacturing method thereof 有权
标题翻译：双扩散漏极金属氧化物半导体器件及其制造方法
公开(公告)号：US08912601B2
公开(公告)日：2014-12-16
申请号：US14173571
申请日：2014-02-05
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L29/66 , H01L29/78 , H01L29/08 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/10
CPC分类号： H01L29/78 , H01L21/823412 , H01L21/823418 , H01L27/088 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/66689 , H01L29/7816
摘要： The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively.
摘要翻译：本发明公开了一种双扩散漏极金属氧化物半导体（DDDMOS）器件及其制造方法。 DDDMOS器件形成在衬底中，并且包括第一阱，栅极，扩散区域，源极和漏极。在衬底中还形成低电压器件，该器件包括第二阱和轻掺杂漏极（LDD）区，其中第一阱和扩散区通过也形成第二阱的工艺步骤形成，并且LDD区域低压装置。

132. 发明授权

US08907432B2 Isolated device and manufacturing method thereof 有权
标题翻译：隔离装置及其制造方法
公开(公告)号：US08907432B2
公开(公告)日：2014-12-09
申请号：US13370691
申请日：2012-02-10
申请人： Tsung-Yi Huang , Chien-Wei Chiu
发明人： Tsung-Yi Huang , Chien-Wei Chiu
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L29/08
CPC分类号： H01L29/086 , H01L29/0611 , H01L29/0615 , H01L29/0619 , H01L29/0847 , H01L29/1083 , H01L29/66492 , H01L29/66659 , H01L29/7835
摘要： An isolated device is formed in a substrate in which is formed a high voltage device. The isolated device includes: an isolated well formed in the substrate by a lithography process and an ion implantation process used in forming the high voltage device; a gate formed on the substrate; a source and a drain, which are located in the isolated well at both sides of the gate respectively; a drift-drain region formed beneath the substrate surface, wherein the gate and the drain are separated by the drift-drain region, and the drain is in the drift-drain region; and a mitigation region, which is formed in the substrate and has a shallowest portion located at least below 90% of a depth of the drift-drain region as measured from the substrate surface, wherein the mitigation region and the drift-drain region are defined by a same lithography process.
摘要翻译：隔离器件形成在形成高电压器件的衬底中。隔离装置包括：通过光刻工艺在衬底中形成的隔离阱和用于形成高压器件的离子注入工艺; 形成在基板上的栅极; 源极和漏极分别位于门的两侧的隔离井中; 形成在所述衬底表面下方的漂移漏极区，其中所述栅极和所述漏极由所述漂移 - 漏极区域分开，并且所述漏极在所述漂移 - 漏极区域中; 以及缓解区域，其形成在所述衬底中，并且具有位于所述衬底表面测量的至少位于所述漂移 - 漏极区域的深度的90％以下的最浅部分，其中所述缓解区域和所述漂移 - 漏极区域被限定通过相同的光刻工艺。

133. 发明授权

US08835258B2 High voltage device and manufacturing method thereof 有权
标题翻译：高压器件及其制造方法
公开(公告)号：US08835258B2
公开(公告)日：2014-09-16
申请号：US13844926
申请日：2013-03-16
申请人： Tsung-Yi Huang , Huan-Ping Chu
发明人： Tsung-Yi Huang , Huan-Ping Chu
IPC分类号： H01L21/336 , H01L29/78 , H01L29/08 , H01L29/66 , H01L29/10 , H01L29/423
CPC分类号： H01L29/0878 , H01L29/0847 , H01L29/1083 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate has an upper surface. The high voltage device includes: a second conductive type buried layer, which is formed in the substrate; a first conductive type well, which is formed between the upper surface and the buried layer; and a second conductive type well, which is connected to the first conductive type well and located at different horizontal positions. The second conductive type well includes a well lower surface, which has a first part and a second part, wherein the first part is directly above the buried layer and electrically coupled to the buried layer; and the second part is not located above the buried layer and forms a PN junction with the substrate.
摘要翻译：本发明公开了一种高压器件及其制造方法。高压器件形成在第一导电型衬底中，其中衬底具有上表面。高压器件包括：形成在衬底中的第二导电型掩埋层; 第一导电型阱，其形成在上表面和埋层之间; 以及第二导电型阱，其连接到第一导电类型阱并且位于不同的水平位置。第二导电类型阱包括井下表面，其具有第一部分和第二部分，其中第一部分直接在掩埋层的上方并电耦合到掩埋层; 并且第二部分不位于掩埋层的上方并与衬底形成PN结。

134. 发明授权

US08772900B2 Trench Schottky barrier diode and manufacturing method thereof 失效
标题翻译：沟槽肖特基势垒二极管及其制造方法
公开(公告)号：US08772900B2
公开(公告)日：2014-07-08
申请号：US13543844
申请日：2012-07-08
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L29/72
CPC分类号： H01L29/872 , H01L29/0615 , H01L29/402 , H01L29/66143 , H01L29/8725
摘要： The present invention discloses a trench Schottky barrier diode (SBD) and a manufacturing method thereof. The trench SBD includes: an epitaxial layer, formed on a substrate; multiple mesas, defined by multiple trenches; a field plate, formed on the epitaxial layer and filled in the multiple trenches, wherein a Schottky contact is formed between the field plate and top surfaces of the mesas; a termination region, formed outside the multiple mesas and electrically connected to the field plate; a field isolation layer, formed on the upper surface and located outside the termination region; and at least one mitigation electrode, formed below the upper surface outside the termination region, and is electrically connected to the field plate through the field isolation layer, wherein the mitigation electrode and the termination region are separated by part of a dielectric layer and part of the epitaxial layer.
摘要翻译：本发明公开了一种沟槽肖特基势垒二极管（SBD）及其制造方法。沟槽SBD包括：形成在衬底上的外延层; 由多个沟槽限定的多个台面; 场板，形成在所述外延层上并填充在所述多个沟槽中，其中在所述场板和所述台面的顶表面之间形成肖特基接触; 终端区域，形成在多个台面之外并电连接到场板; 场隔离层，形成在上表面并位于端接区域外部; 以及形成在终端区域外的上表面下方的至少一个缓解电极，并且通过场隔离层电连接到场板，其中缓解电极和端接区域被介电层的一部分分隔开，外延层。

135. 发明申请

US20140187003A1 High Electron Mobility Transistor and Manufacturing Method Thereof 审中-公开
公开(公告)号：US20140187003A1
公开(公告)日：2014-07-03
申请号：US14201891
申请日：2014-03-09
申请人： Chih-Fang Huang , Chien-Wei Chiu , Ting-Fu Chang , Tsung-Yu Yang , Tsung-Yi Huang
发明人： Chih-Fang Huang , Chien-Wei Chiu , Ting-Fu Chang , Tsung-Yu Yang , Tsung-Yi Huang
IPC分类号： H01L29/66
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/41766 , H01L29/7787
摘要： The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT includes a semiconductor layer, a barrier layer on the semiconductor layer, a piezoelectric layer on the barrier layer, a gate on the piezoelectric layer, and a source and a drain at two sides of the gate respectively, wherein each bandgap of the semiconductor layer, the barrier layer, and the piezoelectric layer partially but not entirely overlaps the other two bandgaps. The gate is formed for receiving a gate voltage. A two dimensional electron gas (2DEG) is formed in a portion of a junction between the semiconductor layer and the barrier layer but not below at least a portion of the piezoelectric layer, wherein the 2DEG is electrically connected to the source and the drain.

136. 发明申请

US20140159111A1 SEMICONDUCTOR COMPOSITE FILM WITH HETEROJUNCTION AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有异质性的半导体复合膜及其制造方法
公开(公告)号：US20140159111A1
公开(公告)日：2014-06-12
申请号：US14048971
申请日：2013-10-08
申请人： Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang
发明人： Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang
IPC分类号： H01L21/02 , H01L29/12
CPC分类号： H01L29/205 , H01L21/02378 , H01L21/0242 , H01L21/0254 , H01L21/02664 , H01L21/30612 , H01L29/12 , H01L29/2003 , H01L29/7845 , H01L29/7849
摘要： The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.
摘要翻译：本发明公开了一种具有异质结的半导体复合膜及其制造方法。半导体复合膜包括：半导体衬底; 以及半导体外延层，其形成在所述半导体基板上，并且具有彼此相对的第一表面和第二表面，其中所述异质结形成在所述第一表面和所述半导体基板之间，并且其中所述半导体外延层进一步包括通过从第二表面朝向第一表面蚀刻半导体外延层而形成的至少一个凹部。该凹槽用于减轻半导体复合膜中的应变。

137. 发明申请

US20140151799A1 Double Diffused Drain Metal Oxide Semiconductor Device and Manufacturing Method Thereof 有权
标题翻译：双扩散漏极金属氧化物半导体器件及其制造方法
公开(公告)号：US20140151799A1
公开(公告)日：2014-06-05
申请号：US14173571
申请日：2014-02-05
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L21/823412 , H01L21/823418 , H01L27/088 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/66689 , H01L29/7816
摘要： The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively.
摘要翻译：本发明公开了一种双扩散漏极金属氧化物半导体（DDDMOS）器件及其制造方法。 DDDMOS器件形成在衬底中，并且包括第一阱，栅极，扩散区域，源极和漏极。在衬底中还形成低电压器件，该器件包括第二阱和轻掺杂漏极（LDD）区，其中第一阱和扩散区通过也形成第二阱的工艺步骤形成，并且LDD区域低压装置。

138. 发明申请

US20140120676A1 DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20140120676A1
公开(公告)日：2014-05-01
申请号：US14146548
申请日：2014-01-02
申请人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
发明人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
IPC分类号： H01L21/8234 , H01L29/66
CPC分类号： H01L29/4238 , H01L21/28114 , H01L21/823425 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/086 , H01L29/0865 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

139. 发明授权

US08710633B2 Semiconductor overlapped PN structure and manufacturing method thereof 有权
标题翻译：半导体重叠PN结构及其制造方法
公开(公告)号：US08710633B2
公开(公告)日：2014-04-29
申请号：US13864196
申请日：2013-04-16
申请人： Tsung-Yi Huang , Chien-Hao Huang , Ying-Shiou Lin
发明人： Tsung-Yi Huang , Chien-Hao Huang , Ying-Shiou Lin
IPC分类号： H01L29/06
CPC分类号： H01L29/06 , H01L21/266 , H01L29/0688 , H01L29/36
摘要： The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.
摘要翻译：本发明公开了半导体重叠PN结构及其制造方法。该方法包括：提供衬底; 提供第一掩模以限定所述衬底中的P（或N）型阱和至少一个重叠区域; 将P（或N）型杂质注入P（或N）型阱和至少一个重叠区域; 提供具有至少一个开口的第二掩模，以在所述衬底中限定N（或P）型阱，并且在所述至少一个重叠区域中限定至少一个双注入区域; 将N（或P）型杂质注入N（或P）型阱和至少一个双注入区，使得至少一个双注入区具有P型和N型杂质。

140. 发明授权

US08709900B1 Double diffused metal oxide semiconductor device and manufacturing method thereof 有权
公开(公告)号：US08709900B1
公开(公告)日：2014-04-29
申请号：US14146548
申请日：2014-01-02
申请人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
发明人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
IPC分类号： H01L21/336
CPC分类号： H01L29/4238 , H01L21/28114 , H01L21/823425 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/086 , H01L29/0865 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

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