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131. 发明授权

US06350559B1 Method for creating thinner resist coating that also has fewer pinholes 有权
标题翻译：创造也具有较少针孔的较薄抗蚀剂涂层的方法
公开(公告)号：US06350559B1
公开(公告)日：2002-02-26
申请号：US09398642
申请日：1999-09-17
申请人： Michael K. Templeton , Kathleen R. Early , Christopher F. Lyons
发明人： Michael K. Templeton , Kathleen R. Early , Christopher F. Lyons
IPC分类号： G03F700
CPC分类号： H01L21/312 , G03F7/168
摘要： In one embodiment, the present invention relates to a method of forming a thin photoresist layer having a low defect density, involving the steps of depositing a photoresist layer having a thickness from greater than about 0.5 &mgr;m to about 2 &mgr;m on a semiconductor substrate; and removing at least a portion of the photoresist layer to provide the thin photoresist layer having the low defect density and a thickness from about 0.1 &mgr;m to about 0.5 &mgr;m. In another embodiment, the present invention relates to a method of reducing pinhole defects in a thin photoresist layer having a thickness below about 0.5 &mgr;m comprising a photoresist material, involving the steps of depositing a layer of the photoresist material having a thickness greater than about 0.5 &mgr;m; and etching at least a portion of the photoresist material to provide the thin photoresist layer having the thickness below about 0.5 &mgr;m, wherein the thickness of the thin photoresist layer is about 90% or less than the thickness of the layer of the photoresist material.
摘要翻译：在一个实施方案中，本发明涉及一种形成具有低缺陷密度的薄的光致抗蚀剂层的方法，包括以下步骤：在半导体衬底上沉积厚度大于约0.5μm至约2μm的光致抗蚀剂层; 以及去除所述光致抗蚀剂层的至少一部分以提供具有低缺陷密度和约0.1μm至约0.5μm的厚度的薄光致抗蚀剂层。在另一个实施方案中，本发明涉及一种减少厚度低于约0.5μm的光致抗蚀剂薄层中的针孔缺陷的方法，该光致抗蚀剂层包括光致抗蚀剂材料，其包括以下步骤：沉积厚度大于约0.5μm的光致抗蚀剂材料层妈妈并蚀刻所述光致抗蚀剂材料的至少一部分以提供具有低于约0.5μm厚度的薄的光致抗蚀剂层，其中所述光致抗蚀剂层的厚度为所述光致抗蚀剂材料层的厚度的约90％或更小。

132. 发明授权

US06319843B1 Nitride surface passivation for acid catalyzed chemically amplified resist processing 有权
标题翻译：用于酸催化的化学放大抗蚀剂加工的氮化物表面钝化
公开(公告)号：US06319843B1
公开(公告)日：2001-11-20
申请号：US09328084
申请日：1999-06-08
申请人： Christopher F. Lyons
发明人： Christopher F. Lyons
IPC分类号： H01L21302
CPC分类号： H01L21/3105 , H01L21/312
摘要： In one embodiment, the present invention relates to a method of minimizing or preventing contamination of an acid catalyzed photoresist when using the acid catalyzed photoresist over a nitride containing film, involving contacting the nitride containing film with an oxidizing plasma comprising from about 1% to about 90% by volume of an oxygen containing gas and from about 10% to about 99% by volume of a forming gas prior to deposition of the acid catalyzed photoresist over the nitride containing film.
摘要翻译：在一个实施方案中，本发明涉及当在含氮化物膜上使用酸催化的光致抗蚀剂时，最小化或防止酸催化的光致抗蚀剂的污染的方法，包括使包含氮化物的膜与包含约1％至约 90％体积的含氧气体和约10％至约99％体积的成形气体，然后在含氮化物膜上沉积酸催化的光致抗蚀剂。

133. 发明授权

US06316277B1 Tuning substrate/resist contrast to maximize defect inspection sensitivity for ultra-thin resist in DUV lithography 失效
标题翻译：调整衬底/抗蚀剂对比度，以最大化DUV光刻中超薄抗蚀剂的缺陷检测灵敏度
公开(公告)号：US06316277B1
公开(公告)日：2001-11-13
申请号：US09580612
申请日：2000-05-30
申请人： Khoi A. Phan , Christopher F. Lyons , Khanh B. Nguyen , Jeff Schefske
发明人： Khoi A. Phan , Christopher F. Lyons , Khanh B. Nguyen , Jeff Schefske
IPC分类号： H01L2166
CPC分类号： H01L22/24
摘要： There is provided a method for enhancing the contrast between oxide film and ultra-thin resists in deep-ultraviolet lithography for use with a wafer defect inspection system in order to maximize defect inspection sensitivity. This is achieved by varying the thickness of the oxide film for a given ultra-thin resist thickness so as to produce a high contrast. As a result, defect inspection of the ultra-thin resist pattern is easily obtained. In a second embodiment, the ultra-thin resist thickness is varied for a given oxide film thickness. In a third embodiment, both the oxide film and the ultra-thin resist thicknesses are varied simultaneously so as to obtain an optimum contrast.
摘要翻译：提供了一种用于在深紫外线光刻中增强氧化膜和超薄抗蚀剂之间的对比度以与晶片缺陷检查系统一起使用以便最大化缺陷检查灵敏度的方法。这是通过改变给定的超薄抗蚀剂厚度的氧化膜的厚度来实现的，以产生高对比度。结果，容易获得超薄抗蚀剂图案的缺陷检查。在第二实施例中，对于给定的氧化膜厚度，超薄抗蚀剂厚度是变化的。在第三实施例中，氧化膜和超薄抗蚀剂厚度同时变化，以获得最佳对比度。

134. 发明授权

US06313019B1 Y-gate formation using damascene processing 有权
标题翻译：使用大马士革加工的Y型门形成
公开(公告)号：US06313019B1
公开(公告)日：2001-11-06
申请号：US09643343
申请日：2000-08-22
申请人： Ramkumar Subramanian , Christopher F. Lyons , Bhanwar Singh , Marina Plat
发明人： Ramkumar Subramanian , Christopher F. Lyons , Bhanwar Singh , Marina Plat
IPC分类号： H01L2144
CPC分类号： H01L21/28114 , H01L29/42376 , Y10S438/978
摘要： A method for fabricating a Y-gate structure is provided. The method comprises the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer, a first sacrificial layer over the protection layer and a second sacrificial layer over the first sacrificial layer. An inwardly sloping opening is formed in the second sacrificial layer and the opening is extended vertically in the first sacrificial layer. A contact material is deposited over the second sacrificial layer filling the opening with the contact material and forming a contact layer and portions of the contact material outside a gate region are removed. The first sacrificial layer and the second sacrificial layer are then removed.
摘要翻译：提供一种制造Y栅极结构的方法。该方法包括以下步骤：提供具有栅极氧化物层的硅层，栅极氧化物层上的保护层，保护层上的第一牺牲层和第一牺牲层上的第二牺牲层。在第二牺牲层中形成向内倾斜的开口，并且开口在第一牺牲层中垂直延伸。接触材料沉积在用接触材料填充开口的第二牺牲层上，并形成接触层，并且去除栅极区域外部的接触材料的部分。然后去除第一牺牲层和第二牺牲层。

135. 发明授权

US06214737B1 Simplified sidewall formation for sidewall patterning of sub 100 nm structures 失效
标题翻译：亚100 nm结构的侧壁图案的简化侧壁形成
公开(公告)号：US06214737B1
公开(公告)日：2001-04-10
申请号：US09234379
申请日：1999-01-20
申请人： Christopher F. Lyons , Michael K. Templeton , Kathleen R. Early
发明人： Christopher F. Lyons , Michael K. Templeton , Kathleen R. Early
IPC分类号： H01L213065
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/32139 , H01L21/76838
摘要： In one embodiment, the present invention relates to a method of forming a conductive structure having a width of about 100 nm or less, involving the steps of providing a substrate having a conductive film; patterning a mask over a first portion of the conductive film wherein a second portion of the conductive film is exposed; partially etching the second portion of the conductive film thereby forming a sidewall in the conductive film; removing the mask; depositing a sidewall film over the conductive film, the sidewall film having a vertical portion adjacent the sidewall of the conductive film and a horizontal portion in areas not adjacent the sidewall of the conductive film; removing the horizontal portion of the sidewall film exposing a third portion of the conductive film; and etching the third portion of the conductive film thereby providing the conductive structure having a width of about 100 nm or less underlying the vertical portion of the sidewall film.
摘要翻译：在一个实施例中，本发明涉及一种形成宽度为约100nm或更小的导电结构的方法，包括提供具有导电膜的基板的步骤; 在导电膜的第一部分上图案化掩模，其中导电膜的第二部分被暴露; 部分蚀刻导电膜的第二部分，从而在导电膜中形成侧壁; 去除面膜; 在所述导电膜上沉积侧壁膜，所述侧壁膜具有邻近所述导电膜的侧壁的垂直部分和在不邻近所述导电膜的侧壁的区域中的水平部分; 去除暴露导电膜的第三部分的侧壁膜的水平部分; 并且蚀刻导电膜的第三部分，从而提供具有在侧壁膜的垂直部分下方的约100nm或更小的宽度的导电结构。

136. 发明授权

US06200907B1 Ultra-thin resist and barrier metal/oxide hard mask for metal etch 有权
标题翻译：用于金属蚀刻的超薄抗蚀剂和阻挡金属/氧化物硬掩模
公开(公告)号：US06200907B1
公开(公告)日：2001-03-13
申请号：US09204216
申请日：1998-12-02
申请人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
发明人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
IPC分类号： H01L21302
CPC分类号： H01L21/32139 , H01L21/0275 , H01L21/0332 , H01L21/31111 , H01L21/31116 , H01L21/76838
摘要： In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a barrier metal layer over the oxide layer; depositing an ultra-thin photoresist over the barrier metal layer, the ultra-thin photoresist having a thickness less than about 2,000 Å; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the barrier metal layer; etching the exposed portion of the barrier metal layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.
摘要翻译：在一个实施例中，本发明涉及一种形成金属线的方法，包括以下步骤：提供包括金属层的半导体衬底，金属层上的氧化物层和氧化物层上的阻挡金属层; 在阻挡金属层上沉积超薄光致抗蚀剂，超薄光致抗蚀剂具有小于约的厚度; 用波长约250nm或更小的电磁辐射照射超薄光致抗蚀剂; 显影暴露一部分阻挡金属层的超薄光刻胶; 蚀刻暴露部分氧化物层的阻挡金属层的暴露部分; 蚀刻暴露出金属层的一部分的氧化物层的暴露部分; 并且蚀刻金属层的暴露部分从而形成金属线。

137. 发明授权

US06187666B1 CVD plasma process to fill contact hole in damascene process 有权
标题翻译： CVD等离子体工艺在镶嵌工艺中填充接触孔
公开(公告)号：US06187666B1
公开(公告)日：2001-02-13
申请号：US09328148
申请日：1999-06-08
申请人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
发明人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/312 , H01L21/76831 , H01L2221/1063
摘要： The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via, the protective material facilitating shielding of at least the edges and sidewalls of the via from a trench etch step. The trench etch step is performed to form a trench opening in the insulating material. The via and trench are filled with a conductive metal.
摘要翻译：本发明涉及在绝缘材料层中制造互连线和通孔的方法。在绝缘材料层中形成通孔。形成保护材料以至少与通孔的边缘和侧壁共形，所述保护材料有助于屏蔽通孔的至少边缘和侧壁至沟槽蚀刻步骤。执行沟槽蚀刻步骤以在绝缘材料中形成沟槽开口。通孔和沟槽填充有导电金属。

138. 发明授权

US06184128B2 Method using a thin resist mask for dual damascene stop layer etch 有权
标题翻译：使用薄抗蚀剂掩模的双镶嵌停止层蚀刻方法
公开(公告)号：US06184128B2
公开(公告)日：2001-02-06
申请号：US09497222
申请日：2000-01-31
申请人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
发明人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
IPC分类号： H01L214763
CPC分类号： H01L21/7681 , H01L21/31144
摘要： In one embodiment, the present invention relates to a dual damascene method involving the steps of providing a substrate having a first low k material layer; forming a first hard mask layer over the first low k material layer; patterning a first opening having a first width in the first hard mask layer using a first photoresist thereby exposing a portion of the first low k material layer; removing the first photoresist; depositing a second low k material layer over the patterned first hard mask layer and the exposed portion of the first low k material layer; forming a second hard mask layer over the second low k material layer; patterning a second opening having a width larger than the first width in the second hard mask layer using a second photoresist thereby exposing a portion of the second low k material layer; anisotropically etching the exposed portions of the first and second low k material layers; and removing the second photoresist, wherein and at least one of the first photoresist and the second photoresist have a thickness of about 1,500 Å or less.
摘要翻译：在一个实施例中，本发明涉及一种双镶嵌方法，包括以下步骤：提供具有第一低k材料层的基底; 在所述第一低k材料层上形成第一硬掩模层; 使用第一光致抗蚀剂构图在第一硬掩模层中具有第一宽度的第一开口，从而暴露第一低k材料层的一部分; 去除第一光致抗蚀剂; 在图案化的第一硬掩模层和第一低k材料层的暴露部分上沉积第二低k材料层; 在所述第二低k材料层上形成第二硬掩模层; 使用第二光致抗蚀剂构图在第二硬掩模层中形成具有大于第一宽度的宽度的第二开口，从而暴露第二低k材料层的一部分; 各向异性地蚀刻第一和第二低k材料层的暴露部分; 并且去除所述第二光致抗蚀剂，其中所述第一光致抗蚀剂和所述第二光致抗蚀剂中的至少一个具有大约等于或小于1500埃的厚度。

139. 发明授权

US5990524A Silicon oxime spacer for preventing over-etching during local interconnect formation 失效
标题翻译：硅肟间隔物，用于在局部互连形成期间防止过蚀刻
公开(公告)号：US5990524A
公开(公告)日：1999-11-23
申请号：US993868
申请日：1997-12-18
申请人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
发明人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
IPC分类号： H01L21/768 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/76895
摘要： During damascene formation of local interconnects in a semiconductor wafer, a punch-through region can be formed into the substrate as a result of exposing the oxide spacers that are adjacent to a transistor gate to one or more etching plasmas that are used to etch one or more overlying dielectric layers. A punch-through region can damage the transistor circuit. Improved, multipurpose spacers are provided to reduce the chances of over-etching. The multipurpose spacers are made of silicon oxime. The etching plasmas that are used to etch one or more overlying dielectric layers tend to have a higher selectivity ratio to the multipurpose spacers than to the conventional oxide spacers. Additionally, the multipurpose spacers do not tend to degrade the hot carrier injection (HCI) properties as would a typical nitride spacer.
摘要翻译：在半导体晶片中局部互连的镶嵌形成期间，由于将与晶体管栅极相邻的氧化物间隔物暴露于用于蚀刻一个或多个蚀刻等离子体的一个或多个蚀刻等离子体，可以将穿透区域形成为衬底，更重叠的电介质层。穿通区域可能会损坏晶体管电路。提供改进的多用途间隔件以减少过度蚀刻的机会。多用途间隔件由硅肟制成。用于蚀刻一个或多个上覆电介质层的蚀刻等离子体与常规氧化物间隔物相比往往具有比多用途间隔物更高的选择比。此外，多用途间隔物不会像典型的氮化物间隔物一样降低热载流子注入（HCl）性质。

140. 发明授权

US5963841A Gate pattern formation using a bottom anti-reflective coating 失效
标题翻译：使用底部抗反射涂层的栅格图案形成
公开(公告)号：US5963841A
公开(公告)日：1999-10-05
申请号：US924370
申请日：1997-09-05
申请人： Olov B. Karlsson , Christopher F. Lyons , Minh Van Ngo , Scott A. Bell , David K. Foote
发明人： Olov B. Karlsson , Christopher F. Lyons , Minh Van Ngo , Scott A. Bell , David K. Foote
IPC分类号： H01L21/3213 , H01L21/302
CPC分类号： H01L21/32139
摘要： A gate is formed on a semiconductor substrate by using a bottom anti-reflective coating (BARC) to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, a SiON BARC over the conductive layer, a thin oxide film over the SiON BARC. The resist mask is formed on the oxide film. The SiON BARC improves the resist mask formation process. The wafer stack is then shaped to form one or more polysilicon gates by sequentially etching through selected portions of the oxide film, the BARC, and the gate conductive layer as defined by the etch windows in the resist mask. Once properly shaped, the remaining portions of the resist mask, oxide film and SiON BARC are removed.
摘要翻译：通过使用底部抗反射涂层（BARC）在半导体衬底上形成栅极以更好地控制通过形成在其上的深UV抗蚀剂掩模所限定的栅极的临界尺寸（CD）。晶片堆叠包括半导体衬底上的栅极氧化物层，栅极氧化物层上的多晶硅栅极层，导电层上的SiON BARC，SiON BARC上的薄氧化物膜。在氧化物膜上形成抗蚀剂掩模。 SiON BARC改进了抗蚀剂掩模形成过程。然后通过依次蚀刻通过抗蚀剂掩模中由蚀刻窗口限定的氧化膜，BARC和栅极导电层的选定部分，将晶片堆叠成形以形成一个或多个多晶硅栅极。一旦适当成形，就去除了抗蚀剂掩模，氧化膜和SiON BARC的其余部分。

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