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131. 发明授权

US08935549B2 Microprocessor with multicore processor power credit management feature 有权
标题翻译：具有多核处理器功率信用管理功能的微处理器
公开(公告)号：US08935549B2
公开(公告)日：2015-01-13
申请号：US13157498
申请日：2011-06-10
申请人： G. Glenn Henry , Darius D. Gaskins , Stephan Gaskins
发明人： G. Glenn Henry , Darius D. Gaskins , Stephan Gaskins
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： A microprocessor includes an input that receives an indication of the amount of instantaneous power being supplied to the microprocessor by an external power source. The microprocessor includes a plurality of processing cores that each receive the indication from the input and responsively determine an amount of energy consumed by the microprocessor during a preceding period. The period is a predetermined length of time. Each processing core operates at a frequency above a predetermined frequency in response to determining that the amount of energy consumed by the microprocessor during the preceding period is less than a predetermined amount of energy. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined length of time without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the two or more processing cores to operate.
摘要翻译：微处理器包括一个输入，该输入接收由外部电源提供给微处理器的瞬时功率量的指示。微处理器包括多个处理核心，每个处理核心从输入端接收指示，并且响应地确定微处理器在前一时段期间消耗的能量的量。该期间是预定的时间长度。响应于确定微处理器在前一周期中消耗的能量的量小于预定量的能量，每个处理核心以高于预定频率的频率工作。预定频率可以是：所有核心可以在预定时间长度上操作而不使微处理器消耗大于预定量的能量的频率，或者替代地，系统软件可以请求两个或多个处理核心的最大频率操作。

132. 发明授权

US08930676B2 Master core discovering enabled cores in microprocessor comprising plural multi-core dies 有权
标题翻译：主核心发现在包括多个多核芯片的微处理器中启用的核心
公开(公告)号：US08930676B2
公开(公告)日：2015-01-06
申请号：US13299207
申请日：2011-11-17
申请人： G. Glenn Henry , Darius D. Gaskins
发明人： G. Glenn Henry , Darius D. Gaskins
IPC分类号： G06F15/16 , G06F1/32 , G06F15/17 , G06F9/44
CPC分类号： G06F1/3206 , G06F9/4403 , G06F15/16 , G06F15/17
摘要： A core configuration discovery method and corresponding microprocessor are provided that does not rely on off-core logic or queries by system BIOS. Reset microcode is provided in the microprocessor's cores. Upon reset, the microcode queries and/or receives from other cores configuration-revealing information and collects the configuration-revealing information to determine a composite core configuration for the microprocessor. The composite core configuration may reveal the number of enabled cores, identify the enabled cores, reveal a hierarchical coordination system of the multi-core processor, such as a nodal map of the cores for certain inter-core communication processes or restricted activities, identify various domains and domain masters within such a system, and/or identify resources, such as voltage sources, clock sources, and caches, shared by various domains of the microprocessor. The composite core configuration may be used for power state management, reconfiguration, and other purposes.
摘要翻译：提供了核心配置发现方法和相应的微处理器，其不依赖于系统BIOS的非核心逻辑或查询。微处理器核心中提供重置微码。复位时，微代码查询和/或从其他核心接收配置 - 显示信息并收集配置显示信息以确定微处理器的复合核心配置。复合核心配置可以显示启用的核心数量，识别启用的核心，揭示多核处理器的分层协调系统，例如用于某些核心间通信过程或受限活动的核心的节点映射，识别各种这样的系统中的域和域主机，和/或识别由微处理器的各个域共享的资源，例如电压源，时钟源和高速缓存。复合核心配置可用于电源状态管理，重新配置和其他目的。

133. 发明授权

US08914661B2 Multicore processor power credit management in which multiple processing cores use shared memory to communicate individual energy consumption 有权
标题翻译：多核处理器功率信用管理，其中多个处理核心使用共享存储器来传达单独的能量消耗
公开(公告)号：US08914661B2
公开(公告)日：2014-12-16
申请号：US13157436
申请日：2011-06-10
申请人： G. Glenn Henry , Darius D. Gaskins , Stephan Gaskins
发明人： G. Glenn Henry , Darius D. Gaskins , Stephan Gaskins
IPC分类号： G06F1/00 , G06F11/30 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： A microprocessor includes two or more processing cores each configured to compute a first value in response to detecting a power event. The first value represents an amount of energy the core consumed during a time interval leading up to the event. The length of the time interval is predetermined. Each core reads from the memory one or more second values that represent an amount of energy the other cores consume during approximately the time interval. The second values were previously computed and written to the memory by the other cores. Each core adjusts its operating frequency based on the first and second values. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined length of time without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the cores to operate.
摘要翻译：微处理器包括两个或多个处理核心，每个处理核心被配置为响应于检测到功率事件而计算第一值。第一个值表示核心在通向事件的时间间隔内消耗的能量。时间间隔的长度是预定的。每个核心从存储器读取一个或多个第二值，其表示在大约时间间隔期间其它核心消耗的能量的量。先前计算了第二个值，并通过其他内核将其写入存储器。每个核心根据第一和第二个值调整其工作频率。预定频率可以是：所有核心可以在预定时间长度上操作而不使微处理器消耗大于预定量的能量的频率，或者替代地，系统软件可以请求核心操作的最大频率。

134. 发明授权

US08910276B2 Apparatus and method for precluding execution of certain instructions in a secure execution mode microprocessor 有权
标题翻译：用于排除在安全执行模式微处理器中执行某些指令的装置和方法
公开(公告)号：US08910276B2
公开(公告)日：2014-12-09
申请号：US12263263
申请日：2008-10-31
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F21/00 , G06F21/72 , G06F21/70
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/12 , G06F21/14 , G06F21/554 , G06F21/70 , G06F21/71 , G06F21/73 , G06F21/74 , G06F21/75 , G06F21/82
摘要： An apparatus providing for a secure execution environment is presented. The apparatus includes a microprocessor and a secure non-volatile memory. The microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus, and where the secure application program is executed in a secure execution mode. The microprocessor has secure execution mode logic that is configured to monitor instructions within the secure application program, and that is configured to preclude execution of certain instructions. The secure non-volatile memory is coupled to the microprocessor via a private bus, and is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.
摘要翻译：提供了一种提供安全执行环境的设备。该装置包括微处理器和安全的非易失性存储器。微处理器被配置为执行非安全应用程序和安全应用程序，其中通过系统总线从系统存储器访问非安全应用程序，并且其中以安全执行模式执行安全应用程序。微处理器具有安全执行模式逻辑，其被配置为监视安全应用程序内的指令，并且被配置为排除某些指令的执行。安全非易失性存储器经由专用总线耦合到微处理器，并且被配置为存储安全应用程序，其中微处理器和安全非易失性存储器之间的专用总线上的事务与系统总线隔离，并且对应于微处理器内的系统总线资源。

135. 发明授权

US08856496B2 Microprocessor that fuses load-alu-store and JCC macroinstructions 有权
标题翻译：微处理器融合了load-alu-store和JCC宏指令
公开(公告)号：US08856496B2
公开(公告)日：2014-10-07
申请号：US13034808
申请日：2011-02-25
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30007 , G06F9/3004 , G06F9/30145 , G06F9/3017 , G06F9/3857 , G06F9/3861
摘要： A microprocessor receives first and second program-adjacent macroinstructions of the microprocessor instruction set architecture. The first macroinstruction loads an operand from a location in memory, performs an arithmetic/logic operation using the loaded operand to generate a result, and stores the result back to the memory location. The second macroinstruction jumps to a target address if condition codes satisfy a specified condition and otherwise executes the next sequential instruction. An instruction translator simultaneously translates the first and second program-adjacent macroinstructions into first, second, and third micro-operations for execution by execution units. The first micro-operation calculates the memory location address and loads the operand therefrom. The second micro-operation performs the arithmetic/logic operation using the loaded operand to generate the result, updates the condition codes based on the result, and jumps to the target address if the updated condition codes satisfy the condition. The third micro-operation stores the result to the memory location.
摘要翻译：微处理器接收微处理器指令集架构的第一和第二程序相邻宏指令。第一宏指令从存储器中的位置加载操作数，使用加载的操作数执行算术/逻辑运算以生成结果，并将结果存储回存储器位置。如果条件代码满足指定条件，则第二个宏指令跳转到目标地址，否则执行下一个顺序指令。指令翻译器同时将第一和第二程序相邻的宏指令转换为执行单元执行的第一，第二和第三微操作。第一个微操作计算存储器位置地址并从中加载操作数。第二微操作使用加载的操作数执行算术/逻辑运算，以生成结果，根据结果更新条件代码，如果更新的条件代码满足条件，则跳转到目标地址。第三个微操作将结果存储到内存位置。

136. 发明授权

US08700919B2 Switch key instruction in a microprocessor that fetches and decrypts encrypted instructions 有权
标题翻译：在提取和解密加密指令的微处理器中切换密钥指令
公开(公告)号：US08700919B2
公开(公告)日：2014-04-15
申请号：US13091547
申请日：2011-04-21
申请人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
发明人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
IPC分类号： G06F21/00
CPC分类号： H04L9/0827 , G06F9/30003 , G06F9/30079 , G06F9/30178 , G06F9/30189 , G06F12/0875 , G06F21/52 , G06F21/54 , G06F21/602 , G06F21/71 , G06F21/72 , G06F2212/402 , G06F2212/452 , G06F2221/2107 , H04L9/0618 , H04L9/0861 , H04L9/0891 , H04L9/0894 , H04L2209/12 , H04L2209/20
摘要： A fetch unit fetches a sequence of blocks of encrypted instructions of an encrypted program from an instruction cache at a corresponding sequence of fetch address values. While fetching each block of the sequence, the fetch unit generates a decryption key as a function of key values and the corresponding fetch address value, and decrypts the encrypted instructions using the generated decryption key by XORing them together. A switch key instruction instructs the microprocessor to update the key values in the fetch unit while the fetch unit is fetching the sequence of blocks. The fetch unit inherently provides an effective decryption key length that depends upon the function and amount of key values used. Including one or more switch key instructions within the encrypted program increases the effective decryption key length up to the encrypted program length.
摘要翻译：取出单元以相应的获取地址值序列从指令高速缓存中提取加密程序的加密指令的一系列块。在提取序列的每个块时，提取单元根据密钥值和相应的获取地址值产生解密密钥，并且通过将它们一起进行异或来解密加密的指令。切换键指令指示微处理器在获取单元获取块序列时更新提取单元中的键值。提取单元固有地提供了一个有效的解密密钥长度，这取决于所使用的密钥值的功能和数量。在加密程序中包括一个或多个切换密钥指令将有效的解密密钥长度增加到加密的程序长度。

137. 发明授权

US08639919B2 Tracer configuration and enablement by reset microcode 有权
标题翻译：示踪器配置和启用复位微码
公开(公告)号：US08639919B2
公开(公告)日：2014-01-28
申请号：US13293268
申请日：2011-11-10
申请人： G. Glenn Henry , Jason Chen
发明人： G. Glenn Henry , Jason Chen
IPC分类号： G06F9/00 , G06F9/24 , G06F9/44 , G06F15/177
CPC分类号： G06F11/36
摘要： A microprocessor is provided with a reset logic flag and corresponding reset microcode that selectively enables the reset microcode to set up and enable debug logic before the microprocessor subsequently fetches and executes user instructions. When the reset logic flag is set to a debug mode, the reset microcode configures and enables the microprocessor's debug logic before the microprocessor subsequently fetches and executes user instructions. When the reset logic flag is set to a normal mode, the reset microcode refrains from configuring and enabling the microprocessor's debug logic. The reset logic flag is indicated by an alterable fuse or a debugger-programmable scan register. Debug configuration initialization values are also provided by several alternative structures, including the reset microcode itself, alterable fuses, and debugger-programmable scan registers. Corresponding methods are also provided for configuring the debug logic of a microprocessor.
摘要翻译：微处理器被提供有复位逻辑标志和相应的复位微代码，其在微处理器随后提取和执行用户指令之前选择性地启用复位微代码来设置和使能调试逻辑。当复位逻辑标志被设置为调试模式时，复位微码在微处理器随后提取和执行用户指令之前配置并启用微处理器的调试逻辑。当复位逻辑标志设置为正常模式时，复位微代码不会配置和启用微处理器的调试逻辑。复位逻辑标志由可变保险丝或调试器可编程扫描寄存器指示。调试配置初始化值也由几种替代结构提供，包括复位微码本身，可变保险丝和调试器可编程扫描寄存器。还提供了相应的方法来配置微处理器的调试逻辑。

138. 发明申请

US20140013089A1 CONDITIONAL LOAD INSTRUCTIONS IN AN OUT-OF-ORDER EXECUTION MICROPROCESSOR 有权
标题翻译：不合格执行微处理器的条件负载指令
公开(公告)号：US20140013089A1
公开(公告)日：2014-01-09
申请号：US14007077
申请日：2012-04-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker , Gerard M. Col , Colin Eddy
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker , Gerard M. Col , Colin Eddy
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F9/30043 , G06F9/30072 , G06F9/30076 , G06F9/30174 , G06F9/30189
摘要： A microprocessor instruction translator translates a conditional load instruction into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives source operands from the source registers of a register file and responsively generates a first result using the source operands. To execute a second the microinstruction, an execution unit receives a previous value of the destination register and the first result and responsively reads data from a memory location specified by the first result and provides a second result that is the data if a condition is satisfied and that is the previous destination register value if not. The previous value of the destination register comprises a result produced by execution of a microinstruction that is the most recent in-order previous writer of the destination register with respect to the second microinstruction.
摘要翻译：微处理器指令转换器将条件加载指令转换成至少两个微指令。无序执行管线执行微指令。为了执行第一微指令，执行单元从寄存器堆的源寄存器接收源操作数，并使用源操作数响应地生成第一结果。为了执行微指令，执行单元接收目的地寄存器的先前值和第一结果，并响应于从第一结果指定的存储器位置读取数据，并且如果满足条件则提供作为数据的第二结果，这是以前的目标寄存器值，如果没有。目的地寄存器的先前值包括通过执行作为目的地寄存器相对于第二微指令的最新的有序先前的写入器的微指令而产生的结果。

139. 发明授权

US08522354B2 Microprocessor apparatus for secure on-die real-time clock 有权
标题翻译：用于安全的即插即用时钟的微处理器
公开(公告)号：US08522354B2
公开(公告)日：2013-08-27
申请号：US12263168
申请日：2008-10-31
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F12/14
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/12 , G06F21/14 , G06F21/554 , G06F21/70 , G06F21/71 , G06F21/73 , G06F21/74 , G06F21/75 , G06F21/82
摘要： An apparatus including a microprocessor and an external crystal. The microprocessor executes non-secure application programs and a secure application program, where the secure application program comprises instructions from a host architecture instruction set, and where the non-secure application programs are accessed from a system memory via a system bus and the secure application program is accessed from a secure non-volatile memory via a private bus coupled to the microprocessor. The microprocessor has a secure real time clock that provides a persistent time, where the secure real time clock is only visible and accessible by the secure application program when the microprocessor is executing in a secure mode. The external crystal is coupled to the secure real time clock within the microprocessor and is configured to cause an oscillator within the secure real time clock to generate an oscillating output voltage that is proportional to the frequency of the external crystal.
摘要翻译：一种包括微处理器和外部晶体的装置。微处理器执行非安全应用程序和安全应用程序，其中安全应用程序包括来自主机架构指令集的指令，并且其中通过系统总线和安全应用程序从系统存储器访问非安全应用程序通过耦合到微处理器的专用总线从安全的非易失性存储器访问程序。微处理器具有安全的实时时钟，其提供持久时间，其中安全实时时钟仅在微处理器以安全模式执行时由安全应用程序可见并可访问。外部晶体耦合到微处理器内的安全实时时钟，并被配置为使安全实时时钟内的振荡器产生与外部晶体频率成比例的振荡输出电压。

140. 发明授权

US08495344B2 Simultaneous execution resumption of multiple processor cores after core state information dump to facilitate debugging via multi-core processor simulator using the state information 有权
标题翻译：在核心状态信息转储后同时执行多个处理器核心，以便通过使用状态信息的多核处理器模拟器进行调试
公开(公告)号：US08495344B2
公开(公告)日：2013-07-23
申请号：US12748929
申请日：2010-03-29
申请人： G. Glenn Henry , Jui-Shuan Chen
发明人： G. Glenn Henry , Jui-Shuan Chen
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F11/00
CPC分类号： G06F9/3885 , G06F9/3861 , G06F11/3636
摘要： A multi-core microprocessor includes first and second processing cores and a bus coupling the first and second processing cores. The bus conveys messages between the first and second processing cores. The cores are configured such that: the first core stops executing user instructions and interrupts the second core via the bus, in response to detecting a predetermined event; the second core stops executing user instructions, in response to being interrupted by the first core; each core outputs its state after it stops executing user instructions; and each core waits to begin fetching and executing user instructions until it receives a notification from the other core via the bus that the other core is ready to begin fetching and executing user instructions. In one embodiment, the predetermined event comprises detecting that the first core has retired a predetermined number of instructions. In one embodiment, microcode waits for the notification.
摘要翻译：多核微处理器包括第一和第二处理核心以及耦合第一和第二处理核心的总线。总线在第一和第二处理核之间传送消息。核心被配置为：响应于检测到预定事件，第一核心停止执行用户指令并经由总线中断第二核心; 第二核心响应于被第一核心中断而停止执行用户指令; 每个核心在停止执行用户指令后输出其状态; 并且每个核心等待开始获取和执行用户指令，直到其经由总线从另一个核心接收到另一个核心准备开始获取和执行用户指令的通知。在一个实施例中，预定事件包括检测第一核已经退出预定数量的指令。在一个实施例中，微代码等待通知。

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