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131. 发明授权

US5932873A Capacitor-coupled bipolar active pixel sensor with integrated electronic shutter 失效
标题翻译：具有集成电子快门的电容耦合双极型有源像素传感器
公开(公告)号：US5932873A
公开(公告)日：1999-08-03
申请号：US932272
申请日：1997-09-17
申请人： Albert Bergemont , Min-Hwa Chi , Hosam Haggag , Carver Mead
发明人： Albert Bergemont , Min-Hwa Chi , Hosam Haggag , Carver Mead
IPC分类号： H01L27/146 , H01L31/11 , H01L21/00
CPC分类号： H01L31/1105 , H01L27/14681
摘要： A capacitor coupled bipolar phototransistor having an integrated electronic shutter for reducing the overflow and blooming problems associated with the imaging of strong images. Overflow control and an anti-blooming mechanism are obtained by use of a second emitter (the "shutter") which is used to remove excess image generated charge. This prevents the base-emitter junction potential from becoming forward biased during image integration when the phototransistor is exposed to a strong image. The shutter is biased slightly lower than the first emitter of the phototransistor so that the base-shutter junction is forward biased sooner than the base-emitter junction when the imaging element is exposed to a strong image. The overflow current of the generated holes is then drained to the shutter, rather than into the emitter where it would produce noise on the column sense line.
摘要翻译：具有集成电子快门的电容器耦合双极光电晶体管，用于减少与强图像成像有关的溢出和开花问题。通过使用用于去除多余图像产生的电荷的第二发射器（“快门”）来获得溢流控制和防喷射机制。这样就可以防止在光电晶体管暴露于强影像时图像积分期间基极 - 发射极结电位变得正向偏置。快门被偏置成比光电晶体管的第一发射极略低，以便当成像元件暴露于强影像时，基极 - 快门结点比基极 - 发射极结更早地向前偏置。所产生的孔的溢流电流然后被排放到快门，而不是进入发射器，在那里它会在列感测线上产生噪声。

132. 发明授权

US5908311A Method for forming a mixed-signal CMOS circuit that includes non-volatile memory cells 失效
标题翻译：用于形成包括非易失性存储单元的混合信号CMOS电路的方法
公开(公告)号：US5908311A
公开(公告)日：1999-06-01
申请号：US690203
申请日：1996-07-25
申请人： Min-hwa Chi , Chih-sieh Teng , Albert Bergemont
发明人： Min-hwa Chi , Chih-sieh Teng , Albert Bergemont
IPC分类号： H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A CMOS device that includes three-volt MOS transistor, five-volt MOS transistors, FLASH EPROM cells, poly resistors, and double-poly capacitors is formed in a single integrated CMOS process flow. The FLASH EPROM cells are formed as single-transistor memory cells that operate on low to very-low voltages.
摘要翻译：在单个集成CMOS工艺流程中形成包括三伏MOS晶体管，五伏MOS晶体管，FLASH EPROM单元，多晶硅电阻和双重多晶硅电容器的CMOS器件。 FLASH EPROM单元形成为在低至非常低的电压下工作的单晶体管存储单元。

133. 发明授权

US5847422A MOS-based active pixel sensor cell that utilizes the parasitic bipolar action of the cell to output image data 失效
标题翻译：基于MOS的有源像素传感器单元利用单元的寄生双极作用来输出图像数据
公开(公告)号：US5847422A
公开(公告)日：1998-12-08
申请号：US858509
申请日：1997-05-19
申请人： Min-Hwa Chi , Lih-Ying Ching , Albert Bergemont
发明人： Min-Hwa Chi , Lih-Ying Ching , Albert Bergemont
IPC分类号： H01L31/113 , H01L31/062 , H01L27/01 , H01L27/12
CPC分类号： H01L31/1136
摘要： A MOS-based active pixel sensor cell utilizes the parasitic bipolar action of the cell to produce a horizontal current in lieu of the vertical image current associated with conventional bipolar-based active pixel sensor cells. Image data is collected during an integration period by applying a negative voltage to the gate of the MOS transistor which is sufficient to reverse-bias both the source/body and drain/body junctions. Following this, the image data is read out by raising the gate voltage such that the source/body junction remains reverse-biased, and the drain/body junction becomes forward-biased. Under these bias conditions, an amplified horizontal image current flows from the source, through the body, and out of the drain.
摘要翻译：基于MOS的有源像素传感器单元利用单元的寄生双极作用来产生水平电流，代替与传统的基于双极的有源像素传感器单元相关联的垂直图像电流。在积分期间通过向MOS晶体管的栅极施加负电压来收集图像数据，其足以反向偏置源/体和漏/体结。此后，通过提高栅极电压来读出图像数据，使得源极/本体结保持反向偏置，并且漏极/主体结变为正向偏置。在这些偏压条件下，放大的水平图像电流从源极流过本体并流出漏极。

134. 发明授权

US5828102A Multiple finger polysilicon gate structure and method of making 失效
标题翻译：多指多晶硅门结构及其制作方法
公开(公告)号：US5828102A
公开(公告)日：1998-10-27
申请号：US940556
申请日：1997-09-30
申请人： Albert Bergemont
发明人： Albert Bergemont
IPC分类号： H01L23/482 , H01L29/423 , H01L29/768
CPC分类号： H01L23/4824 , H01L29/4238 , H01L2924/0002
摘要： Disclosed is a MOS transistor having a polysilicon gate structure in which an overlying metal interconnect completely shorts the gate area. In one embodiment, the gate is formed from multiple fingers joined in a serpentine pattern and separated by oxide-filled spaces. Overlying the fingers and oxide-filled spaces is an interconnect comprising a first metal layer and a second metal layer. The first metal layer overlies the fingers and oxide-filled spaces and the second metal layer overlies the first metal layer. Both metal layers form a stack that simultaneously shorts the fingers. Also disclosed is a method of fabricating such a polysilicon gate structure in a MOS transistor using a series of masks. Once the gate and fingers are defined, a conformal oxide is deposited over the fingers and in the spaces between the fingers. The conformal oxide is anisotropically etched to produce a planarized profile of the fingers and oxide-filled spaces. A metal interconnect is formed from a first metal layer and an overlying second metal layer by which all of the fingers are shorted simultaneously.
摘要翻译：公开了具有多晶硅栅极结构的MOS晶体管，其中上覆的金属互连完全使栅极区域短路。在一个实施例中，栅极由多个指状物形成，其以蛇形图案连接并被氧化物填充的空间分开。指状物和填充氧化物的空间覆盖着包括第一金属层和第二金属层的互连。第一金属层覆盖在手指和氧化物填充空间之间，第二金属层覆盖在第一金属层上。两个金属层形成一个同时使手指短路的叠层。还公开了使用一系列掩模在MOS晶体管中制造这种多晶硅栅极结构的方法。一旦门和手指被限定，保形氧化物沉积在手指之间和手指之间的空间中。各向异性蚀刻共形氧化物以产生手指和氧化物填充空间的平坦化轮廓。金属互连由第一金属层和上覆的第二金属层形成，通过该第二金属层，所有的指状物都同时短路。

135. 发明授权

US5814856A Variable and tunable V.sub.T MOSFET with poly and/or buried diffusion 失效
标题翻译：具有电容耦合的可变和可调谐VT MOSFET，由多晶硅和/或掩埋扩散耦合
公开(公告)号：US5814856A
公开(公告)日：1998-09-29
申请号：US857156
申请日：1997-05-15
申请人： Albert Bergemont , Min-hwa Chi
发明人： Albert Bergemont , Min-hwa Chi
IPC分类号： H01L29/788 , H01L29/76
CPC分类号： H01L29/7881 , H01L2924/0002
摘要： A MOSFET structure that utilizes self-aligned polysilicon and/or buried diffusion lines for coupling capacitors, provides a threshold voltage V.sub.T that is tunable from the control gate from positive (enhancement) to negative (depletion) by applying V.sub.cc to the bias gate and carefully designing the coupling ratio of the control gate and the bias gate. This scheme provides multiple V.sub.T 's on-chip without process complexity.
摘要翻译：利用自对准多晶硅和/或用于耦合电容器的掩埋扩散线的MOSFET结构通过将Vcc施加到偏置栅极并且仔细地提供阈值电压VT，其可以从控制栅极从正（增强）到负（耗尽）可调设计控制栅极和偏置栅极的耦合比。该方案提供了多个VT芯片，无需过程复杂性。

136. 发明授权

US5776795A Method of making a contactless capacitor-coupled bipolar active pixel sensor with intergrated electronic shutter 失效
标题翻译：制造具有集成电子快门的非接触电容耦合双极有源像素传感器的方法
公开(公告)号：US5776795A
公开(公告)日：1998-07-07
申请号：US923757
申请日：1997-09-02
申请人： Min-Hwa Chi , Albert Bergemont , Carver Mead
发明人： Min-Hwa Chi , Albert Bergemont , Carver Mead
IPC分类号： H01L27/146 , H01L31/11 , H01L21/00
CPC分类号： H01L27/14681 , H01L31/1105
摘要： A contactless capacitor coupled bipolar phototransistor having an integrated electronic shutter for reducing the overflow and blooming problems associated with the imaging of strong images. Overflow control and an anti-blooming mechanism are obtained by use of a second emitter (the "shutter") which is used to remove excess image generated charge. This prevents the base-emitter junction potential from becoming forward biased during image integration when the phototransistor is exposed to a strong image. The shutter is biased slightly lower than the first emitter of the phototransistor so that the base-shutter junction is forward biased sooner than the base-emitter junction when the imaging element is exposed to a strong image. The overflow current of the generated holes is then drained to the shutter, rather than into the emitter where it would produce noise on the column sense line.
摘要翻译：具有集成电子快门的非接触电容器耦合双极光电晶体管，用于减少与强图像成像有关的溢出和开花问题。通过使用用于去除多余图像产生的电荷的第二发射器（“快门”）来获得溢流控制和防喷射机制。这样就可以防止在光电晶体管暴露于强影像时图像积分期间基极 - 发射极结电位变得正向偏置。快门被偏置成比光电晶体管的第一发射极略低，以便当成像元件暴露于强影像时，基极 - 快门结点比基极 - 发射极结更早地向前偏置。所产生的孔的溢流电流然后被排放到快门，而不是进入发射器，在那里它会在列感测线上产生噪声。

137. 发明授权

US5760458A Bipolar-based active pixel sensor cell with poly contact and increased capacitive coupling to the base region 失效
标题翻译：基于双极的有源像素传感器单元，具有多接触和增加与基极区域的电容耦合
公开(公告)号：US5760458A
公开(公告)日：1998-06-02
申请号：US735025
申请日：1996-10-22
申请人： Albert Bergemont , Min-Hwa Chi
发明人： Albert Bergemont , Min-Hwa Chi
IPC分类号： H01L21/8249 , H01L27/146 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L21/8249 , H01L27/14609 , H01L27/14681
摘要： The dynamic range is increased and the noise level is reduced in a bipolar-based active pixel sensor cell with a capacitively coupled base region by forming the capacitor over a portion of the base region and the field oxide region of the cell. In addition, the noise levels are also reduced by heavily-doping the material which forms a portion of the bottom plate of the capacitor with the same conductivity type as the base region of the cell, and by placing the material which forms the portion of the bottom plate in direct contact with the base region.
摘要翻译：通过在电池的基极区域和场氧化物区域的一部分上形成电容器，动态范围增加，并且通过在具有电容耦合的基极区域的基于双极的有源像素传感器单元中降低噪声水平。此外，通过以与电池的基底区域相同的导电类型重叠掺杂形成电容器的底板的一部分的材料，并且通过将形成底板与基座区域直接接触。

138. 发明授权

US5753954A Single-poly neuron MOS transistor 失效
标题翻译：单多晶硅神经元MOS晶体管
公开(公告)号：US5753954A
公开(公告)日：1998-05-19
申请号：US684410
申请日：1996-07-19
申请人： Min-hwa Chi , Albert Bergemont
发明人： Min-hwa Chi , Albert Bergemont
IPC分类号： H01L21/336 , H01L27/115 , H01L29/788
CPC分类号： H01L29/66825 , H01L27/115 , H01L29/7881
摘要： A single-poly neuron transistor is formed by utilizing a series of doped substrate regions in lieu of the input gates that are conventionally used to form neuron transistors. With conventional neuron transistors, the input gates are isolated from the floating gate by a layer of interpoly dielectric. In the present invention, the series of doped substrate regions are isolated from the floating gate by a layer of gate oxide.
摘要翻译：通过利用一系列掺杂的衬底区域代替通常用于形成神经元晶体管的输入门来形成单聚聚神经元晶体管。使用传统的神经元晶体管，输入栅极通过一层多晶硅电介质与浮动栅极隔离。在本发明中，通过栅极氧化物层将一系列掺杂衬底区域从浮置栅极隔离开来。

139. 发明授权

US5615152A Method of erasing a high density contactless flash EPROM array 失效
标题翻译：擦除高密度非接触式闪存EPROM阵列的方法
公开(公告)号：US5615152A
公开(公告)日：1997-03-25
申请号：US648423
申请日：1996-05-15
申请人： Albert Bergemont
发明人： Albert Bergemont
IPC分类号： G11C16/04 , G11C16/16 , H01L27/115
CPC分类号： G11C16/0491 , G11C16/16 , H01L27/115
摘要： The present invention provides a contactless flash EPROM array formed in a P-well in a diffused silicon substrate of N-type conductivity. To facilitate a channel erase operation, thin tunnel oxide is formed between the P-well and the overlying polysilicon floating gate EPROM cells. The array is programmed in a conventional EPROM cell array manner. However, in accordance with the invention, the channel erase of a selected row of EPROM cells is accomplished by allowing all bit lines to float, applying a negative erase voltage to the word line of the selected row and holding the substrate at the supply voltage.
摘要翻译：本发明提供一种形成在N型导电性扩散硅衬底中的P阱中的非接触式闪存EPROM阵列。为了便于通道擦除操作，在P阱和上覆的多晶硅浮栅EPROM单元之间形成薄的隧道氧化物。阵列以常规的EPROM单元阵列方式编程。然而，根据本发明，通过允许所有位线浮动，将负的擦除电压施加到所选择的行的字线并将衬底保持在电源电压来实现所选行的EPROM单元的通道擦除。

140. 发明授权

US5590068A Ultra-high density alternate metal virtual ground ROM 失效
标题翻译：超高密度备用金属虚拟地面ROM
公开(公告)号：US5590068A
公开(公告)日：1996-12-31
申请号：US555257
申请日：1995-11-08
申请人： Albert Bergemont
发明人： Albert Bergemont
IPC分类号： H01L21/8246 , H01L27/112 , G11C13/00
CPC分类号： H01L27/112
摘要： An alternate metal ground (AMG) read only memory (ROM) includes an array of ROM data storage cells that are divided into segments. Each segment includes a plurality (typically 2.sup.x, e.g. 32 or 64) of word lines, a pair of segment select transistors for minimizing bit line capacitance when reading, and a pair of inner select transistors on each part of a segment to insure the connection between the connected diffusion but line and the intermediate non-connected diffusion bit line. That is, diffusion bit lines N-1, and N+1 are connected to metal bit lines via the segment select transistors. The diffusion bit lines between bit lines N-1, N and N+1 are not connected to metal bit lines. These non-connected intermediate bit lines are connected to ground via the inner or outer select transistors.
摘要翻译：备用金属接地（AMG）只读存储器（ROM）包括被划分成段的ROM数据存储单元的阵列。每个段包括多个（通常为2x，例如32或64）字线，一对用于在读取时最小化位线电容的段选择晶体管，以及一段内部选择晶体管，以确保段之间的连接连接的扩散但线和中间非连接的扩散位线。也就是说，扩散位线N-1和N + 1经由段选择晶体管连接到金属位线。位线N-1，N和N + 1之间的扩散位线不连接到金属位线。这些未连接的中间位线经由内部或外部选择晶体管连接到地。

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