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    • 121. 发明授权
    • Reducing power consumption in a wireless communication system
    • 降低无线通信系统的功耗
    • US09374782B2
    • 2016-06-21
    • US13450209
    • 2012-04-18
    • Yong LiuRaja Banerjea
    • Yong LiuRaja Banerjea
    • H04W52/02
    • H04W52/0216H04W28/08H04W52/0229Y02D70/142Y02D70/22
    • After transitioning a network interface of a first wireless communication device from a low power state to an active state, transmitting a request for a second wireless communication device to transmit data for the first wireless communication device that is buffered at the second wireless communication device. An indication of whether there is data for the first wireless communication device buffered at second wireless communication device is received. When there is data for the first wireless communication device buffered at second wireless communication device, data for the first wireless communication device that was buffered at the second wireless communication device is received from the second wireless communication device.
    • 在将第一无线通信设备的网络接口从低功率状态转换到活动状态之后,向第二无线通信设备发送对第二无线通信设备发送数据的第一无线通信设备的数据进行缓冲。 接收在第二无线通信设备中缓存的第一无线通信设备是否存在数据的指示。 当存在在第二无线通信设备中缓存的第一无线通信设备的数据时,从第二无线通信设备接收在第二无线通信设备处缓冲的第一无线通信设备的数据。
    • 123. 发明授权
    • High bandwidth configurable serial link
    • 高带宽可配置串行链路
    • US09355558B2
    • 2016-05-31
    • US14053111
    • 2013-10-14
    • Marvell World Trade Ltd.
    • Kapil JainSriharsha Annadore
    • G08C19/00
    • G08C19/00
    • Aspects of the disclosure provide an audio circuit that includes a clock circuit, a transmitting circuit, an audio data preparation circuit and a controller. The controller is configured to provide control signals to configure the transmitting circuit and the audio data preparation circuit according to one of a plurality of link protocol. The clock circuit is configured to provide a clock signal for bit transmission. The transmitting circuit is configured to transmit a bit in response to a transition edge of the clock signal according to the link protocol. The audio data preparation circuit is configured to insert audio data into a bit stream and provide the bit stream to the transmitting circuit according to the link protocol.
    • 本公开的方面提供了包括时钟电路,发送电路,音频数据准备电路和控制器的音频电路。 控制器被配置为提供控制信号,以根据多个链路协议之一配置发送电路和音频数据准备电路。 时钟电路被配置为提供用于位传输的时钟信号。 发送电路被配置为根据链路协议响应于时钟信号的转移边缘发送比特。 音频数据准备电路被配置为将音频数据插入到比特流中,并且根据链路协议将比特流提供给发送电路。