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121. 发明申请

US20120091593A1 STRUCTURE AND METHOD FOR SIMULTANEOUSLY FORMING A THROUGH SILICON VIA AND A DEEP TRENCH STRUCTURE 有权
标题翻译：同时形成通过硅和深层结构的硅的结构和方法
公开(公告)号：US20120091593A1
公开(公告)日：2012-04-19
申请号：US12904348
申请日：2010-10-14
申请人： Kangguo Cheng , Mukta G. Farooq , Louis L. Hsu
发明人： Kangguo Cheng , Mukta G. Farooq , Louis L. Hsu
IPC分类号： H01L23/538 , G06F17/50 , H01L21/768
CPC分类号： H01L27/0207 , G06F17/5081 , H01L21/743 , H01L21/76898
摘要： A through silicon via (TSV) and a deep trench capacitor (DTCap) or a deep trench isolation (DTI) are simultaneously formed on the same substrate by a single mask and a single reactive ion etching (RIE). The TSV trench is wider and deeper that the DTCap or DTI trench. The TSV and DTCap or DTI are formed with different dielectric materials on the trench sidewalls. The TSV and DTCap or DTI are perfectly aligned.
摘要翻译：通过单个掩模和单个反应离子蚀刻（RIE）同时在同一衬底上形成贯通硅通孔（TSV）和深沟槽电容器（DTCap）或深沟槽隔离（DTI）。 TSV沟槽比DTCap或DTI沟槽更宽更深。 TSV和DTCap或DTI在沟槽侧壁上形成有不同的介电材料。 TSV和DTCap或DTI完全对齐。

122. 发明授权

US07956466B2 Structure for interconnect structure containing various capping materials for electrical fuse and other related applications 有权
标题翻译：包含用于电熔丝和其他相关应用的各种封盖材料的互连结构的结构
公开(公告)号：US07956466B2
公开(公告)日：2011-06-07
申请号：US12118186
申请日：2008-05-09
申请人： Louis L. Hsu , William R. Tonti , Chih-Chao Yang
发明人： Louis L. Hsu , William R. Tonti , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L27/10 , H01L29/73 , H01L29/74
CPC分类号： H01L23/5256 , H01L21/76829 , H01L21/76838 , H01L21/76849 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.
摘要翻译：为包含用于电熔丝和其它相关应用的各种封盖材料的互连结构提供了一种设计结构。该结构包括具有第一界面结构的第一互连结构和与第一结构相邻的第二互连结构。第二互连结构具有与第一界面结构不同的第二界面结构。

123. 发明申请

US20090278228A1 DESIGN STRUCTURE FOR INTERCONNECT STRUCTURE CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS 有权
标题翻译：用于电气保险丝和其他相关应用的各种封装材料的互连结构设计结构
公开(公告)号：US20090278228A1
公开(公告)日：2009-11-12
申请号：US12118186
申请日：2008-05-09
申请人： Louis L. Hsu , William R. Tonti , Chih-Chao Yang
发明人： Louis L. Hsu , William R. Tonti , Chih-Chao Yang
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/76829 , H01L21/76838 , H01L21/76849 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.
摘要翻译：为包含用于电熔丝和其它相关应用的各种封盖材料的互连结构提供了一种设计结构。该结构包括具有第一界面结构的第一互连结构和与第一结构相邻的第二互连结构。第二互连结构具有与第一界面结构不同的第二界面结构。

124. 发明申请

US20090217961A1 Integrated Thermoelectric Cooling Devices and Methods for Fabricating Same 有权
标题翻译：集成热电冷却装置及其制造方法
公开(公告)号：US20090217961A1
公开(公告)日：2009-09-03
申请号：US12465419
申请日：2009-05-13
申请人： Howard Hao Chen , Richard C. Chu , Louis L. Hsu
发明人： Howard Hao Chen , Richard C. Chu , Louis L. Hsu
IPC分类号： H01L35/30
CPC分类号： H01L35/34 , H01L23/38 , H01L27/16 , H01L35/32 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： Semiconductor integrated thermoelectric devices are provided, which are formed having high-density arrays of thermoelectric (TE) elements using semiconductor thin-film and VLSI (very large scale integration) fabrication processes. Thermoelectric devices can be either separately formed and bonded to semiconductor chips, or integrally formed within the non-active surface of semiconductor chips, for example.
摘要翻译：提供半导体集成热电装置，它们使用半导体薄膜和VLSI（超大规模集成）制造工艺形成具有高密度阵列的热电（TE）元件。例如，热电器件可以单独形成并结合到半导体芯片，或者一体地形成在半导体芯片的非有源表面内。

125. 发明授权

US07499308B2 Programmable heavy-ion sensing device for accelerated DRAM soft error detection 有权
标题翻译：用于加速DRAM软错误检测的可编程重离子感测装置
公开(公告)号：US07499308B2
公开(公告)日：2009-03-03
申请号：US11689096
申请日：2007-03-21
申请人： Howard H. Chen , John A. Fifield , Louis L. Hsu , Henry H. K. Tang
发明人： Howard H. Chen , John A. Fifield , Louis L. Hsu , Henry H. K. Tang
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G01R31/31816 , G11C11/401 , G11C11/40615 , G11C11/4078 , G11C11/4091 , G11C29/026 , G11C29/028 , G11C29/50 , G11C29/52 , G11C2029/5002
摘要： Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with programmable sensing margin, refresh rate, and supply voltage to achieve various degree of SER sensitivity. In addition, a dual-mode DRAM array is proposed so that at least a portion of the array can be used to monitor high-energy particle activities during soft-error detection (SED) mode.
摘要翻译：本发明的方面涉及用于加速DRAM软错误检测的可编程重离子感测装置。优选将基于DRAM的α粒子感测装置的设计用作加速片上SER测试车辆。该感测装置具有可编程的感应余量，刷新率和电源电压，以达到SER灵敏度的各种程度。另外，提出了双模DRAM阵列，使得阵列的至少一部分可以用于在软错误检测（SED）模式期间监视高能量粒子活动。

126. 发明申请

US20080296728A1 SEMICONDUCTOR STRUCTURE FOR FUSE AND ANTI-FUSE APPLICATIONS 失效
标题翻译：用于保险丝和抗 - 保险丝应用的半导体结构
公开(公告)号：US20080296728A1
公开(公告)日：2008-12-04
申请号：US11755995
申请日：2007-05-31
申请人： Chih-Chao Yang , Daniel C. Edelstein , Jack A. Mandelman , Louis L. Hsu
发明人： Chih-Chao Yang , Daniel C. Edelstein , Jack A. Mandelman , Louis L. Hsu
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier.
摘要翻译：提供了一种保险丝/反熔丝结构，其中抗熔丝的编程由邻近熔丝元件形成的电动诱发小丘引起。小丘破裂位于熔丝元件的侧壁上的薄的扩散阻挡层，并且熔丝元件内的导电材料扩散到相邻的介电材料中。保险丝元件包括位于线路开口内的导电材料，该导电材料包括具有第一厚度的第一扩散阻挡层，位于侧壁上的第一厚度和线路开口的底壁。抗熔丝元件包括位于组合的通孔和线路开口内的导电材料，其包括位于组合的通路和线路开口的侧壁上的第一扩散阻挡层和具有大于第二扩散阻挡层的第二厚度的第二扩散阻挡层第一厚度位于第一扩散阻挡层上。

127. 发明申请

US20080280399A1 Methods for Forming Co-Planar Wafer-Scale Chip Packages 有权
标题翻译：形成共平面晶片尺寸芯片封装的方法
公开(公告)号：US20080280399A1
公开(公告)日：2008-11-13
申请号：US12121468
申请日：2008-05-15
申请人： Lloyd G. Burrell , Howard Hao Chen , Louis L. Hsu , Wolfgang Sauter
发明人： Lloyd G. Burrell , Howard Hao Chen , Louis L. Hsu , Wolfgang Sauter
IPC分类号： H01L21/00
CPC分类号： H01L23/5389 , H01L21/52 , H01L23/147 , H01L23/5385 , H01L2221/68322 , H01L2221/68345 , H01L2924/0002 , H01L2924/1433 , H01L2924/00
摘要： Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.
摘要翻译：提出了用于形成共面多芯片晶片级封装的经济方法。部分晶片接合和部分晶片切割技术用于制造芯片以及口袋。然后将完成的芯片安装在载体基板的相应凹穴中，并且芯片之间的全局互连形成在成品芯片的顶部平坦表面上。所提出的方法促进了用不同工艺步骤和材料制造的芯片的集成。不需要使用诸如化学机械抛光剂的平面化处理来平坦化芯片的顶表面。由于芯片精确地对准并且所有芯片都朝上安装，所以模块准备好进行全局布线，这消除了将芯片从倒置位置翻转的需要。

128. 发明申请

US20080229144A1 FLEXIBLE ROW REDUNDANCY SYSTEM 失效
标题翻译：灵活的冗余系统
公开(公告)号：US20080229144A1
公开(公告)日：2008-09-18
申请号：US12131307
申请日：2008-06-02
申请人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
发明人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
IPC分类号： G06F11/00
CPC分类号： G11C29/808
摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
摘要翻译：提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 其中所述复制逻辑模块被编程为根据可选择的修复字段大小将所述至少一个故障地址复制到对应于预定数量的存储体的行熔丝阵列中的行熔丝信息。

129. 发明授权

US07405108B2 Methods for forming co-planar wafer-scale chip packages 有权
标题翻译：用于形成共面晶片级芯片封装的方法
公开(公告)号：US07405108B2
公开(公告)日：2008-07-29
申请号：US10994494
申请日：2004-11-20
申请人： Lloyd G. Burrell , Howard Hao Chen , Louis L. Hsu , Wolfgang Sauter
发明人： Lloyd G. Burrell , Howard Hao Chen , Louis L. Hsu , Wolfgang Sauter
IPC分类号： H01L21/00
CPC分类号： H01L23/5389 , H01L21/52 , H01L23/147 , H01L23/5385 , H01L2221/68322 , H01L2221/68345 , H01L2924/0002 , H01L2924/1433 , H01L2924/00
摘要： Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.
摘要翻译：提出了用于形成共面多芯片晶片级封装的经济方法。部分晶片接合和部分晶片切割技术用于制造芯片以及口袋。然后将完成的芯片安装在载体基板的相应凹穴中，并且芯片之间的全局互连形成在成品芯片的顶部平坦表面上。所提出的方法促进了用不同工艺步骤和材料制造的芯片的集成。不需要使用诸如化学机械抛光剂的平面化处理来平坦化芯片的顶表面。由于芯片精确地对准并且所有芯片都朝上安装，所以模块准备好进行全局布线，从而不需要将芯片从倒置的位置翻转。

130. 发明授权

US07329939B2 Metal-insulator-metal capacitor and method of fabricating same 有权
标题翻译：金属绝缘体金属电容器及其制造方法
公开(公告)号：US07329939B2
公开(公告)日：2008-02-12
申请号：US11205719
申请日：2005-08-17
申请人： Louis L. Hsu , Rajiv V. Joshi , Chun-Yung Sung
发明人： Louis L. Hsu , Rajiv V. Joshi , Chun-Yung Sung
IPC分类号： H01L29/92
CPC分类号： H01G4/228 , H01G4/33 , H01L21/768 , H01L23/5223 , H01L28/60 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insultaing layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insultaing layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings. MIM capacitors and methods of fabricating same are described, wherein the MIM capacitors are formed simultaneously with the BEOL interconnect and large density MIM capacitors are fabricated at low cost.
摘要翻译：一种金属绝缘体金属（MIM）电容器，包括金属层，形成在金属层上的绝缘层，至少第一开口和形成在第一绝缘层中的至少第二开口，形成在第一开口中的电介质层沉积在第一和第二开口中的导电材料和形成在第一开口上的第一金属板和形成在第二开口上的第二金属板。一种制造MIM电容器的方法，包括形成第一金属层，在第一金属层上形成绝缘层，至少在第一绝缘层中形成第一开口和至少第二开口，在第二开口上沉积掩模在第一开口中形成电介质层，去除掩模，在第一和第二开口中沉积导电材料，并在第一和第二开口上沉积第二金属层。描述MIM电容器及其制造方法，其中MIM电容器与BEOL互连同时形成，并且以低成本制造大密度MIM电容器。

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