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121. 发明授权

US07466593B2 Non-volatile semiconductor memory device reading and writing multi-value data defined by a combination of different data levels of cells 失效
标题翻译：非易失性半导体存储器件读取和写入由不同数据级别的单元组合定义的多值数据
公开(公告)号：US07466593B2
公开(公告)日：2008-12-16
申请号：US11319568
申请日：2005-12-29
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C16/28
CPC分类号： G11C7/065 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/28 , G11C16/3459 , G11C2211/5621
摘要： A non-volatile semiconductor memory device includes: a memory cell array in which a plurality of electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to write M-value data (where, M is an integer equal to 4 or more) to pair-cells each constituted by simultaneously selected first and second memory cells connected to a pair of bit lines in the memory cell array, the M-value data being defined as a combination of different threshold levels of the first and second memory cells in M threshold levels to be set at each memory cell, and the M-value data stored in each pair-cell being read by sensing a difference between cell currents of the first and second memory cells; and a controller configured to control data write and read operations for the memory cell array.
摘要翻译：非挥发性半导体存储器件包括：存储单元阵列，其中布置有多个电可重写和非易失性存储单元; 一个读出放大器电路，被配置为将M值数据（其中，M是等于4或更大的整数）写入到由存储单元阵列中的一对位线连接的同时选择的第一和第二存储器单元构成的配对单元 M值数据被定义为要在每个存储单元设置的M个门限电平中的第一和第二存储器单元的不同阈值电平的组合，并且通过感测读取存储在每对单元中的M值数据第一和第二存储器单元的单元电流之间的差异; 以及控制器，被配置为控制所述存储单元阵列的数据写入和读取操作。

122. 发明授权

US07459715B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US07459715B2
公开(公告)日：2008-12-02
申请号：US11761318
申请日：2007-06-11
申请人： Haruki Toda , Koichi Kubo
发明人： Haruki Toda , Koichi Kubo
IPC分类号： H01L29/02 , G11C11/00
CPC分类号： G11C5/02 , G11C7/18 , G11C13/0004 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/126 , H01L45/1266 , H01L45/146 , H01L45/147 , Y10S439/936
摘要： A resistance change memory device including: a semiconductor substrate; cell arrays stacked above the substrate, bit lines and word lines; a read/write circuit formed on the semiconductor substrate; first and second vertical wirings connecting bit lines to the read/write circuit; and third vertical wirings connecting word lines to the read/write circuit, wherein the memory cell includes a variable resistance element. The variable resistance element has: a recording layer formed of a composite compound containing at least one transition element and a cavity site for housing a cation ion; and electrodes formed on the opposite sides of the recording layer, one of the electrodes serving as a cation source in a write or erase mode for supplying a cation to the recording layer to be housed in the cavity site therein.
摘要翻译：一种电阻变化存储器件，包括：半导体衬底; 堆叠在衬底上的单元阵列，位线和字线; 形成在半导体衬底上的读/写电路; 将位线连接到读/写电路的第一和第二垂直布线; 以及将字线连接到读/写电路的第三垂直布线，其中所述存储单元包括可变电阻元件。可变电阻元件具有：由包含至少一个过渡元素和用于容纳阳离子离子的空腔部位的复合化合物形成的记录层; 以及形成在记录层的相对侧上的电极，其中一个电极用作写入或擦除模式中的阳离子源，用于将阳离子供应到要容纳在其中的空腔位置的记录层。

123. 发明授权

US07453749B2 Semiconductor memory device with electrically rewritable and non-volatile memory cells arranged therein 失效
标题翻译：具有布置在其中的电可重写和非易失性存储单元的半导体存储器件
公开(公告)号：US07453749B2
公开(公告)日：2008-11-18
申请号：US11623907
申请日：2007-01-17
申请人： Toshihiro Suzuki , Haruki Toda
发明人： Toshihiro Suzuki , Haruki Toda
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C7/12 , G11C7/14 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C2207/2281
摘要： A semiconductor memory device includes: a cell array with electrically rewritable and non-volatile memory cells disposed at crossings between bit lines and word lines, which intersect with each other; a row decoder configured to drive the word lines; and a sense amplifier so coupled to a selected bit line as to compare a cell current with a reference current and sense data of a selected memory cell in the cell array, wherein bit line precharge is performed for a certain time prior to the sense amplifier activation in a data read mode while word line boost is performed in advance of the bit line precharge.
摘要翻译：一种半导体存储器件包括：具有电可重写和非易失性存储单元的单元阵列，其设置在位线和字线之间的交叉处，它们彼此相交; 配置为驱动所述字线的行解码器; 以及耦合到所选位线的读出放大器，以将单元电流与参考电流和单元阵列中的选定存储单元的感测数据进行比较，其中位线预充电在读出放大器激活之前一定时间被执行在数据读取模式下，在位线预充电之前执行字线升压。

124. 发明授权

US07369433B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07369433B2
公开(公告)日：2008-05-06
申请号：US11476023
申请日：2006-06-28
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C7/06 , G11C11/5642 , G11C16/0483 , G11C16/3445 , G11C16/3459
摘要： A semiconductor memory device includes: first and second cell arrays each having a plurality of memory cells; and a sense amplifier circuit for reading out data of the first and second cell arrays, wherein plural information cells and at least one reference cell are set in each of the first and second cell arrays, one of four data levels L0, L1, L2 and L3 (where, L0
摘要翻译：半导体存储器件包括：第一和第二单元阵列，每个具有多个存储单元; 以及用于读出第一和第二单元阵列的数据的读出放大器电路，其中在第一和第二单元阵列中的每一个中设置多个信息单元和至少一个参考单元，四个数据电平L 0，L 1，写入信息单元的L 2和L 3（其中，L 0

125. 发明申请

US20070285967A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20070285967A1
公开(公告)日：2007-12-13
申请号：US11761397
申请日：2007-06-12
申请人： Haruki Toda , Koichi Kubo
发明人： Haruki Toda , Koichi Kubo
IPC分类号： G11C11/36
CPC分类号： G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0014 , G11C13/0016 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate, each memory cell having a stack structure of a variable resistance element and an access element, the access element having such an off-state resistance value in a certain voltage range that is ten times or more as high as that in a select state; and a read/write circuit formed on the semiconductor substrate as underlying the cell array, wherein the variable resistance element comprises a recording layer formed of a first composite compound expressed by AxMyOz (where “A” and “M” are cation elements different from each other; “O” oxygen; and 0.5≦x≦1.5, 0.5≦y≦2.5 and 1.5≦z≦4.5) and a second composite compound containing at least one transition element and a cavity site for housing a cation ion.
摘要翻译：一种电阻变化存储器件，包括：半导体衬底; 形成在所述半导体衬底上的至少一个单元阵列，每个存储单元具有可变电阻元件和存取元件的堆叠结构，所述存取元件具有在十倍或更多的一定电压范围内的截止电阻值与选择状态一样高; 以及形成在半导体衬底上的单元阵列下面的读/写电路，其中，所述可变电阻元件包括由A x M y Y y表示的第一复合化合物形成的记录层，其中“A”和“M”是彼此不同的阳离子元素;“O”氧; 0.5 <= x <= 1.5,0.5 <= y <= 2.5和 1.5 <= z <= 4.5）和包含至少一个过渡元素和用于容纳阳离子离子的空腔部位的第二复合化合物。

126. 发明授权

US07154775B2 Magnetic random access memory 失效
标题翻译：磁性随机存取存储器
公开(公告)号：US07154775B2
公开(公告)日：2006-12-26
申请号：US10614814
申请日：2003-07-09
申请人： Yuui Shimizu , Haruki Toda
发明人： Yuui Shimizu , Haruki Toda
IPC分类号： G11C11/14
CPC分类号： G11C11/16
摘要： A magnetic random access memory includes a memory cell array in which memory cells, each having a magnetoresistive element as a storage element, are arranged, word lines respectively connected to rows of the memory cell array, bit lines respectively connected to columns of the memory cell array, row decoders to select the word lines, and a column decoder to select the bit lines. To determine the value of storage data, electrical characteristic values based on storage data stored in the plurality of memory cells are detected, reference data is continuously written in the plurality of memory cells, the reference data written in the plurality of memory cells is continuously read out to detect electrical characteristic values based on the reference data, and the electrical characteristic values based on the storage data are compared with those based on the reference data.
摘要翻译：磁性随机存取存储器包括一个存储单元阵列，其中排列有各自具有磁阻元件作为存储元件的存储单元，分别连接到存储单元阵列的行的字线，分别连接到存储单元的列的位线阵列，行解码器选择字线，以及列解码器来选择位线。为了确定存储数据的值，检测基于存储在多个存储单元中的存储数据的电特性值，将参考数据连续写入多个存储单元，写入多个存储单元的参考数据被连续读取基于参考数据检测电特性值，并将基于存储数据的电特性值与基于参考数据的电特性值进行比较。

127. 发明申请

US20060152979A1 Semiconductor memory device 失效
公开(公告)号：US20060152979A1
公开(公告)日：2006-07-13
申请号：US11299758
申请日：2005-12-13
申请人： Haruki Toda , Shozo Saito , Kaoru Tokushige
发明人： Haruki Toda , Shozo Saito , Kaoru Tokushige
IPC分类号： G11C7/00
CPC分类号： G11C7/1036 , G11C7/1018 , G11C7/1072 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C2207/107
摘要： A semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array has a plurality of memory cells arranged in rows and columns. The memory cells store data and are selected according to address signals. The control circuit is configured to receive a clock signal and a first control signal, and output a plurality of data in response to the clock signal after the first control signal is asserted. After the first control signal is asserted, an internal signal which responds to the clock signal transits N times (N is a positive integer and greater than or equal to 2), then output of the data is started. At least one of the data is output at the transition after the output begins.

128. 发明授权

US07061827B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07061827B2
公开(公告)日：2006-06-13
申请号：US10688881
申请日：2003-10-21
申请人： Haruki Toda , Shozo Saito , Kaoru Tokushige
发明人： Haruki Toda , Shozo Saito , Kaoru Tokushige
IPC分类号： G11C11/00
CPC分类号： G11C7/1036 , G11C7/1018 , G11C7/1072 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C2207/107
摘要： A semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array has a plurality of memory cells arranged in rows and columns. The memory cells store data and are selected according to address signals. The control circuit is configured to receive a clock signal and a first control signal, and output a plurality of data in response to the clock signal after the first control signal is asserted. After the first control signal is asserted, an internal signal which responds to the clock signal transits N times (N is a positive integer and greater than or equal to 2), then output of the data is started. At least one of the data is output at the transition after the output begins.
摘要翻译：半导体存储器件包括存储单元阵列和控制电路。存储单元阵列具有以行和列排列的多个存储单元。存储单元存储数据，并根据地址信号进行选择。控制电路被配置为接收时钟信号和第一控制信号，并且在第一控制信号被断言之后响应于时钟信号输出多个数据。在第一控制信号置位之后，响应时钟信号的内部信号转换N次（N为正整数，大于或等于2），则数据的输出开始。在输出开始后的转换中输出至少一个数据。

129. 发明申请

US20050111286A1 Clock-synchronous semiconductor memory device 失效
公开(公告)号：US20050111286A1
公开(公告)日：2005-05-26
申请号：US11023397
申请日：2004-12-29
申请人： Haruki Toda , Hitoshi Kuyama
发明人： Haruki Toda , Hitoshi Kuyama
IPC分类号： G11C7/10 , G11C8/04 , G11C8/00
CPC分类号： G11C8/04 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C2207/2254
摘要： A semiconductor device comprises a memory cell array, a control section and a latency setting circuit. The control section configured to receive a clock signal and a control signal, and configured to output a plurality of data in synchronism with the clock signal after the control signal is asserted. The latency setting circuit configured to set the latency N, and the latency setting circuit including at least one switch which fixes the latency by use of an externally supplied signal.

130. 发明授权

US06822917B2 Data write circuit in memory system and data write method 失效
标题翻译：数据写入电路在内存系统和数据写入方式
公开(公告)号：US06822917B2
公开(公告)日：2004-11-23
申请号：US10437256
申请日：2003-05-13
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C700
CPC分类号： G11C7/1096 , G11C7/1078 , G11C7/22 , G11C11/4076 , G11C2207/002 , G11C2207/229
摘要： There is disclosed a memory system including a memory cell array, a sense amplifier circuit, a write circuit, a level setting circuit, a column decoder, a data line, and a sense amplifier control circuit. The level setting circuit sets external input data to substantially the same level as a read potential difference level from the memory cell. The external input data whose level has been set by the level setting circuit is transferred to the sense amplifier selected by the column decoder via the data line. The sense amplifier control circuit activates the selected sense amplifier so as to write the external input data into the memory cell with substantially the same sequence as that at a data read time from the memory cell.
摘要翻译：公开了一种包括存储单元阵列，读出放大器电路，写入电路，电平设置电路，列解码器，数据线以及读出放大器控制电路的存储器系统。电平设置电路将外部输入数据设置为与来自存储单元的读取电位差电平基本相同的电平。电平已由电平设置电路设置的外部输入数据经由数据线传输到由列解码器选择的读出放大器。读出放大器控制电路激活所选择的读出放大器，以便以与从存储器单元的数据读取时间基本相同的顺序将外部输入数据写入存储单元。

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