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121. 发明授权

US06423599B1 Method for fabricating a field effect transistor having dual gates in SOI (semiconductor on insulator) technology 有权
标题翻译：在SOI（绝缘体上半导体）技术中制造具有双栅极的场效应晶体管的方法
公开(公告)号：US06423599B1
公开(公告)日：2002-07-23
申请号：US09846793
申请日：2001-05-01
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L29/78648
摘要： For fabricating a field effect transistor having dual gates, on a buried insulating layer in SOI (semiconductor on insulator) technology, a first layer of first semiconductor material is deposited on the buried insulating material. The first layer of first semiconductor material is patterned to form a first semiconductor island having a first top surface and a second semiconductor island having a second top surface. The first and second semiconductor islands are comprised of the first semiconductor material. An insulating material is deposited to surround the first and second semiconductor islands, and the insulating material is polished down until the first and second top surfaces of the first and second semiconductor islands are exposed such that sidewalls of the first and second semiconductor islands are surrounded by the insulating material. A gate dopant is implanted into the second semiconductor island. A layer of back gate dielectric material is deposited on the first and second top surfaces of the first and second semiconductor islands. An opening is patterned through the layer of back gate dielectric material above the first semiconductor island such that a bottom wall of the opening is formed by the first top surface of the first semiconductor island. A second layer of second semiconductor material is grown from the exposed first top surface of the first semiconductor island and onto the layer of back gate dielectric material. A front gate dielectric is formed over a portion of the second layer of second semiconductor material disposed over the second semiconductor island. A front gate electrode is formed over the front gate dielectric. The second semiconductor island forms a back gate electrode, and a portion of the layer of back gate dielectric material under the front gate dielectric forms a back gate dielectric.
摘要翻译：为了制造具有双栅极的场效应晶体管，在SOI（绝缘体上半导体）技术的掩埋绝缘层上，第一半导体材料层沉积在掩埋绝缘材料上。第一层第一半导体材料被图案化以形成具有第一顶表面的第一半导体岛和具有第二顶表面的第二半岛。第一和第二半导体岛由第一半导体材料组成。沉积绝缘材料以包围第一和第二半导体岛，并且绝缘材料被抛光直到第一和第二半导体岛的第一和第二顶表面被暴露，使得第一和第二半导体岛的侧壁被绝缘材料。将栅极掺杂剂注入第二半导体岛。一层背栅介质材料沉积在第一和第二半导体岛的第一和第二顶表面上。通过第一半导体岛上方的背栅介质材料层图案化开口，使得开口的底壁由第一半导体岛的第一顶表面形成。第二层第二半导体材料从第一半导体岛的暴露的第一顶表面生长到背栅电介质材料层上。在位于第二半导体岛上的第二半导体材料的第二层的一部分上形成前栅极电介质。前栅电极形成在前栅极电介质上。第二半导体岛形成背栅电极，并且在前栅极电介质下方的背栅介质材料层的一部分形成背栅电介质。

122. 发明授权

US06420767B1 Capacitively coupled DTMOS on SOI 有权
标题翻译：在SOI上电容耦合DTMOS
公开(公告)号：US06420767B1
公开(公告)日：2002-07-16
申请号：US09605920
申请日：2000-06-28
申请人： Srinath Krishnan , John C. Holst , Bin Yu
发明人： Srinath Krishnan , John C. Holst , Bin Yu
IPC分类号： H01L2976
CPC分类号： H01L29/78621 , H01L29/7841 , H01L29/78612
摘要： A transistor structure is provided comprising a source region having a N+ source region and a N− lightly doped source region. The structure also comprises a drain region having a N+ drain region and a N− lightly doped drain region. A P++ heavily doped region is provided. The P++ region resides alongside at least a portion of at least one of the N− lightly doped source region and N− lightly doped drain region. A P+ body region resides below a gate of the device and between the source and drain regions. The P+⇄ heavily doped region provides a capacitive coupling between a body region and the gate of the device and form a capacitive voltage divider with the junction capacitance of the device.
摘要翻译：提供一种晶体管结构，其包括具有N +源极区域和N-轻掺杂源极区域的源极区域。该结构还包括具有N +漏极区域和N-轻掺杂漏极区域的漏极区域。提供了P ++重掺杂区域。 P ++区域与N-轻掺杂源区域和N-轻掺杂漏极区域中的至少一个的至少一部分一起存在。 P +体区域位于器件的栅极之下以及源极和漏极区域之间。 P +⇄重掺杂区域在器件区域和器件的栅极之间提供电容耦合，并与器件的结电容形成电容分压器。

123. 发明授权

US06403981B1 Double gate transistor having a silicon/germanium channel region 有权
标题翻译：具有硅/锗沟道区的双栅极晶体管
公开(公告)号：US06403981B1
公开(公告)日：2002-06-11
申请号：US09633209
申请日：2000-08-07
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L2904
CPC分类号： H01L29/66916 , H01L29/66742 , H01L29/78639 , H01L29/78648 , H01L29/78687 , H01L29/802
摘要： A method of manufacturing an integrated circuit with a channel region containing germanium. The method includes providing an amorphous semiconductor material including germanium, crystallizing the amorphous semiconductor material, and doping to form a source location and a drain location. The semiconductor material containing germanium can increase the charge mobility associated with the transistor. A double gate structure can also be formed.
摘要翻译：一种制造具有含有锗的沟道区的集成电路的方法。该方法包括提供包括锗的非晶半导体材料，使非晶半导体材料结晶，并掺杂以形成源极位置和漏极位置。含锗的半导体材料可以增加与晶体管相关的电荷迁移率。也可以形成双栅极结构。

124. 发明授权

US06372659B1 Fabrication of metal oxide structure for a gate dielectric of a field effect transistor 有权
标题翻译：用于场效应晶体管的栅极电介质的金属氧化物结构的制造
公开(公告)号：US06372659B1
公开(公告)日：2002-04-16
申请号：US09661041
申请日：2000-09-14
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L2131
CPC分类号： H01L29/517 , H01L21/26506 , H01L21/2807 , H01L21/28079 , H01L21/28211 , H01L21/2822 , H01L21/31683 , H01L29/66583
摘要： For fabricating a metal oxide structure on a semiconductor substrate, an active device area is formed to be surrounded by at least one STI (shallow trench isolation) structure in the semiconductor substrate. A layer of metal is deposited on the semiconductor substrate, and the layer of metal contacts the active device area of the semiconductor substrate. A layer of oxygen blocking material is deposited on the layer of metal, and an opening is etched through the layer of oxygen blocking material to expose an area of the layer of metal on top of the active device area. An interfacial dopant is implanted through the layer of metal to the semiconductor substrate adjacent the layer of metal in the area of the opening where the layer of metal is exposed. A thermal oxidation process is performed to form a metal oxide structure from reaction of oxygen with the area of the opening where the layer of metal is exposed. A thickness of the metal oxide structure is determined by a thickness of the layer of metal, and the layer of oxygen blocking material prevents contact of oxygen with the layer of metal such that the metal oxide structure is formed localized at the area of the opening where the layer of metal is exposed. The interfacial dopant implanted in to the semiconductor substrate adjacent the layer of metal promotes adhesion of the metal oxide structure to the semiconductor substrate. In this manner, the metal oxide structure is formed by localized thermal oxidation of the layer of metal such that a deposition or sputtering process or an etching process is not necessary for formation of the metal oxide structure. In addition, the thickness of the metal oxide structure is determined by controlling the thickness of the layer of metal used for forming the metal oxide structure.
摘要翻译：为了在半导体衬底上制造金属氧化物结构，有源器件区域形成为被半导体衬底中的至少一个STI（浅沟槽隔离）结构包围。一层金属沉积在半导体衬底上，金属层与半导体衬底的有源器件区接触。一层氧阻塞材料沉积在金属层上，并且通过氧气阻挡材料层蚀刻开口以暴露有源器件区域顶部的金属层的区域。将界面掺杂剂通过金属层注入邻近金属层的金属层的暴露金属层的区域中的半导体衬底。进行热氧化处理以由氧与金属层暴露的开口区域的反应形成金属氧化物结构。金属氧化物结构的厚度由金属层的厚度确定，并且阻氧材料层防止氧与金属层的接触，使得金属氧化物结构形成在开口的区域金属层被暴露。注入到与金属层相邻的半导体衬底中的界面掺杂物促进了金属氧化物结构对半导体衬底的粘附。以这种方式，通过金属层的局部热氧化形成金属氧化物结构，使得形成金属氧化物结构不需要沉积或溅射工艺或蚀刻工艺。此外，通过控制用于形成金属氧化物结构的金属层的厚度来确定金属氧化物结构的厚度。

125. 发明授权

US06362055B1 Method of gate doping by ion implantation 失效
公开(公告)号：US06362055B1
公开(公告)日：2002-03-26
申请号：US09144527
申请日：1998-08-31
申请人： Ming-Ren Lin , Bin Yu
发明人： Ming-Ren Lin , Bin Yu
IPC分类号： H01L218234
摘要： A semiconductor device includes a first gate stack and a second gate stack, each gate stack corresponding to a gate of a FET formed on the semiconductor device. The first gate stack includes a gate material formed from one of poly-silicon, poly-SiGe, and amorphous silicon. The gate material is implanted with a dopant of a first conductivity type at a first concentration. A metal silicide layer is formed over the doped gate material. The second gate stack includes a gate material formed from one of poly-silicon, poly-Si—Ge, and amorphous silicon. The gate material of the second gate stack is implanted with a dopant of a second conductivity type at a second concentration.

126. 发明授权

US06361874B1 Dual amorphization process optimized to reduce gate line over-melt 有权
标题翻译：双非晶化工艺优化，以减少栅极线过熔
公开(公告)号：US06361874B1
公开(公告)日：2002-03-26
申请号：US09597623
申请日：2000-06-20
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/268 , H01L29/6659 , Y10T428/31906
摘要： A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region 300 nm thick. The shallow amorphous region can be between 10-15 nm below the top surface of the substrate, and the deep amorphous region can be between 150-200 nm below the top surface of the substrate. The process can reduce gate over-melting effects. The process can be utilized for P-channel or N-channel metal oxide semiconductor field effect transistors (MOSFETs).
摘要翻译：制造具有超浅源极/漏极结的集成电路的方法采用双非晶化技术。该技术产生了300nm厚的浅非晶区和深非晶区。浅非晶区域可以在衬底的顶表面之下10-15nm之间，并且深非晶区域可以在衬底顶表面之下的150-200nm之间。该过程可以减少栅极过熔效应。该过程可用于P沟道或N沟道金属氧化物半导体场效应晶体管（MOSFET）。

127. 发明授权

US06339017B1 Hard mask for integrated circuit fabrication 有权
标题翻译：用于集成电路制造的硬掩模
公开(公告)号：US06339017B1
公开(公告)日：2002-01-15
申请号：US09596993
申请日：2000-06-20
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L214763
CPC分类号： H01L29/6659 , H01L21/0337 , H01L21/0338 , H01L21/28035 , H01L21/28123 , H01L29/7833
摘要： A method of manufacturing small structures or narrow structures on an ultra-large scale integrated circuit utilizes a hard mask. A mask layer can be deposited over a top surface of a material above a semiconductor substrate. A mask layer can be lithographically patterned to have a feature. The side walls of the feature can be oxidized. The oxidized side walls can be removed to reduce the size of the feature below one lithographic feature. The material underneath mask layer can be etched in accordance with the feature without the oxidized side walls.
摘要翻译：在超大规模集成电路上制造小结构或窄结构的方法利用硬掩模。掩模层可沉积在半导体衬底上方的材料的顶表面上。掩模层可以光刻图案化以具有特征。特征的侧壁可以被氧化。可以去除氧化的侧壁以将特征的尺寸减小到低于一个光刻特征。掩模层下面的材料可以根据没有氧化侧壁的特征进行蚀刻。

128. 发明授权

US06297117B1 Formation of confined halo regions in field effect transistor 有权
标题翻译：场效应晶体管中限制晕圈的形成
公开(公告)号：US06297117B1
公开(公告)日：2001-10-02
申请号：US09781389
申请日：2001-02-12
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/26506 , H01L21/268 , H01L29/1083 , Y10S977/888
摘要： Halo regions are formed for a field effect transistor having a gate structure on a gate dielectric within an active device area of a semiconductor substrate. A first dummy spacer is formed on a first sidewall, and a second dummy spacer is formed on a second sidewall, of the gate structure and the gate dielectric. The first dummy spacer is disposed substantially over a drain extension junction, and the second dummy spacer is disposed substantially over a source extension junction of the field effect transistor. An insulating material is deposited to cover the first dummy spacer, the second dummy spacer, and the gate structure. The insulating material is polished down such that the top surfaces of the gate structure, the first dummy spacer, and the second dummy spacer are exposed and are level with a top surface of the insulating material. The first dummy spacer is etched away to form a first spacer opening, and the second dummy spacer is etched away to form a second spacer opening. A halo dopant is implanted through the first spacer opening to form a drain halo region substantially only beneath the drain extension junction within the semiconductor substrate and through the second spacer opening to form a source halo region substantially only beneath the source extension junction within the semiconductor substrate. The drain halo region and the source halo region are heated up in a thermal anneal process, such as a (LTP) laser thermal process, to activate the halo dopant substantially only within the drain halo region and the source halo region. An amorphization dopant may also be implanted into the drain halo region and the source halo region for activating the halo dopant within the drain and source halo regions at a lower temperature.
摘要翻译：为半导体衬底的有源器件区域内的栅极电介质上具有栅极结构的场效应晶体管形成光晕区域。第一虚拟间隔物形成在第一侧壁上，并且第二虚设间隔物形成在栅极结构和栅极电介质的第二侧壁上。第一虚拟间隔物基本上设置在漏极延伸结上方，并且第二虚拟间隔物基本上设置在场效应晶体管的源极延伸结上。沉积绝缘材料以覆盖第一虚拟间隔物，第二虚拟间隔物和栅极结构。绝缘材料被抛光，使得栅极结构的顶表面，第一虚设衬垫和第二虚拟衬垫露出并与绝缘材料的顶表面平齐。蚀刻掉第一虚拟间隔物以形成第一间隔开口，并且蚀刻掉第二虚拟间隔物以形成第二间隔开口。通过第一间隔开口注入卤素掺杂剂，以形成基本上仅在半导体衬底内的漏极延伸结下方的漏极晕区，并通过第二间隔开口，以形成基本上仅在半导体衬底内的源极延伸结下方的源极晕区。在诸如（LTP）激光热处理的热退火工艺中，将漏极晕区域和源极晕区域加热，以基本上仅在漏极晕区域和源极晕区域内激活卤素掺杂物。也可以将非晶化掺杂剂注入到漏极卤素区域和源极晕区域中，以在较低温度下激活漏极和源极区域内的卤素掺杂剂。

129. 发明授权

US06287925B1 Formation of highly conductive junctions by rapid thermal anneal and laser thermal process 有权
标题翻译：通过快速热退火和激光热处理形成高导电结
公开(公告)号：US06287925B1
公开(公告)日：2001-09-11
申请号：US09512202
申请日：2000-02-24
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/268 , H01L21/324 , H01L29/665 , H01L29/66545 , H01L29/6656
摘要： For forming a highly conductive junction in an active device area of a semiconductor substrate, a first dopant is implanted into the active device area to form a preamorphization region. A second dopant is then implanted into the preamorphization region to have a dopant profile along a depth of the preamorphization region, and the dopant profile has a dopant peak within the preamorphization region. A RTA (Rapid Thermal Anneal) is performed to recrystallize a portion of the preamorphization region from an interface between the preamorphization region and the semiconductor substrate to below the dopant peak. A LTP (Laser Thermal Process) is then performed to recrystallize a remaining portion of the preamorphization region that has not been recrystallized during the RTA (Rapid Thermal Anneal) to activate a substantial portion of the second dopant in the preamorphization region. In this manner, a relatively small portion of junction at the interface of the junction with the semiconductor substrate is recrystallized using a RTA (Rapid Thermal Anneal) process before the LTP (Laser Thermal Process). The interface of the junction with the semiconductor substrate that is recrystallized using a RTA (Rapid Thermal Anneal) has a minimized amount of crystallization defects such that the resistance of the junction is minimized. Such a highly conductive junction may be formed as a drain extension, a source extension, a drain contact junction, and a source contact junction of a field effect transistor for minimizing the series resistance at the drain and source of the field effect transistor and thus for enhancing the speed performance of the field effect transistor.
摘要翻译：为了在半导体衬底的有源器件区域中形成高导电结，将第一掺杂剂注入有源器件区域以形成预变形区域。然后将第二掺杂剂注入到预变质区域中以沿着预变质区域的深度具有掺杂剂分布，并且掺杂剂分布在预变形区域内具有掺杂剂峰。进行RTA（快速热退火）以使前变质区域的一部分从前变质区域和半导体衬底之间的界面重结晶到掺杂剂峰值以下。然后进行LTP（激光热处理）以使在RTA（快速热退火）期间未重结晶的剩余部分再结晶，以激活前变质区域中的大部分第二掺杂剂。以这种方式，在LTP（激光热处理）之前，使用RTA（快速热退火）工艺在与半导体衬底的结的界面处的相交处相对小的部分进行再结晶。使用RTA（快速热退火）重结晶的与半导体衬底的结的界面具有最小量的结晶缺陷，使得结的电阻最小化。这种高导电结可以形成为场效应晶体管的漏极延伸，源极延伸，漏极接触结和源极接触结，用于使场效应晶体管的漏极和源极处的串联电阻最小化，提高了场效应晶体管的速度性能。

130. 发明授权

US06284672B1 Method of forming a super-shallow amorphous layer in silicon 有权
标题翻译：在硅中形成超浅层非晶层的方法
公开(公告)号：US06284672B1
公开(公告)日：2001-09-04
申请号：US09260255
申请日：1999-03-02
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L21302
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/306
摘要： A method of manufacturing an integrated circuit is disclosed herein. The method includes providing an implant in a semiconductor to create an amorphous region; growing a thermal oxide layer on the amorphous region such that the thermal oxide layer consumes a portion of the amorphous region; and removing the thermal oxide layer such that the resulting amorphous region is super-shallow.
摘要翻译：本文公开了一种制造集成电路的方法。该方法包括在半导体中提供植入物以产生非晶区域; 在非晶区域上生长热氧化物层，使得热氧化物层消耗非晶区域的一部分; 并且去除热氧化物层，使得所得到的非晶区域是超浅的。

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