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121. 发明申请

US20120104578A1 Approach for Bonding Dies onto Interposers 有权
标题翻译：将模具粘合到插入物上的方法
公开(公告)号：US20120104578A1
公开(公告)日：2012-05-03
申请号：US13342583
申请日：2012-01-03
申请人： Hsien-Pin Hu , Chen-Hu Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
发明人： Hsien-Pin Hu , Chen-Hu Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
IPC分类号： H01L23/495
CPC分类号： H01L21/561 , H01L21/486 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/97 , H01L25/0655 , H01L2224/05001 , H01L2224/05027 , H01L2224/05571 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/05541 , H01L2224/05005 , H01L2224/05599 , H01L2224/05099
摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.
摘要翻译：一种方法包括提供包括衬底的中介层晶片，以及从衬底的前表面延伸到衬底中的多个贯通衬底通孔（TSV）。多个管芯结合到插入件晶片的前表面上。在结合多个模具的步骤之后，在基板的背面进行研磨以暴露多个TSV。多个金属凸块形成在插入器晶片的背面并电耦合到多个TSV。

122. 发明申请

US20080265378A1 Scribe line layout design 有权
标题翻译：划线设计
公开(公告)号：US20080265378A1
公开(公告)日：2008-10-30
申请号：US11796202
申请日：2007-04-27
申请人： Hsin-Hui Lee , Mirng-Ji Lii , Shin-Puu Jeng , Shang-Yun Hou
发明人： Hsin-Hui Lee , Mirng-Ji Lii , Shin-Puu Jeng , Shang-Yun Hou
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L23/585 , H01L2223/5442 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A scribe line layout design to reduce the damage caused by sawing the wafer is presented. An embodiment comprises metal plates located within the scribe lines and at least partially within the junctions of the scribe lines. Each of these metal plates has one or more slots to help relieve the pressure. Alternatively, instead of metal plates, grooves that may be filled with metal could be placed into the scribe lines. These metal plates could also be used concurrently with a seal ring for better protection during sawing.
摘要翻译：提出了一种划线设计，以减少锯切锯片造成的损坏。一个实施例包括位于划线内且至少部分地位于划线内的金属板。这些金属板中的每一个具有一个或多个槽以帮助减轻压力。或者，代替金属板，可以将填充有金属的凹槽放置在划线中。这些金属板也可以与密封环同时使用，以便在锯切期间更好地保护。

123. 发明授权

US07732897B2 Methods of die sawing and structures formed thereby 有权
标题翻译：模具切割的方法和由此形成的结构
公开(公告)号：US07732897B2
公开(公告)日：2010-06-08
申请号：US11424367
申请日：2006-06-15
申请人： Shin-Puu Jeng , Hao-Yi Tsai
发明人： Shin-Puu Jeng , Hao-Yi Tsai
IPC分类号： H01L23/544
CPC分类号： H01L21/78 , B28D5/022
摘要： A structure includes a substrate having a plurality of scribe line areas surrounding a plurality of die areas. Each of the die areas includes at least one first conductive structure formed over the substrate. Each of the scribe line areas includes at least one active region and at least one non-active region. The active region includes a second conductive structure formed therein. The structure further includes at least one first passivation layer formed over the first conductive structure and second conductive structure, wherein at least a portion of the first passivation layer within the non-active region is removed, whereby die-sawing damage is reduced.
摘要翻译：一种结构包括具有围绕多个管芯区域的多个划线区域的衬底。每个管芯区域包括形成在衬底上的至少一个第一导电结构。每个划线区域包括至少一个有效区域和至少一个非有源区域。有源区包括形成在其中的第二导电结构。该结构还包括形成在第一导电结构和第二导电结构之上的至少一个第一钝化层，其中非活性区域内的第一钝化层的至少一部分被去除，从而降低模切锯损坏。

124. 发明申请

US20100197114A1 Methods of die sawing 有权
标题翻译：模切方法
公开(公告)号：US20100197114A1
公开(公告)日：2010-08-05
申请号：US12798587
申请日：2010-04-06
申请人： Shin-Puu Jeng , Hao-Yi Tsai
发明人： Shin-Puu Jeng , Hao-Yi Tsai
IPC分类号： H01L21/78
CPC分类号： H01L21/78 , B28D5/022
摘要： A structure includes a substrate having a plurality of scribe line areas surrounding a plurality of die areas. Each of the die areas includes at least one first conductive structure formed over the substrate. Each of the scribe line areas includes at least one active region and at least one non-active region. The active region includes a second conductive structure formed therein. The structure further includes at least one first passivation layer formed over the first conductive structure and second conductive structure, wherein at least a portion of the first passivation layer within the non-active region is removed, whereby die-sawing damage is reduced.
摘要翻译：一种结构包括具有围绕多个管芯区域的多个划线区域的衬底。每个管芯区域包括形成在衬底上的至少一个第一导电结构。每个划线区域包括至少一个有效区域和至少一个非有源区域。有源区包括形成在其中的第二导电结构。该结构还包括形成在第一导电结构和第二导电结构之上的至少一个第一钝化层，其中非活性区域内的第一钝化层的至少一部分被去除，从而降低模切锯损坏。

125. 发明申请

US20070293019A1 METHODS OF DIE SAWING AND STRUCTURES FORMED THEREBY 有权
标题翻译：切割方法和形成的结构
公开(公告)号：US20070293019A1
公开(公告)日：2007-12-20
申请号：US11424367
申请日：2006-06-15
申请人： Shin-Puu Jeng , Hao-Yi Tsai
发明人： Shin-Puu Jeng , Hao-Yi Tsai
IPC分类号： H01L21/00
CPC分类号： H01L21/78 , B28D5/022
摘要： A structure includes a substrate having a plurality of scribe line areas surrounding a plurality of die areas. Each of the die areas includes at least one first conductive structure formed over the substrate. Each of the scribe line areas includes at least one active region and at least one non-active region. The active region includes a second conductive structure formed therein. The structure further includes at least one first passivation layer formed over the first conductive structure and second conductive structure, wherein at least a portion of the first passivation layer within the non-active region is removed, whereby die-sawing damage is reduced.
摘要翻译：一种结构包括具有围绕多个管芯区域的多个划线区域的衬底。每个管芯区域包括形成在衬底上的至少一个第一导电结构。每个划线区域包括至少一个有效区域和至少一个非有源区域。有源区包括形成在其中的第二导电结构。该结构还包括形成在第一导电结构和第二导电结构之上的至少一个第一钝化层，其中非活性区域内的第一钝化层的至少一部分被去除，从而降低模切锯损坏。

126. 发明授权

US08058151B2 Methods of die sawing 有权
标题翻译：模切方法
公开(公告)号：US08058151B2
公开(公告)日：2011-11-15
申请号：US12798587
申请日：2010-04-06
申请人： Shin-Puu Jeng , Hao-Yi Tsai
发明人： Shin-Puu Jeng , Hao-Yi Tsai
IPC分类号： H01L21/46 , H01L21/78 , H01L21/301
CPC分类号： H01L21/78 , B28D5/022
摘要： A structure includes a substrate having a plurality of scribe line areas surrounding a plurality of die areas. Each of the die areas includes at least one first conductive structure formed over the substrate. Each of the scribe line areas includes at least one active region and at least one non-active region. The active region includes a second conductive structure formed therein. The structure further includes at least one first passivation layer formed over the first conductive structure and second conductive structure, wherein at least a portion of the first passivation layer within the non-active region is removed, whereby die-sawing damage is reduced.
摘要翻译：一种结构包括具有围绕多个管芯区域的多个划线区域的衬底。每个管芯区域包括形成在衬底上的至少一个第一导电结构。每个划线区域包括至少一个有源区和至少一个非有源区。有源区包括形成在其中的第二导电结构。该结构还包括形成在第一导电结构和第二导电结构之上的至少一个第一钝化层，其中非活性区域内的第一钝化层的至少一部分被去除，从而降低模切锯损坏。

127. 发明授权

US07952453B2 Structure design for minimizing on-chip interconnect inductance 有权
标题翻译：用于最小化片上互连电感的结构设计
公开(公告)号：US07952453B2
公开(公告)日：2011-05-31
申请号：US12759836
申请日：2010-04-14
申请人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
IPC分类号： H01P3/08
CPC分类号： H01P3/08
摘要： A semiconductor device comprising a signal line and ground line is disclosed. The signal line comprises an opening and at least a portion of the ground line is in the opening in the signal line.
摘要翻译：公开了一种包括信号线和接地线的半导体器件。信号线包括开口，并且接地线的至少一部分在信号线中的开口中。

128. 发明申请

US20080076258A1 METHOD FOR FABRICATING AIR GAP FOR SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造半导体器件的空气隙的方法
公开(公告)号：US20080076258A1
公开(公告)日：2008-03-27
申请号：US11533809
申请日：2006-09-21
申请人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/7682 , H01L21/0206
摘要： A method for fabricating an interconnect structure in a semiconductor device. A masking layer is formed on a dielectric layer formed on a substrate, having at least one opening. The opening is transferred into the dielectric layer. A Plasma stripping process is performed to remove the masking layer, such that a damaged sidewall portion of the dielectric layer surrounding the opening therein is formed. The opening in the dielectric layer is filled with a conductive element. The damaged sidewall portion of the dielectric layer is removed to form a gap between the dielectric layer and the conductive element, wherein substances from removal of the damaged sidewall portion of the dielectric layer are formed on the conductive element. The substances are removed using a citric acid solution.
摘要翻译：一种在半导体器件中制造互连结构的方法。在形成在基板上的电介质层上形成有至少一个开口的掩模层。开口转移到电介质层中。进行等离子体剥离处理以去除掩模层，从而形成围绕其中的开口的电介质层的受损侧壁部分。电介质层中的开口填充有导电元件。去除电介质层损坏的侧壁部分，以形成电介质层和导电元件之间的间隙，其中去除导电元件上介质层损坏的侧壁部分的物质。使用柠檬酸溶液除去物质。

129. 发明申请

US20070166887A1 Semiconductor device structure and methods of manufacturing the same 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US20070166887A1
公开(公告)日：2007-07-19
申请号：US11333618
申请日：2006-01-17
申请人： Hsien-Wei Chen , Hsueh-Chung Chen , Yi-Lung Cheng , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Hsueh-Chung Chen , Yi-Lung Cheng , Shin-Puu Jeng
IPC分类号： H01L21/82
CPC分类号： H01L27/0203 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.
摘要翻译：提供了一种生成半导体器件阵列布局的方法。提供了第一布局，包括有源导电特征，围绕有源导电特征的边界区域以及除了有源导电特征和边界区域之外的开放区域。提供了多个不同图案密度的虚拟模板，每个虚拟模板包括多个虚拟种子。通过根据至少一个虚拟模板将假种子添加到开放区域来生成第二布局。

130. 发明申请

US20050205991A1 System and method of heat dissipation in semiconductor devices 有权
标题翻译：半导体器件散热系统和方法
公开(公告)号：US20050205991A1
公开(公告)日：2005-09-22
申请号：US10801475
申请日：2004-03-16
申请人： Hsien-Wei Chen , Jiun-Lin Yeh , Shin-Puu Jeng , Yi-Lung Cheng
发明人： Hsien-Wei Chen , Jiun-Lin Yeh , Shin-Puu Jeng , Yi-Lung Cheng
IPC分类号： H01L21/3205 , H01L21/44 , H01L21/768 , H01L21/82 , H01L23/34 , H01L23/433 , H01L23/52 , H01L23/528 , H01L27/04
CPC分类号： H01L23/528 , H01L21/76834 , H01L21/76837 , H01L23/4334 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method and system for heat dissipation in semiconductor devices. In one example, an integrated circuit semiconductor device includes a semiconductor substrate; one or more metallurgy layers connected to the semiconductor substrate, and each of the one or more metallurgy layers includes: one or more conductive lines; and one or more dummy structures between the one or more conductive lines and at least two of the one or more dummy structures are connected; and one or more dielectric layers between the one or more metallurgy layers.
摘要翻译：本公开提供了一种用于半导体器件中散热的方法和系统。在一个示例中，集成电路半导体器件包括半导体衬底; 连接到半导体衬底的一个或多个冶金层，并且所述一个或多个冶金层中的每一个包括：一个或多个导电线; 并且连接所述一个或多个导电线与所述一个或多个虚拟结构中的至少两个之间的一个或多个虚设结构; 以及一个或多个冶金层之间的一个或多个电介质层。

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