专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

121. 发明授权

US07560351B2 Integrated circuit arrangement with low-resistance contacts and method for production thereof 有权
标题翻译：具有低电阻触点的集成电路布置及其制造方法
公开(公告)号：US07560351B2
公开(公告)日：2009-07-14
申请号：US11324803
申请日：2006-01-03
申请人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht
发明人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht
IPC分类号： H01L21/336
CPC分类号： H01L29/41783 , H01L21/28518 , H01L29/41725 , H01L29/665 , H01L29/78 , Y10S438/964
摘要： An integrated circuit arrangement and fabrication method is presented. The integrated circuit arrangement contains a semiconductor and a metal electrode. The contact area between a semiconductor and the electrode is increased without increasing the lateral dimensions using partial regions of the semiconductor and/or of the electrode that extend through a transition layer between the semiconductor and electrode.
摘要翻译：提出了一种集成电路布置和制造方法。集成电路装置包含半导体和金属电极。使用延伸穿过半导体和电极之间的过渡层的半导体和/或电极的部分区域，增加半导体和电极之间的接触面积而不增加横向尺寸。

122. 发明授权

US07528425B2 Semiconductor memory with charge-trapping stack arrangement 失效
标题翻译：具有电荷俘获堆叠布置的半导体存储器
公开(公告)号：US07528425B2
公开(公告)日：2009-05-05
申请号：US11193026
申请日：2005-07-29
申请人： Michael Specht , Wolfgang Roesner , Franz Hofmann
发明人： Michael Specht , Wolfgang Roesner , Franz Hofmann
IPC分类号： H01L29/792
CPC分类号： H01L29/7887 , G11C16/0475 , H01L29/513 , H01L29/66833 , H01L29/7923
摘要： A semiconductor memory having a multitude of memory cells (21-1), the semiconductor memory having a substrate (1), at least one wordline (5-1), a first (15-1) and a second line (15-2; 16-1), wherein each of the multitude of memory cells (21-1) comprises a first doping region (6) disposed in the substrate (1), a second doping region (7) disposed in the substrate (1), a channel region (22) disposed in the substrate (1) between the first doping region (6) and the second doping region (7), a charge-trapping layer stack (2) disposed on the substrate (1), on the channel region (22), on a portion of the first doping region (6) and on a portion of the second doping region (7). Each memory cell (21-1) further comprises a conductive layer (3) disposed on the charge-trapping layer stack (2), wherein the conductive layer (3) is electrically floating. A dielectric layer (4) is disposed on a top surface of the conductive layer (3) and on sidewalls (23) of the conductive layer (3). The first line (15-1) extends along a first direction and is coupled to the first doping region (6), and the second line (15-2; 16-1) extends along the first direction and is coupled to the second doping region (7). The at least one wordline (5-1) extends along a second direction and is disposed on the dielectric layer (4).
摘要翻译：一种具有多个存储单元（21-1）的半导体存储器，所述半导体存储器具有衬底（1），至少一个字线（5-1），第一（15-1）和第二线（15-2） ; 16-1），其中多个存储单元（21-1）中的每一个包括设置在所述基板（1）中的第一掺杂区域（6），设置在所述基板（1）中的第二掺杂区域（7）设置在第一掺杂区域（6）和第二掺杂区域（7）之间的衬底（1）中的沟道区域（22），设置在衬底（1）上的电荷捕获层堆叠（2）在第一掺杂区域（6）的一部分上和第二掺杂区域（7）的一部分上的区域（22）。每个存储单元（21-1）还包括设置在电荷捕获层堆叠（2）上的导电层（3），其中导电层（3）是电浮置的。介电层（4）设置在导电层（3）的顶表面和导电层（3）的侧壁（23）上。第一行（15-1）沿着第一方向延伸并且耦合到第一掺杂区域（6），并且第二线路（15-2; 16-1）沿第一方向延伸并耦合到第二掺杂区域地区（7）。所述至少一个字线（5-1）沿着第二方向延伸并设置在所述电介质层（4）上。

123. 发明申请

US20080294413A1 PROGRAM PRODUCT SUPPORTING PHASE EVENTS IN A SIMULATION MODEL OF A DIGITAL SYSTEM 失效
标题翻译：在数字系统仿真模型中支持相关事件的程序产品
公开(公告)号：US20080294413A1
公开(公告)日：2008-11-27
申请号：US12130104
申请日：2008-05-30
申请人： GABOR BOBOK , Wolfgang Roesner , Derek E. Williams
发明人： GABOR BOBOK , Wolfgang Roesner , Derek E. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： According to a method of simulation processing, an instrumented simulation executable model of a design is built by compiling one or more hardware description language (HDL) files specifying one or more design entities within the design and one or more instrumentation entities and instantiating instances of the one or more instrumentation entities within instances of the one or more design entities. Operation of the design is then simulated utilizing the instrumented simulation executable model. Simulating operation includes each of multiple instantiations of the one or more instrumentation entities generating a respective external phase signal representing an occurrence of a particular phase of operation and instrumentation combining logic generating from external phase signals of the multiple instantiations of the one or more instrumentation entities an aggregate phase signal representing an occurrence of the particular phase.
摘要翻译：根据模拟处理的方法，通过编译指定设计中的一个或多个设计实体的一个或多个硬件描述语言（HDL）文件和一个或多个设备实体和一个或多个设备实例的实例化来构建设计的仪器化模拟可执行模型在一个或多个设计实体的实例内的一个或多个仪表实体。然后使用仪器化模拟可执行模型对设计的操作进行模拟。模拟操作包括一个或多个仪器实体的多个实例中的每个实例，其产生表示特定操作阶段的出现的相应的外部相位信号，以及组合从一个或多个仪器实体的多个实例的外部相位信号产生的逻辑聚合相位信号表示特定相位的出现。

124. 发明授权

US07453759B2 Clock-gated model transformation for asynchronous testing of logic targeted for free-running, data-gated logic 失效
标题翻译：用于针对自由运行，数据门控逻辑的逻辑的异步测试的时钟门控模型转换
公开(公告)号：US07453759B2
公开(公告)日：2008-11-18
申请号：US11380257
申请日：2006-04-26
申请人： Yee Ja , Bradley S. Nelson , Wolfgang Roesner
发明人： Yee Ja , Bradley S. Nelson , Wolfgang Roesner
IPC分类号： G11C8/00
CPC分类号： G06F17/504 , G06F17/5022 , G06F2217/62
摘要： Asynchronous behavior of a circuit is modeled by modifying latches in a netlist to add an extra port to the latches, e.g., a single-port latch is transformed into a dual-port latch. Each input port has an enable line and a data input. The data input in the added port is a feedback line from the latch output, and the enable line in the added port is the logical NOR of all of the original enable lines. By adding this extra latch port in the higher-level model, it becomes possible to introduce assertion logic to ensure that one and only one latch port for a given latch is ever active during the same simulation cycle. The model can then be tested earlier in the design methodology prior to the availability of the post-synthesis netlist. The model can also be used in both simulation and formal or semi-formal verification.
摘要翻译：电路的异步行为是通过修改网表中的锁存器来增加锁存器的额外端口来建模的，例如，单端口锁存器被转换成双端口锁存器。每个输入端口都有一个使能线和数据输入。添加端口中输入的数据是来自锁存器输出的反馈线，加入端口中的使能线为所有原始使能线的逻辑或。通过在更高级别的模型中添加这个额外的锁存端口，可以引入断言逻辑，以确保给定锁存器中的一个和唯一一个锁存端口在同一仿真周期内始终处于活动状态。然后可以在设计方法之前对该模型进行测试，然后才能获得后合成网表。该模型也可用于模拟和正式或半正式验证。

125. 发明申请

US20080021691A1 METHOD, SYSTEM AND PROGRAM PRODUCT SUPPORTING PRESENTATION OF A SIMULATED OR HARDWARE SYSTEM INCLUDING CONFIGURATION ENTITIES 有权
标题翻译：方法，系统和程序产品支持模拟或硬件系统的介绍，包括配置实体
公开(公告)号：US20080021691A1
公开(公告)日：2008-01-24
申请号：US11829447
申请日：2007-07-27
申请人： Wolfgang Roesner , Derek Williams
发明人： Wolfgang Roesner , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Within a display device, a respective one of a plurality of design graphical representations is displayed for each of a plurality of hierarchically arranged design entity instances within a simulated system. The design entity instances include a particular design entity instance containing a latch that is represented by a particular design graphical representation. A configuration entity instance associated with the particular design entity is identified within a configuration database associated with the simulated system. The configuration entity instance has a plurality of different settings that each reflects a value of the latch. Within the display device, a configuration graphical representation of the configuration entity instance is presented in association with the particular design graphical representation corresponding to the particular design entity instance. In addition, a current setting of the configuration entity instance is presented concurrently with the configuration graphical representation.
摘要翻译：在显示装置内，为模拟系统内的多个分层布置的设计实体实例中的每一个显示多个设计图形表示中的相应一个。设计实体实例包括包含由特定设计图形表示表示的锁存器的特定设计实体实例。在与模拟系统相关联的配置数据库中识别与特定设计实体相关联的配置实体实例。配置实体实例具有多个不同的设置，每个设置反映锁存器的值。在显示设备内，与对应于特定设计实体实例的特定设计图形表示相关联地呈现配置实体实例的配置图形表示。此外，配置实体实例的当前设置与配置图形表示同时呈现。

126. 发明授权

US07305639B2 Method and apparatus for specifying multiple voltage domains and validating physical implementation and interconnections in a processor chip 失效
标题翻译：用于指定多个电压域并验证处理器芯片中的物理实现和互连的方法和装置
公开(公告)号：US07305639B2
公开(公告)日：2007-12-04
申请号：US11055863
申请日：2005-02-11
申请人： Michael Stephen Floyd , Joshua David Friedrich , Elspeth Anne Huston , Wolfgang Roesner , Rick John Weiss
发明人： Michael Stephen Floyd , Joshua David Friedrich , Elspeth Anne Huston , Wolfgang Roesner , Rick John Weiss
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method, an apparatus and computer instructions are provided for specifying multiple voltage domains of a signal and macros in a processor chip and validating physical implementation and interconnections of the signal and macros. A set of attributes is provided for designs to define multiple voltage domains of a signal and macros in a processor chip. A first validation mechanism is then provided to validate that no electrical or logical errors created by logical connections between macros as defined by the set of attributes. A translation mechanism is provided to translate logical voltage description to a physical netlist for designers to connect powers to macros and signals. A second validation mechanism is provided to validate physical implementation adhere to designers' intent according to the set of attributes defined in the logical design.
摘要翻译：提供了一种用于指定处理器芯片中的信号和宏的多个电压域并验证信号和宏的物理实现和互连的方法，装置和计算机指令。提供了一组属性，用于设计以定义处理器芯片中的信号和宏的多个电压域。然后提供第一验证机制以验证由该属性集所定义的宏之间的逻辑连接所产生的电或逻辑错误。提供了一种翻译机制，用于将逻辑电压描述转换为物理网表，供设计师将功能连接到宏和信号。提供了第二个验证机制，以根据逻辑设计中定义的属性集来验证物理实现符合设计者的意图。

127. 发明申请

US20070174806A1 Method, system and program product providing a configuration specification language supporting arbitrary mapping functions for configuration constructs 有权
标题翻译：提供配置规范语言的方法，系统和程序产品，支持用于配置结构的任意映射功能
公开(公告)号：US20070174806A1
公开(公告)日：2007-07-26
申请号：US11408835
申请日：2006-04-21
申请人： Wolfgang Roesner , Derek Williams
发明人： Wolfgang Roesner , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of the digital design. In addition, a Dial is specified that defines a relationship between each of a plurality of input values and a respective one of a plurality of different output values. The HDL files also include a statement that instantiates an instance of the Dial in association with the configuration latch such that a one-to-one correspondence exists between a value contained within the configuration latch and an input value of the instance of the Dial. The HDL files further include a statement associating the Dial with a mapping function that applies a selected transformation to values read from or written to the instance of the Dial.
摘要翻译：公开了一种将映射函数与由一个或多个硬件描述语言（HDL）文件定义的数字设计的配置结构相关联的方法。根据该方法，在HDL文件中，在形成数字设计的至少一部分的设计实体内指定配置锁存器。此外，指定了一个Dial，其定义了多个输入值中的每一个与多个不同输出值中的相应的一个之间的关系。 HDL文件还包括一个语句，用于与配置锁存器相关联地实例化Dial的实例，使得在配置锁存器中包含的值与Dial的实例的输入值之间存在一一对应的对应关系。 HDL文件还包括将Dial与将映射功能相关联的语句，该映射函数将选择的变换应用于从Dial的实例读取或写入的值。

128. 发明申请

US20070083843A1 Method, system and program product for providing a configuration specification language supporting error checking dials 失效
标题翻译：方法，系统和程序产品，用于提供支持错误检查拨盘的配置说明语言
公开(公告)号：US20070083843A1
公开(公告)日：2007-04-12
申请号：US11245300
申请日：2005-10-06
申请人： Wolfgang Roesner , Robert Shadowen , Derek Williams
发明人： Wolfgang Roesner , Robert Shadowen , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A digital system includes one or more design entities containing a functional portion of the digital system. Within a configuration database, one or more configuration entities are instantiated. The configuration entities including an Error checking Dial (EDial) having a plurality of input latches within the digital design and a plurality of output latches within the digital design. The EDial has an associated function defining a relationship between values of the input latches and values of the output latches. An instance of the EDial in the configuration database is accessed to access the values of the output latches in the digital design.
摘要翻译：数字系统包括包含数字系统的功能部分的一个或多个设计实体。在配置数据库中，一个或多个配置实体被实例化。配置实体包括在数字设计中具有多个输入锁存器的错误检查拨号（EDial）和数字设计中的多个输出锁存器。 EDial具有定义输入锁存器的值和输出锁存器值之间的关系的相关函数。访问配置数据库中的EDial实例以访问数字设计中输出锁存器的值。

129. 发明申请

US20060190867A1 Method for reconfiguration of random biases in a synthesized design without recompilation 有权
标题翻译：在没有重新编译的情况下，在合成设计中重新配置随机偏差的方法
公开(公告)号：US20060190867A1
公开(公告)日：2006-08-24
申请号：US11050232
申请日：2005-02-03
申请人： Jason Baumgartner , Ali El-Zein , Daniel Heller , Wolfgang Roesner
发明人： Jason Baumgartner , Ali El-Zein , Daniel Heller , Wolfgang Roesner
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method, system and computer program product for performing testing and verification is disclosed. The method includes converting a bias data specification to a driver specification. The driver specification is then parsed into a base constraint and bias file, wherein the base constraint and bias file is suitable for conversion into one of a set comprising a netlist representation and a random simulation representation. A verification framework is selected from among a set comprising a random verification framework using the random simulation representation and a synthesized verification framework using the netlist representation. In response to selecting the random verification framework using the random simulation representation, the random simulation representation is compiled into a parameter database. In response to selecting the synthesized verification framework using the netlist representation, the netlist representation is compiled into a synthesized model. A property of at least one of a set of the synthesized model and the parameter database is tested and verified.
摘要翻译：公开了一种用于执行测试和验证的方法，系统和计算机程序产品。该方法包括将偏置数据规范转换为驱动器规范。然后将驱动器规范解析为基本约束和偏置文件，其中基本约束和偏置文件适于转换成包括网表表示和随机模拟表示的集合之一。从包括使用随机模拟表示的随机验证框架的集合和使用网表表示的合成验证框架中选择验证框架。响应于使用随机模拟表示法选择随机验证框架，随机模拟表示被编译成参数数据库。响应于使用网表表示来选择合成的验证框架，网表表示被编译成合成模型。测试和验证合成模型和参数数据库中的至少一个的属性。

130. 发明申请

US20060115978A1 Charge-trapping memory cell and method for production 有权
标题翻译：电荷俘获记忆体和生产方法
公开(公告)号：US20060115978A1
公开(公告)日：2006-06-01
申请号：US11000350
申请日：2004-11-30
申请人： Michael Specht , Wolfgang Roesner , Franz Hofmann
发明人： Michael Specht , Wolfgang Roesner , Franz Hofmann
IPC分类号： H01L21/4763
CPC分类号： H01L21/76895 , H01L21/28282 , H01L21/76897 , H01L27/105 , H01L27/11568 , H01L29/66833 , H01L29/7851 , H01L29/792
摘要： The memory cell array comprises a plurality of parallel fins provided as bitlines arranged at a distance of down to about 40 nm from one another and having a lateral dimension of less than about 30 nm, subdivided into pairs of adjacent first and second fins. A charge-trapping memory layer sequence is arranged on the fins. Wordlines are arranged across the fins, and source/drain regions are located in the fins between the wordlines and at the ends of the fins. There are preferably self-aligned contact areas of the source/drain regions at the ends of the fins, each contact area being common to the fins of one of said pairs. Select transistors and select lines are provided for the first and second fins individually to enable a separate addressing of the memory cells.
摘要翻译：存储单元阵列包括多个平行翅片，它们设置成彼此相距约40nm的位线，并且具有小于约30nm的横向尺寸，被细分成相邻的第一和第二鳍片对。鳍片上布置有电荷俘获记忆层序列。词汇排列在翅片之间，源极/漏极区域位于字线之间的翅片和翅片的末端。优选地，在鳍片的端部处的源极/漏极区域的自对准接触区域，每个接触区域对于所述成对中的一个的翅片是共同的。选择晶体管，并且单独地为第一和第二散热片提供选择线以使得能够单独寻址存储器单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式