专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

121. 发明申请

US20070029345A1 Method and structure for mixing different materials 有权
标题翻译：混合不同材料的方法和结构
公开(公告)号：US20070029345A1
公开(公告)日：2007-02-08
申请号：US10584094
申请日：2004-11-05
申请人： Jeong Min Lee , Seong Jae Lee
发明人： Jeong Min Lee , Seong Jae Lee
IPC分类号： B67D5/60
CPC分类号： B01F3/12 , B01F15/0205 , B01F15/0215 , B01F15/0224 , B01F2215/0022 , B65D51/2835 , B65D51/2864 , B65D51/2878 , Y10S215/08
摘要： A structure for mixing different materials includes a main body having a lip portion with an upper opening portion, the main body coupled to an opening of a container containing a first material; a spouting guide member movably inserted in the lip portion by a predetermined distance; a cap ascending and descending together with the spouting guide member, the cap being coupled to the main body; and a seal closer separately formed on a lower portion of the spouting guide member.
摘要翻译：用于混合不同材料的结构包括主体，其具有带有上开口部分的唇部，主体联接到容纳第一材料的容器的开口; 喷射引导构件，其可移动地插入所述唇部中预定距离; 与喷射引导构件一起上升和下降的盖，所述盖联接到所述主体; 以及分开形成在喷射引导构件的下部上的密封件。

122. 发明申请

US20070012580A1 Method and structure for mixing different materials in the pouch container 失效
标题翻译：在容器中混合不同材料的方法和结构
公开(公告)号：US20070012580A1
公开(公告)日：2007-01-18
申请号：US10584107
申请日：2004-11-09
申请人： Jeong-Min Lee , Seong-Jae Lee
发明人： Jeong-Min Lee , Seong-Jae Lee
IPC分类号： B65D25/08 , B65D1/04
CPC分类号： B65D51/2878 , B01F11/0005 , B01F15/00512 , B01F15/0205 , B01F15/0212 , B65D51/225 , B65D51/226 , B65D51/227 , B65D51/2835 , B65D51/2871 , B65D75/5866 , B65D2251/0015 , B65D2251/0025 , B65D2251/0093
摘要： A structure for mixing different materials in a pouch container includes a spout main body provided with a spout hole through which mixture of first and second materials is exhausted; a cap removably coupled on an outer portion of the spout hole and storing the first material therein; and a seal member coupled to a lower end of the tube portion.
摘要翻译：用于将不同材料混合在袋容器中的结构包括：喷口主体，其设置有第一和第二材料的混合物排出的喷口; 盖子，其可移除地联接在所述喷口孔的外部部分上，并将所述第一材料存储在其中; 以及联接到所述管部的下端的密封构件。

123. 发明申请

US20060180867A1 Field effect transistor and method of fabricating the same 有权
公开(公告)号：US20060180867A1
公开(公告)日：2006-08-17
申请号：US11400520
申请日：2006-04-10
申请人： Won-ju Cho , Chang-geun Ahn , Ki-ju Im , Jong-heon Yang , In-bok Baek , Seong-jae Lee
发明人： Won-ju Cho , Chang-geun Ahn , Ki-ju Im , Jong-heon Yang , In-bok Baek , Seong-jae Lee
IPC分类号： H01L21/336 , H01L29/94
CPC分类号： H01L29/7835 , H01L29/41783 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66659 , H01L29/7834
摘要： Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of the present invention, a source junction and a drain junction are thin, and the overlap between the source and the gate and between the drain and the gate is prevented, thereby lowering parasitic resistance. Further, the gate electric field is easily introduced to the drain extending region, so that the carrier concentration is effectively controlled in the channel at the drain. Also, the drain extending region is formed to be thinner than the source, so that the short channel characteristic is excellent.

124. 发明授权

US06693294B1 Schottky barrier tunnel transistor using thin silicon layer on insulator and method for fabricating the same 失效
标题翻译：使用绝缘体上的薄硅层的肖特基势垒隧道晶体管及其制造方法
公开(公告)号：US06693294B1
公开(公告)日：2004-02-17
申请号：US10331945
申请日：2002-12-31
申请人： Moon-Gyu Jang , Seong-Jae Lee , Woo-Seok Cheong , Won-Ju Cho , Kyoung-Wan Park
发明人： Moon-Gyu Jang , Seong-Jae Lee , Woo-Seok Cheong , Won-Ju Cho , Kyoung-Wan Park
IPC分类号： H01L3900
CPC分类号： H01L29/42384 , H01L29/458 , H01L29/7839 , H01L29/78609 , H01L29/78696
摘要： Provided are a Schottky barrier tunnel transistor (SBTT) and a method of fabricating the same. The SBTT includes a buried oxide layer formed on a base substrate layer and having a groove at its upper surface; an ultra-thin silicon-on-insulator (SOI) layer formed across the groove; an insulating layer wrapping the SOI layer on the groove; a gate formed to be wider than the groove on the insulating layer; source and drain regions each positioned at both sides of the gate, the source and drain regions formed of silicide; and a conductive layer for filling the groove. In the SBTT, the SOI layer is formed to an ultra-thin thickness to minimize the occurrence of a leakage current, and a channel in the SOI layer below the gate is completely wrapped by the gate and the conductive layer, thereby improving the operational characteristics of the SBTT.
摘要翻译：提供了一种肖特基势垒隧道晶体管（SBTT）及其制造方法。 SBTT包括形成在基底层上并在其上表面具有凹槽的掩埋氧化物层; 跨越沟槽形成的超薄绝缘体上硅（SOI）层; 将SOI层包裹在槽上的绝缘层; 形成为比绝缘层上的沟槽宽的栅极; 源极和漏极区域各自位于栅极的两侧，源极和漏极区域由硅化物形成; 以及用于填充凹槽的导电层。在SBTT中，SOI层形成为超薄的厚度，以最小化泄漏电流的发生，栅极下方的SOI层中的沟道被栅极和导电层完全包围，从而提高了操作特性的SBTT。

125. 发明授权

US06620668B2 Method of fabricating MOS transistor having shallow source/drain junction regions 失效
标题翻译：制造具有浅源极/漏极结区域的MOS晶体管的方法
公开(公告)号：US06620668B2
公开(公告)日：2003-09-16
申请号：US10117001
申请日：2002-04-05
申请人： Seong-jae Lee , Won-ju Cho , Kyoung-wan Park
发明人： Seong-jae Lee , Won-ju Cho , Kyoung-wan Park
IPC分类号： H01L218238
CPC分类号： H01L29/6659 , H01L21/2255 , H01L21/26586 , H01L21/823814 , H01L29/7833
摘要： A method of fabricating a MOS transistor having shallow source/drain junction regions is provided. A diffusion source layer is formed on a semiconductor substrate on which gate patterns are formed. Same type or different type of impurities are implanted into the diffusion source layer several times in different directions. As a result, dislocation does not occur and the impurity concentration of the diffusion source layer can be nonuniformly controlled so that damage to the crystal structure of the semiconductor substrate does not occur. Also, the impurities nonuniformly contained in the diffusion source layer are diffused into the semiconductor substrate by a solid phase diffusion method to form shallow source/drain junction regions having LDD regions and highly doped source/drain regions by a self-alignment method.
摘要翻译：提供一种制造具有浅源极/漏极结区域的MOS晶体管的方法。扩散源层形成在其上形成有栅极图案的半导体衬底上。相同类型或不同类型的杂质在不同方向上多次注入扩散源层。结果，不会发生位错，扩散源层的杂质浓度可能被不均匀地控制，从而不会发生对半导体衬底的晶体结构的损坏。此外，扩散源层中不均匀地包含的杂质通过固相扩散法扩散到半导体衬底中，以通过自对准方法形成具有LDD区和高掺杂源极/漏极区的浅源极/漏极结区域。

126. 发明授权

US6037198A Method of fabricating SOI wafer 有权
标题翻译：制造SOI晶圆的方法
公开(公告)号：US6037198A
公开(公告)日：2000-03-14
申请号：US139651
申请日：1998-08-25
申请人： Kyoung Wan Park , Seong Jae Lee , Moon Ho Park , Min Cheol Shin , Sang Chul Oh
发明人： Kyoung Wan Park , Seong Jae Lee , Moon Ho Park , Min Cheol Shin , Sang Chul Oh
IPC分类号： H01L21/20 , H01L21/762 , H01C71/00
CPC分类号： H01L21/76262
摘要： The present invention is to fabricate SOI wafer whose the silicon layer is very uniform and the impurity concentration is low. The insulating layer, that is, a composite layer of SiO2 and silicon, is grown on oxide substrate by means of a molecular beam epitaxy fabricating method using silicon as an original material in the oxygen atmosphere. The composite layer of the oxide and silicon is grown according to gradual decreasing the pressure of oxygen atmosphere. A top silicon layer of uniform thickness is grown by means of a molecular beam epitaxy fabricating method using only silicon material consecutively on the composite layer.
摘要翻译：本发明是制造硅层非常均匀且杂质浓度低的SOI晶片。通过在氧气氛中使用硅作为原料的分子束外延制造方法，在氧化物衬底上生长绝缘层，即SiO 2和硅的复合层。氧化物和硅的复合层根据氧气气氛的逐渐降低而生长。通过在复合层上连续使用硅材料的分子束外延制造方法生长均匀厚度的顶部硅层。

127. 发明授权

US5940696A Method of manufacturing a quantum diffraction transistor 失效
$Method of manufacturing a quantum diffraction transistor$
标题翻译：量子衍射晶体管的制造方法
公开(公告)号：US5940696A
公开(公告)日：1999-08-17
申请号：US932616
申请日：1997-09-17
申请人： Kyoung Wan Park , Seong Jae Lee , Min Cheol Shin
发明人： Kyoung Wan Park , Seong Jae Lee , Min Cheol Shin
IPC分类号： H01L29/06 , H01L21/335 , H01L29/66 , H01L29/772 , H01L29/80 , H01L21/338
CPC分类号： B82Y10/00 , H01L29/66446 , H01L29/66977 , H01L29/772 , Y10S438/962
摘要： The present invention discloses a technique for applying diffraction characteristics of electrons to a two-dimensional electronic device to manufacture multi-functional transistor having various ON/OFF states. Method of manufacturing a quantum diffraction transistor according to the present invention is capable of adjusting the amplitude of drain current and having various ON/OFF states utilizing diffraction characteristics of electrons by interposing a reflection-type diffraction grating in a bent electron path. In the inventive multi-functional quantum diffraction transistor using a two dimensional electron gas in quantum well structure formed at a different species junction in a heterostructure semiconductor device and having a bent electron path between the source electrode and the drain electrode with a reflection-type diffraction grating, the quantum diffraction effect of the electrons is used for the control of the diffracted drain current.
摘要翻译：本发明公开了一种将电子衍射特性应用于二维电子器件以制造具有各种ON / OFF状态的多功能晶体管的技术。根据本发明的量子衍射晶体管的制造方法能够通过在弯曲的电子路径中插入反射型衍射光栅来利用电子的衍射特性来调节漏极电流的振幅并具有各种导通/截止状态。在本发明的多功能量子衍射晶体管中，使用在异质结构半导体器件中形成于不同物质结的量子阱结构中的二维电子气，并且在源电极和漏电极之间具有反射型衍射光栅，电子的量子衍射效应用于衍射漏极电流的控制。

128. 发明授权

US5880484A Lateral resonant tunneling transistor having two non-symmetric quantum dots 失效
标题翻译：具有两个非对称量子点的横向谐振隧穿晶体管
公开(公告)号：US5880484A
公开(公告)日：1999-03-09
申请号：US706238
申请日：1996-09-04
申请人： Kyoung-Wan Park , Seong-Jae Lee , Min-Cheol Shin
发明人： Kyoung-Wan Park , Seong-Jae Lee , Min-Cheol Shin
IPC分类号： H01L29/68 , H01L21/334 , H01L29/06 , H01L29/12 , H01L29/205 , H01L29/66 , H01L29/772 , H01L29/778 , H01L29/80
CPC分类号： B82Y10/00 , H01L29/127 , H01L29/66939 , H01L29/772 , H01L29/7786
摘要： A lateral resonant tunneling transistor having two non-symmetric quantum dots is disclosed. When a negative voltage is supplied to each plurality of thin split gates, two non-symmetric quantum dots are formed owing to the formation of the potential barrier. Thus when a forward bias voltage is applied, the resonant tunneling phenomena occur twice successively. Through these two successive resonant tunneling phenomena and by lowering the height of the third potential barrier 6a, the resonant tunneling current can be maximized.
摘要翻译：公开了具有两个非对称量子点的横向谐振隧穿晶体管。当向每个多个薄分割栅极提供负电压时，由于形成势垒而形成两个非对称量子点。因此，当施加正向偏置电压时，谐振隧道现象连续发生两次。通过这两个连续的谐振隧道现象，并且通过降低第三势垒6a的高度，可以使谐振隧穿电流最大化。

129. 发明授权

US5519232A Quantum interference device 失效
标题翻译：量子干扰装置
公开(公告)号：US5519232A
公开(公告)日：1996-05-21
申请号：US352046
申请日：1994-11-30
申请人： Kyoung-Wan Park , Seong-Jae Lee , Min-Cheol Shin
发明人： Kyoung-Wan Park , Seong-Jae Lee , Min-Cheol Shin
IPC分类号： H01L29/68 , H01L21/338 , H01L29/205 , H01L29/66 , H01L29/778 , H01L29/80 , H01L29/812 , H01L31/0328 , H01L31/0336
CPC分类号： B82Y10/00 , H01L29/66977
摘要： A quantum interference device comprises a semi-insulating GaAs substrate; GaAs and AlGaAs layers sequentially formed with high purity on the substrate; a two-dimensional electron gas layer formed in the GaAs layer and serving as a channel; source/drain regions formed on the semi-insulating GaAs substrate and at both ends of a laminated portion composed of the GaAs/AlGaAs layers; and a gate formed on the AlGaAs layer and having a periodic structure wherein the length thereof varies in a periodic manner in a transverse direction. In the device, the electron gas layer formed in the GaAs layer is used as an electron path, and the phases of electrons passing along different electron paths are caused to interfere with each other by the gate, thereby causing the current of a drain therein to be maximized or minimized. The transconductance can be significantly increased.
摘要翻译：量子干涉装置包括半绝缘GaAs衬底; 在衬底上依次形成高纯度的GaAs和AlGaAs层; 形成在GaAs层中并用作沟道的二维电子气层; 在半绝缘GaAs衬底上形成的源极/漏极区域和由GaAs / AlGaAs层构成的层叠部分的两端; 以及形成在AlGaAs层上并且具有周期性结构的栅极，其中其长度在横向上以周期性方式变化。在该器件中，使用形成在GaAs层中的电子气层作为电子通路，使通过不同的电子路径的电子相被栅极相互干扰，从而使其中的漏极的电流最大化或最小化。跨导可以显着增加。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式