专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

111. 发明授权

US5583872A High speed data transfer over twisted pair cabling 失效
公开(公告)号：US5583872A
公开(公告)日：1996-12-10
申请号：US388872
申请日：1995-02-10
申请人： Alan Albrecht , Steven H. Goody , Michael P. Spratt , Joseph A. Curcio, Jr. , Daniel J. Dove
发明人： Alan Albrecht , Steven H. Goody , Michael P. Spratt , Joseph A. Curcio, Jr. , Daniel J. Dove
IPC分类号： H04L5/14 , H04L12/413 , H04L12/44 , H04L25/14 , H04L25/49 , H04L12/40
CPC分类号： H04L12/44 , H04L25/14 , H04L25/4908 , H04L5/143 , H04L12/413
摘要： A method provides for a first network node in a plurality of network nodes to transmit a data packet to a hub. The hub and the network nodes are interconnected within a local network system. Control signals are exchanged between the first network node and the hub. The exchange of control signals is done in a first signal frequency range. A data packet is sent from the first network node to the hub. The data packet is sent using data signals within a second signal frequency range. The first signal frequency range and the second signal frequency range do not overlap.

112. 发明授权

US5278827A Variable data rate channels for digital networks 失效
公开(公告)号：US5278827A
公开(公告)日：1994-01-11
申请号：US887021
申请日：1992-05-22
申请人： Alan Pound
发明人： Alan Pound
IPC分类号： H04J3/00 , H04J3/06 , H04J3/16 , H04J3/22 , H04L25/14
CPC分类号： H04J3/0626 , H04J3/1682 , H04L25/14
摘要： Communication channels provided by the Integrated services Digital Network (ISDN) usually carry 64 Kbits/sec in each direction and are therefore unsuitable for data traffic at higher rates. This difficulty can be overcome by assembling ISDN channels to form channels having a higher bit rate. However problems arise, for example, in the transmission of data packets where the bit-rate required changes frequently and therefore the number of channels grouped together must be changed often. These problems are tackled as now described. Data from different data streams to be transmitted is read into respective buffers in a RAM. ISDN channels are grouped into channels known as slots and U-channels, respectively, and each U-channel transmits a respective data stream. Data from the buffers are assembled into frames, corresponding to an ISDN frame in a frame store by a microprocessor. Information controlling how the data is assembled in the frame store is held by a slot control RAM and respective control portions of the RAM. Conventional ISDN circuits take frames from the store for transmission and fill a receive frame store on reception from other stations in the ISDN. The RAM takes account of any "skew" due to differential delays in different ISDN channels in reading out from the frame store into receive buffers. When a U-channel is to be expanded, without interruption of the existing slots in the U-channel, by the addition of another slot, a first distinctive synchronizing packet is transmitted which indicates the U-channel to which the new slot is to belong. When this packet has been acknowledged a second distinctive synchronizing packet is transmitted which carries a time reference for calculating skew and then data is sent in the new slot in the next frame. When the bit-rate for a U-channel falls one of the slots of that U-channel can be closed by transmitting a distinctive closing packet in that slot. On reception of this packet that slot is deleted in the next frame.

113. 发明授权

US5065396A Inverse multiplexer and demultiplexer techniques 失效
标题翻译：反向多路复用器和解复用器技术
公开(公告)号：US5065396A
公开(公告)日：1991-11-12
申请号：US460209
申请日：1990-01-02
申请人： James J. Castellano , John H. Leshchuk , Michael L. Steinberger
发明人： James J. Castellano , John H. Leshchuk , Michael L. Steinberger
IPC分类号： H04J3/06 , H04J3/00 , H04L25/14 , H04Q11/04
CPC分类号： H04L25/14 , H04J2203/0094
摘要： An Inverse Multiplexer is disclosed which first demultiplexes a first data rate input signal into a plurality of second lower data rate subsectional signals, where each subsectional signal is provided with a periodic synchronization marker and includes a data rate which is less than the channel data rate used to transmit that subsectional signal to a remote terminal. Programmable Multiplexers (PMUXs) then operate to each take one or more subsectional signals that are (1) clock synchronized to a PMUX clock, and (2) a rational fraction of the channel data rate, and map contiguously assigned time slots in a capacity domain frame for each subsectional signal to time slots of a time domain frame format using a 2-step or 3-step digit reverse technique. The resultant time domain format has the input subsectional capacity domain time slots substantially uniformly distributed over the time domain frame. At the receiving end, an Inverse Demultiplexer performs the reverse operation to recover the original first data rate input signal.

114. 发明授权

US4811364A Method and apparatus for stabilized data transmission 失效
标题翻译：用于稳定数据传输的方法和装置
公开(公告)号：US4811364A
公开(公告)日：1989-03-07
申请号：US176570
申请日：1988-04-01
申请人： David J. Sager , Leon D. Hesch , Andrew D. Ingraham , William A. Samaras
发明人： David J. Sager , Leon D. Hesch , Andrew D. Ingraham , William A. Samaras
IPC分类号： G06F13/42 , G06F1/10 , H04L7/00 , H04L7/02 , H04L7/033 , H04L7/04 , H04L25/02 , H04L25/14 , G06F11/00
CPC分类号： H04L7/0008 , G06F1/10 , H04L25/14 , H04L7/02 , H04L7/0338
摘要： Data can be accurately transmitted between two subsystems even if the clock skew between the two subsystems is larger than one clock cycle by the method of the invention. In one embodiment data is loaded into N state devices in the sending subsystem while the receiver recovers data from the sending state devices in rotation with an N input multiplexer. Another embodiment forwards a clock signal from the sending subsystem along with a data vector of N state signals for recovery by a pair of state devices capturing data on the rising and falling edges of the forwarded clock. A further embodiment achieves double bandwidth by forwarding two clock signals.
摘要翻译：即使通过本发明的方法两个子系统之间的时钟偏差大于一个时钟周期，也可以在两个子系统之间精确地传输数据。在一个实施例中，数据被加载到发送子系统中的N个状态设备中，同时接收机利用N输入多路复用器从发送状态设备中旋转数据。另一实施例将来自发送子系统的时钟信号与N个状态信号的数据向量一起转发，以便通过在转发的时钟的上升沿和下降沿捕获数据的一对状态设备进行恢复。另一实施例通过转发两个时钟信号实现双倍带宽。

115. 发明授权

USB558220I5 失效
公开(公告)号：USB558220I5
公开(公告)日：1976-01-27
申请号：US55822075
申请日：1975-03-14
IPC分类号： H04B1/74 , H04B7/17 , H04J3/06 , H04J3/07 , H04L1/02 , H04L25/14
CPC分类号： H04L25/14 , H04B1/74 , H04J3/06 , H04J3/07 , H04L1/02

116. 发明授权

US3803502A Pcm detector 失效
标题翻译： PCM检测器
公开(公告)号：US3803502A
公开(公告)日：1974-04-09
申请号：US33870673
申请日：1973-03-07
申请人： INT STANDARD ELECTRIC CORP
发明人： PILLOT J , ZACCONE P
IPC分类号： H04L25/03 , H03K5/153 , H04L25/06 , H04L25/14 , H04L25/49 , H03K9/00
CPC分类号： H04L25/14 , H04L25/062
摘要： There is disclosed a detector to determine the binary value of high speed PCM bits transmitted in NRZ or bipolar form. The incoming bits are distributed to n channels so that the detection time available for each bit is multiplied by n. In each channel, a capacitor is charged by a current having a value depending on the instantaneous amplitude of the input bit and then discharged at a constant current. A zero detector and a logic comparator are employed for determining the binary value of the bit based on the length of time it takes the capacitor to discharge down to a voltage level set by a clamping circuit.

117. 发明授权

US2916553A High speed delta modulation encoder 失效
标题翻译：高速delta调制编码器
公开(公告)号：US2916553A
公开(公告)日：1959-12-08
申请号：US66272857
申请日：1957-05-31
申请人： BELL TELEPHONE LABOR INC
发明人： CROWLEY THOMAS H
IPC分类号： H03M3/02 , H04L25/14
CPC分类号： H04L25/14 , H03M3/022

118. 发明授权

US1857259A Transmission system 失效
公开(公告)号：US1857259A
公开(公告)日：1932-05-10
申请号：US54662431
申请日：1931-06-24
申请人： AMERICAN TELEPHONE & TELEGRAPH
发明人： REA WILTON T
IPC分类号： H04L25/14
CPC分类号： H04L25/14

119. 发明授权

US12057973B2 Low power chip-to-chip bidirectional communications 有权
公开(公告)号：US12057973B2
公开(公告)日：2024-08-06
申请号：US18047610
申请日：2022-10-18
申请人： Kandou Labs, S.A.
发明人： Ali Hormati
IPC分类号： H04L25/02 , H04B3/14 , H04L25/08 , H04L25/49 , H01Q13/24 , H04L25/03 , H04L25/14 , H04W72/23
CPC分类号： H04L25/0292 , H04B3/14 , H04L25/0272 , H04L25/085 , H04L25/4919 , H01Q13/24 , H04L2025/03363 , H04L25/14 , H04W72/23
摘要： Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.

120. 发明公开

US20240160516A1 C-PHY RECEIVER CORRUPT POST PATTERN FILTER 审中-公开
公开(公告)号：US20240160516A1
公开(公告)日：2024-05-16
申请号：US17986631
申请日：2022-11-14
申请人： QUALCOMM Incorporated
发明人： Yasser AHMED , Sachin Ajit DEVAMARE
IPC分类号： G06F11/07 , H04L25/03 , H04L25/14
CPC分类号： G06F11/079 , G06F11/0745 , H04L25/03057 , H04L25/14
摘要： A communication interface circuit has a shift register configured to convert a serial stream of 3-bit symbols to a parallel multi-symbol word comprising a plurality of symbols ordered in accordance with time of arrival at an input of the shift register; a set of symbol comparators, each symbol comparator being configured to determine whether a pattern of symbols in the parallel multi-symbol word indicates presence of a false synchronization pattern in the serial stream of 3-bit symbols; and a synchronization detection circuit configured to provide a control signal that is active when a synchronization pattern is detected in the serial stream of 3-bit symbols, and further configured to suppress the control signal when at least one of the set of symbol comparators indicates the presence of the false synchronization pattern of 3-bit symbols.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式