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111. 发明申请

US20130054661A1 BLOCK FLOATING POINT COMPRESSION WITH EXPONENT DIFFERENCE AND MANTISSA CODING 有权
标题翻译：具有特殊差异和MANTISSA编码的块浮动点压缩
公开(公告)号：US20130054661A1
公开(公告)日：2013-02-28
申请号：US13661435
申请日：2012-10-26
申请人： Albert W. WEGENER
发明人： Albert W. WEGENER
IPC分类号： G06F7/00
CPC分类号： H03M7/24 , G06F7/483 , H03M7/40 , H03M7/46
摘要： A method and apparatus for compressing signal samples uses block floating point representations where the number of bits per mantissa is determined by the maximum magnitude sample in the group. The compressor defines groups of signal samples having a fixed number of samples per group. The maximum magnitude sample in the group determines an exponent value corresponding to the number of bits for representing the maximum sample value. The exponent values are encoded to form exponent tokens. Exponent differences between consecutive exponent values may be encoded individually or jointly. The samples in the group are mapped to corresponding mantissas, each mantissa having a number of bits based on the exponent value. Removing LSBs depending on the exponent value produces mantissas having fewer bits. Feedback control monitors the compressed bit rate and/or a quality metric. This abstract does not limit the scope of the invention as described in the claims.
摘要翻译：用于压缩信号样本的方法和装置使用块浮点表示，其中每尾数的位数由组中的最大幅度样本确定。压缩机定义每组具有固定数量样本的信号样本组。组中的最大幅度采样确定与用于表示最大采样值的位数相对应的指数值。指数值被编码以形成指数令牌。连续指数值之间的指数差异可以单独或联合编码。组中的样本被映射到相应的尾数，每个尾数具有基于指数值的位数。根据指数值去除LSB会产生具有较少位的尾数。反馈控制监视压缩比特率和/或质量度量。该摘要并不限制如权利要求中所述的本发明的范围。

112. 发明授权

US08375078B2 Fast floating point result forwarding using non-architected data format 有权
标题翻译：使用非架构化数据格式的快速浮点结果转发
公开(公告)号：US08375078B2
公开(公告)日：2013-02-12
申请号：US12820578
申请日：2010-06-22
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F2207/3824
摘要： A microprocessor having an instruction set architecture (ISA) that specifies at least one architected data format (ADF) for floating-point operands. The microprocessor includes a plurality of floating-point units, each comprising an arithmetic unit configured to receive non-ADF source operands and to perform a floating-point operation on the non-ADF source operands to generate a non-ADF result. The microprocessor also includes forwarding buses, configured to forward the non-ADF result generated by each arithmetic unit of the plurality of floating-point units to each of the plurality of floating-point units for selective use as one of the non-ADF source operands.
摘要翻译：具有指定集架构（ISA）的微处理器，其指定用于浮点操作数的至少一个架构数据格式（ADF）。微处理器包括多个浮点单元，每个浮点单元包括被配置为接收非ADF源操作数并且对非ADF源操作数执行浮点运算以产生非ADF结果的算术单元。微处理器还包括转发总线，其配置为将多个浮点单元的每个运算单元产生的非ADF结果转发到多个浮点单元中的每一个，以供选择性使用，作为非ADF源操作数之一。

113. 发明申请

US20130036296A1 FLOATING POINT EXECUTION UNIT WITH FIXED POINT FUNCTIONALITY 有权
标题翻译：具有固定点功能的浮点执行单元
公开(公告)号：US20130036296A1
公开(公告)日：2013-02-07
申请号：US13197894
申请日：2011-08-04
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F9/302
CPC分类号： G06F9/30014 , G06F7/483 , G06F9/3001 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3836 , G06F9/3889 , G06F2207/3824
摘要： A floating point execution unit is capable of selectively repurposing one or more adders in an exponent path of the floating point execution unit to perform fixed point addition operations, thereby providing fixed point functionality in the floating point execution unit.
摘要翻译：浮点执行单元能够选择性地重新排列浮点执行单元的指数路径中的一个或多个加法器，以执行固定点加法运算，从而在浮点执行单元中提供固定点功能。

114. 发明授权

US08301803B2 Block floating point compression of signal data 有权
标题翻译：阻塞信号数据的浮点压缩
公开(公告)号：US08301803B2
公开(公告)日：2012-10-30
申请号：US12605245
申请日：2009-10-23
申请人： Albert W. Wegener
发明人： Albert W. Wegener
IPC分类号： G06F15/16 , G06F7/00 , H04L9/32 , H04N7/167
CPC分类号： H03M7/24 , G06F7/483 , H03M7/40 , H03M7/46
摘要： A method and apparatus for compressing signal samples uses block floating point representations where the number of bits per mantissa is determined by the maximum magnitude sample in the group. The compressor defines groups of signal samples having a fixed number of samples per group. The maximum magnitude sample in the group determines an exponent value corresponding to the number of bits for representing the maximum sample value. The exponent values are encoded to form exponent tokens. Exponent differences between consecutive exponent values may be encoded individually or jointly. The samples in the group are mapped to corresponding mantissas, each mantissa having a number of bits based on the exponent value. Removing LSBs depending on the exponent value produces mantissas having fewer bits. Feedback control monitors the compressed bit rate and/or a quality metric. This abstract does not limit the scope of the invention as described in the claims.
摘要翻译：用于压缩信号样本的方法和装置使用块浮点表示，其中每尾数的位数由组中的最大幅度样本确定。压缩机定义每组具有固定数量样本的信号样本组。组中的最大幅度采样确定与用于表示最大采样值的位数相对应的指数值。指数值被编码以形成指数令牌。连续指数值之间的指数差异可以单独或联合编码。组中的样本被映射到相应的尾数，每个尾数具有基于指数值的位数。根据指数值去除LSB会产生具有较少位的尾数。反馈控制监视压缩比特率和/或质量度量。该摘要并不限制如权利要求中所述的本发明的范围。

115. 发明申请

US20120265964A1 DATA PROCESSING DEVICE AND DATA PROCESSING METHOD THEREOF 有权
标题翻译：数据处理设备及其数据处理方法
公开(公告)号：US20120265964A1
公开(公告)日：2012-10-18
申请号：US13365928
申请日：2012-02-03
申请人： Kan MURATA , Hideyuki Noda , Masaru Haraguchi
发明人： Kan MURATA , Hideyuki Noda , Masaru Haraguchi
IPC分类号： G06F15/80 , G06F9/02
CPC分类号： G06F15/7821 , G06F7/483 , G06F7/57 , G06F12/04 , G06F15/8007 , G06F2207/3812 , Y02D10/12 , Y02D10/13
摘要： Disclosed is a data processing device capable of efficiently performing an arithmetic process on variable-length data and an arithmetic process on fixed-length data. The data processing device includes first PEs of SIMD type, SRAMs provided respectively for the first PEs, and second PEs. The first PEs each perform an arithmetic operation on data stored in a corresponding one of the SRAMs. The second PEs each perform an arithmetic operation on data stored in corresponding ones of the SRAMs. Therefore, the SRAMs can be shared so as to efficiently perform the arithmetic process on variable-length data and the arithmetic process on fixed-length data.
摘要翻译：公开了能够有效地对可变长度数据进行算术处理的数据处理装置和对固定长度数据的运算处理。数据处理装置包括SIMD型的第一PE，分别为第一PE提供的SRAM和第二PE。第一PE每个对存储在相应的一个SRAM中的数据执行算术运算。第二PE每个对存储在相应SRAM中的数据执行算术运算。因此，可以共享SRAM，以便有效地执行关于可变长度数据的算术处理和对固定长度数据的算术处理。

116. 发明申请

US20120260031A1 ENHANCED PIPELINING AND MULTI-BUFFER ARCHITECTURE FOR LEVEL TWO CACHE CONTROLLER TO MINIMIZE HAZARD STALLS AND OPTIMIZE PERFORMANCE 有权
标题翻译：提高两级缓存控制器的管道和多缓冲结构，最大限度地减少危害和优化性能
公开(公告)号：US20120260031A1
公开(公告)日：2012-10-11
申请号：US13245211
申请日：2011-09-26
申请人： Abhijeet Ashok Chachad , Raguram Damodaran
发明人： Abhijeet Ashok Chachad , Raguram Damodaran
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is a data processing system including a central processing unit, an external interface, a level one cache, level two memory including level two unified cache and directly addressable memory. A level two memory controller includes a directly addressable memory read pipeline, a central processing unit write pipeline, an external cacheable pipeline and an external non-cacheable pipeline.
摘要翻译：本发明是包括中央处理单元，外部接口，一级缓存，包括二级统一缓存的二级存储器和直接可寻址存储器的数据处理系统。二级存储器控制器包括可直接寻址的存储器读取流水线，中央处理单元写入流水线，外部可缓存流水线和外部非缓存流水线。

117. 发明授权

US08280939B2 Methods and apparatus for automatic accuracy-sustaining scaling of block-floating-point operands 有权
标题翻译：块浮点运算的自动精度维持缩放的方法和装置
公开(公告)号：US08280939B2
公开(公告)日：2012-10-02
申请号：US12125536
申请日：2008-05-22
申请人： Igor Reyzin , Aleksey Lipchin
发明人： Igor Reyzin , Aleksey Lipchin
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F2207/3824
摘要： A computer-implemented method performs an operation on a set of at least one BFP operands to generate a BFP result. The method is designed to reduce the risks of overflow and loss of accuracy attributable to the operation. The method performs an analysis to determine respective shift values for each of the operands and the result. The method calculates result mantissas by shifting the stored bit patterns representing the corresponding operand mantissa values by their respective associated shift values determined in the analysis step, performing the operation on shifted operand mantissas to generate preliminary result mantissa, and shifting the preliminary result mantissas by a number of bits determined in the analysis step.
摘要翻译：计算机实现的方法对一组至少一个BFP操作数执行操作以产生BFP结果。该方法旨在减少由于操作引起的溢出和精度损失的风险。该方法执行分析以确定每个操作数和结果的各个移位值。该方法通过将表示相应的操作数尾数值的所存储的位模式移动其分析步骤中确定的各自相关的移位值来计算结果尾数，对移位的操作数尾进行操作以产生初步结果尾数，并将初步结果尾数移位在分析步骤中确定的位数。

118. 发明授权

US08275819B2 Methods and apparatus for performing calculations using reduced-width data 有权
标题翻译：使用缩减宽度数据进行计算的方法和装置
公开(公告)号：US08275819B2
公开(公告)日：2012-09-25
申请号：US12492961
申请日：2009-06-26
申请人： Ping T. Tang , Gopi K. Kolli
发明人： Ping T. Tang , Gopi K. Kolli
IPC分类号： G06F1/00
CPC分类号： G06F7/552 , G06F7/483 , G06F2207/5523
摘要： Methods, apparatus, and articles of manufacture for performing calculations using reduced-width data are disclosed. In particular, an example method determines reduced-width data values associated with generating and evaluating functions. Some of the reduced-width data values are stored within instructions in an instruction memory during a compile phase and retrieved from instruction memory during a runtime phase.
摘要翻译：公开了使用缩减宽度数据执行计算的方法，装置和制品。特别地，示例性方法确定与生成和评估功能相关联的缩小宽度数据值。一些缩减宽度数据值在编译阶段存储在指令存储器中的指令中，并在运行阶段期间从指令存储器中检索。

119. 发明申请

US20120221614A1 Processor Pipeline which Implements Fused and Unfused Multiply-Add Instructions 有权
标题翻译：处理器管道，实现融合和未填充的乘法添加说明
公开(公告)号：US20120221614A1
公开(公告)日：2012-08-30
申请号：US13469212
申请日：2012-05-11
申请人： Jeffrey S. Brooks , Christopher H. Olson
发明人： Jeffrey S. Brooks , Christopher H. Olson
IPC分类号： G06F7/48
CPC分类号： G06F7/483 , G06F7/5443 , G06F2207/3884
摘要： Implementing an unfused multiply-add instruction within a fused multiply-add pipeline. The system may include an aligner having an input for receiving an addition term, a multiplier tree having two inputs for receiving a first value and a second value for multiplication, and a first carry save adder (CSA), wherein the first CSA may receive partial products from the multiplier tree and an aligned addition term from the aligner. The system may include a fused/unfused multiply add (FUMA) block which may receive the first partial product, the second partial product, and the aligned addition term, wherein the first partial product and the second partial product are not truncated. The FUMA block may perform an unfused multiply add operation or a fused multiply add operation using the first partial product, the second partial product, and the aligned addition term, e.g., depending on an opcode or mode bit.
摘要翻译：在融合的乘法加法管道中实现未经加密的乘法加法指令。系统可以包括具有用于接收加法项的输入的对准器，具有用于接收第一值的两个输入和用于乘法的第二值的乘法器树，以及第一进位保存加法器（CSA），其中第一CSA可以接收部分乘数树中的乘积和对准器的对齐加法项。该系统可以包括可以接收第一部分乘积，第二部分乘积和对齐的加法项的融合/未融合乘法（FUMA）块，其中第一部分乘积和第二部分乘积不被截断。 FUMA块可以使用第一部分乘积，第二部分积和对齐的相加项来执行未融合的加法运算或融合乘法运算，例如取决于操作码或模式位。

120. 发明申请

US20120203813A1 GENERATION OF TEST CASES WITH RANGE CONSTRAINTS FOR FLOATING POINT ADD AND SUBTRACT INSTRUCTIONS 审中-公开
标题翻译：产生用于浮点添加和放弃说明的范围限制的测试案例
公开(公告)号：US20120203813A1
公开(公告)日：2012-08-09
申请号：US13448761
申请日：2012-04-17
申请人： Abraham Ziv
发明人： Abraham Ziv
IPC分类号： G06F7/38
CPC分类号： G06F17/5022 , G06F7/483 , G06F7/49957
摘要： Methods, apparatus and systems are disclosed for the generation of range-constrained test cases for verification of designs of arithmetic floating point units. Given three ranges of floating point numbers Rx, Ry, Rz, a floating point operation (op), and a rounding-mode (round), three floating point numbers x, y, z are generated such that xεRx, yεRy, zεRz, and z=round ( x op y). Solutions are provided for add and subtract operations. Range constraints are imposed on the input operands and on the result operand of floating point add and subtract instructions to target corner cases when generating test cases for use in verification of floating point hardware.
摘要翻译：公开了用于生成用于验证算术浮点单元的设计的范围限制测试用例的方法，装置和系统。给定三个浮点数Rx的范围，Ry，Rz，浮点运算（op）和舍入模式（round）三个浮点数x，y，z，使得x，y，y，，z＆egr; Rz，z = round（x op y）。提供解决方案用于加减操作。在生成用于验证浮点硬件的测试用例时，对输入操作数和浮点加法和减法指令的结果操作数施加范围约束。

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