专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

111. 发明申请

US20040128460A1 Transceiver with latency alignment circuitry 失效
标题翻译：具有延迟对准电路的收发器
公开(公告)号：US20040128460A1
公开(公告)日：2004-07-01
申请号：US10699116
申请日：2003-10-31
申请人： Rambus Inc.
发明人： Kevin Donnelly , Mark Johnson , Chanh Tran
IPC分类号： G06F012/00
CPC分类号： G06F13/405 , G06F13/4022 , G06F13/4243
摘要： In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.
摘要翻译：在收发机系统中，第一接口使用第一时钟信号从第一信道接收数据，并使用第二时钟信号将数据发送到第一信道。第二接口使用第三时钟信号从第二信道接收数据，并使用第四时钟信号将数据发送到第二信道。重新定时器使用第一时钟信号从第一信道接收数据，并使用第四时钟信号将数据重传到第二信道。

112. 发明申请

US20040123014A1 System and method for communicating over intra-hierarchy and inter-hierarchy links 失效
标题翻译：用于通过层次内和层间链接进行通信的系统和方法
公开(公告)号：US20040123014A1
公开(公告)日：2004-06-24
申请号：US10325807
申请日：2002-12-19
申请人： Intel Corporation
发明人： Joseph Schaefer , David B. Minturn , Prashant Sethi
IPC分类号： G06F013/20
CPC分类号： G06F13/405
摘要： A system having an I/O interconnect topology utilizes internal packetized communications. The system includes a host system element, a plurality of switching elements, and a root complex to bridge communications between the host system and the switching elements. The ports of at least some of the switching elements have a cross-link device associated therewith, which is a logical device defined by configuration space of the switching element. Each cross-link device defines a cross-link communication path between two switching elements of the hierarchy allowing communications between peripherals to bypass the host.
摘要翻译：具有I / O互连拓扑的系统利用内部分组通信。该系统包括主机系统元件，多个开关元件和用于桥接主机系统与开关元件之间的通信的根复合体。至少一些开关元件的端口具有与其相关联的交叉连接装置，其是由开关元件的配置空间限定的逻辑装置。每个交叉链路设备定义了层级的两个交换元件之间的交叉链路通信路径，从而允许外围设备之间的通信绕过主机。

113. 发明授权

US06708244B2 Optimized I2O messaging unit 有权
标题翻译：优化的I2O消息单元
公开(公告)号：US06708244B2
公开(公告)日：2004-03-16
申请号：US09359465
申请日：1999-07-22
申请人： B. David Black , Steven P. Larky , Leah S. Clark , David A. Podsiadlo
发明人： B. David Black , Steven P. Larky , Leah S. Clark , David A. Podsiadlo
IPC分类号： G06F1300
CPC分类号： G06F13/405
摘要： A circuit comprising a storage circuit and a control circuit. The storage circuit may be configured to store one or more message frames received from a first bus and a second bus in one or more memory locations in response to one or more signals. The control circuit may be configured to store and access the one or more signals, wherein the signals are presented to the storage circuit through the first or the second bus such that management overhead of the first or second bus is reduced.
摘要翻译：一种包括存储电路和控制电路的电路。存储电路可以被配置为响应于一个或多个信号，在一个或多个存储器位置中存储从第一总线和第二总线接收的一个或多个消息帧。控制电路可以被配置为存储和访问一个或多个信号，其中通过第一或第二总线将信号呈现给存储电路，使得减少第一或第二总线的管理开销。

114. 发明申请

US20030188075A1 CPU expandability bus 有权
公开(公告)号：US20030188075A1
公开(公告)日：2003-10-02
申请号：US10401586
申请日：2003-03-31
发明人： Alex D. Peleg , Adi Golbert
IPC分类号： G06F013/36
CPC分类号： G06F13/405
摘要： Embodiments of the present invention provide a computer system with a high speed, high bandwidth expandability bus for integrated and non-integrated CPU products. The computer system includes a processor, a chipset coupled to the processor, a graphics processor coupled to the chipset for controlling a video display and a main memory coupled to the chipset. The computer system further includes an expandability bus, which is coupled at one end to the chipset and at the other end to a replaceable electronic component. The expandability bus can be changeably configured to enable or disable bus mastering at both ends, as required, to operate with whichever replaceable electronic component is installed.

115. 发明授权

US06598103B2 Transmission of signals synchronous to a common clock and transmission of data synchronous to strobes in a multiple agent processing system 有权
公开(公告)号：US06598103B2
公开(公告)日：2003-07-22
申请号：US09991626
申请日：2001-11-06
申请人： Peter D. MacWilliams , William S. Wu , Dilip K. Sampath , Bindi A. Prasad
发明人： Peter D. MacWilliams , William S. Wu , Dilip K. Sampath , Bindi A. Prasad
IPC分类号： G06F1342
CPC分类号： G06F13/385 , G06F13/4018 , G06F13/405
摘要： A method and apparatus for transferring data between bus agents in a computer system. The present invention includes transmitting a control signal, from a first agent to a second agent, via a first transfer protocol; and, transmitting data corresponding to the control signal, from the first agent to the second agent, via a second transfer protocol. In one embodiment, the control signals are transmitted from the first agent to the second agent via a synchronous transmission with respect to a bus clock; and, the data is transmitted via an asynchronous transmission with respect to the bus clock, which has a data width greater than the synchronous transmission. In addition, in one embodiment of the present invention, the synchronous transmission is a common clock data transfer protocol, and the asynchronous transmission is a source clock data transfer protocol.

116. 发明申请

US20030095557A1 RESPONSE VIRTUAL CHANNEL FOR HANDLING ALL RESPONSES 失效
标题翻译：应对虚拟通道处理所有反应
公开(公告)号：US20030095557A1
公开(公告)日：2003-05-22
申请号：US09398624
申请日：1999-09-17
发明人： JAMES B. KELLER , DERRICK R. MEYER
IPC分类号： H04L012/28
CPC分类号： G06F13/405
摘要： A computer system employs virtual channels and allocates different resources to the virtual channels. Packets which do not have logical/protocol-related conflicts are grouped into a virtual channel. Accordingly, logical conflicts occur between packets in separate virtual channels. The packets within a virtual channel may share resources (and hence experience resource conflicts), but the packets within different virtual channels may not share resources. Since packets which may experience resource conflicts do not experience logical conflicts, and since packets which may experience logical conflicts do not experience resource conflicts, deadlock-free operation may be achieved. Additionally, nodes within the computer system may be configured to preallocate resources to process response packets. Some response packets may have logical conflicts with other response packets, and hence would normally not be allocable to the same virtual channel. However, by preallocating response-processing resources, response packets are accepted by the destination node. Thus, any resource conflicts which may occur are temporary (as the response packets which make forward progress are processable). Viewed in another way, response packets may be logically independent if the destination node is capable of processing the response packets upon receipt. Accordingly, a response virtual channel is formed to which each response packet belongs.
摘要翻译：计算机系统采用虚拟通道并为虚拟通道分配不同的资源。没有逻辑/协议相关冲突的数据包被分组成虚拟通道。因此，在分离的虚拟通道中的分组之间发生逻辑冲突。虚拟通道内的数据包可能共享资源（从而遇到资源冲突），但不同虚拟通道内的数据包可能不共享资源。由于可能遇到资源冲突的数据包不会出现逻辑冲突，并且由于可能遇到逻辑冲突的数据包不会遇到资源冲突，因此可能会实现无死锁操作。此外，计算机系统内的节点可以被配置为预先分配资源以处理响应分组。一些响应分组可能与其他响应分组具有逻辑冲突，因此通常不能分配给相同的虚拟信道。然而，通过预分配响应处理资源，响应分组被目的节点接受。因此，可能发生的任何资源冲突都是临时的（因为可以进行进展的响应数据包是可处理的）。以另一种方式观察，如果目的地节点在接收时能够处理响应分组，则响应分组可以在逻辑上是独立的。因此，形成每个响应分组所属的响应虚拟信道。

117. 发明授权

US06553434B1 Pseudo master/slave decoupling of high speed bus communications timing 失效
标题翻译：伪主/从分离高速总线通讯时序
公开(公告)号：US06553434B1
公开(公告)日：2003-04-22
申请号：US09369135
申请日：1999-08-05
申请人： Alfred Abkarian , Kiran Munj , Harun Muliadi
发明人： Alfred Abkarian , Kiran Munj , Harun Muliadi
IPC分类号： G06F1314
CPC分类号： G06F13/405
摘要： A system and method of decoupling timing in a high speed bus system. A master/slave translator is coupled between a master device and a slave device. A pseudo slave of the master/slave translator responds to the master in a first timing protocol. A pseudo master of the master/slave translator masters the slave devices under a different timing protocol. The master/slave translator causes the master to believe its communications with the slave device are occurring under the first protocol.
摘要翻译：一种在高速总线系统中去耦定时的系统和方法。主/从转换器耦合在主设备和从设备之间。主/从转换器的伪从机以第一定时协议响应主机。主/从转换器的伪主机以不同的定时协议来对从设备进行主控。主/从翻译器使主机相信其与从设备的通信正在第一协议下进行。

118. 发明授权

US06553430B1 Computer system implementing flush operation 有权
标题翻译：计算机系统实现冲洗操作
公开(公告)号：US06553430B1
公开(公告)日：2003-04-22
申请号：US09410852
申请日：1999-10-01
申请人： James B. Keller
发明人： James B. Keller
IPC分类号： G06F1316
CPC分类号： G06F13/405
摘要： A computer system is presented which implements a “flush” operation providing a response to a source which signifies that all posted write operations previously issued by the source have been properly ordered within their targets with respect to other pending operations. The computer system includes multiple processing nodes within a processing subsystem and at least one input/output (I/O) node coupled to a processing node including a host bridge. The host bridge receives non-coherent posted write commands from the I/O node and responsively generates corresponding coherent posted write commands within the processing subsystem. Each posted write command has a target within the processing subsystem. The host bridge includes a data buffer for storing data used to track the status of non-coherent posted write commands. The I/O node issues a flush command to ensure that all previously issued non-coherent posted write commands have at least reached points of coherency within the processing subsystem. The host bridge issues a non-coherent target done response to the I/O node in response to: (i) the flush command, and (ii) coherent target done responses received from all targets of posted write commands previously issued by the I/O node. Coherent target done responses signify write commands have at least reached points of coherency within the processing subsystem. The non-coherent target done response signals the I/O node that all non-coherent posted write commands previously issued by the I/O node have at least reached points of coherency within the processing subsystem.
摘要翻译：提供了一种计算机系统，其实现“冲洗”操作，其提供对源的响应，其表示以前由源发出的所有发布的写入操作已经相对于其他挂起的操作在其目标内被正确地排序。计算机系统包括处理子系统内的多个处理节点和耦合到包括主机桥的处理节点的至少一个输入/输出（I / O）节点。主机桥从I / O节点接收非相干的写入命令，并在处理子系统内响应地生成相应的相干的写入命令。每个发布的写入命令在处理子系统内都有一个目标。主桥包括用于存储用于跟踪非相干发布的写入命令的状态的数据的数据缓冲器。 I / O节点发出flush命令，以确保所有先前发布的非相干发布的写入命令至少达到处理子系统内的一致性点。响应于：（i）flush命令和（ii）从I / O节点先前发布的已发布的写入命令的所有目标接收的相干目标完成响应，主桥发出对I / O节点的非相干目标完成响应， O节点。相干目标完成响应表示写入命令至少达到处理子系统内的一致性点。非相干目标完成响应信号I / O节点，以前由I / O节点发出的所有非相干发布的写命令至少达到处理子系统内的一致性点。

119. 发明申请

US20030065845A1 Isochronous transactions for interconnect busses of a computer system 有权
标题翻译：计算机系统的互连总线的同步事务
公开(公告)号：US20030065845A1
公开(公告)日：2003-04-03
申请号：US09967606
申请日：2001-09-29
发明人： Dwight D. Riley
IPC分类号： G06F013/00
CPC分类号： G06F13/405
摘要： An isochronous channel is configured on an interconnect bus between a first device and a second device. A first device requests an isochronous channel, required bandwidth, and a required service window size. If a service window of the required size at the required bandwidth is available, an isochronous bus controller sends the request to the second device. If the second device has a service window of the required size at the required, it accepts the isochronous channel request. The isochronous bus controller can be a collection of isochronous controllers, each controlling a subset of the interconnect bus. The isochronous bus controller then allocates bandwidth to the first device, notifying the first device to begin generating isochronous transactions, controlling access to the bus to ensure the first device does not exceed the bandwidth allocation. Further, the isochronous bus controller terminates the isochronous channel, if the first device stops sending isochronous transactions.
摘要翻译：在第一设备和第二设备之间的互连总线上配置同步信道。第一个设备请求同步信道，所需带宽和所需的服务窗口大小。如果所需带宽的所需大小的服务窗口可用，则同步总线控制器将请求发送到第二设备。如果第二个设备具有所需大小的服务窗口，则接受同步信道请求。同步总线控制器可以是同步控制器的集合，每个控制器控制互连总线的子集。等时总线控制器然后将带宽分配给第一设备，通知第一设备开始生成等时事务，控制对总线的访问以确保第一设备不超过带宽分配。此外，等时总线控制器终止同步信道，如果第一设备停止发送同步事务。

120. 发明申请

US20030046514A1 Single-chip microcomputer 失效
公开(公告)号：US20030046514A1
公开(公告)日：2003-03-06
申请号：US10172290
申请日：2002-06-13
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F015/00
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式