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111. 发明授权

US07268393B2 Semiconductor devices and methods of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07268393B2
公开(公告)日：2007-09-11
申请号：US11112533
申请日：2005-04-22
申请人： Jea-Hee Kim
发明人： Jea-Hee Kim
IPC分类号： H01L29/72
CPC分类号： H01L29/6656 , H01L21/26586 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： Semiconductor devices and methods of manufacturing semiconductor devices which achieve higher integration and higher operating speed are provided. A disclosed example semiconductor device includes a semiconductor substrate of a first conductivity type; a gate insulating layer on the substrate; and a gate on the gate insulating layer. The substrate also includes first spacers on opposite side walls of the gate. Each of the first spacers has a notch at a lower end adjacent the substrate. The example device also includes second spacers on side walls of respective ones of the first spacers; source/drain junction regions of a second conductivity type in the substrate on opposite sides of the gate and the second spacers; and LDD regions of the second conductivity type in the substrate at opposite sides of the gate and the first spacers. Each of the LDD regions has an end adjacent a respective one of the junction regions. The disclosed example device also includes pocket regions of the first conductivity type in the substrate at opposite sides of the gate. Each of the pocket regions has an end adjacent a respective one of the LDD regions, and each of the pocket regions has more depth under the gate than in other regions.
摘要翻译：提供了实现更高集成度和更高操作速度的制造半导体器件的半导体器件和方法。所公开的示例性半导体器件包括第一导电类型的半导体衬底; 基板上的栅极绝缘层; 和栅极绝缘层上的栅极。衬底还包括在栅极的相对侧壁上的第一间隔物。每个第一间隔件在邻近衬底的下端具有凹口。示例性装置还包括在第一间隔件中的相应一个的侧壁上的第二间隔件; 在栅极和第二间隔物的相对侧上的衬底中的第二导电类型的源极/漏极结区域; 和第二导电类型的LDD区域在栅极的相对侧的基板和第一间隔物中。每个LDD区域具有邻近各个连接区域的端部。所公开的示例性装置还包括在栅极的相对侧的衬底中的第一导电类型的袋区域。每个袋区域具有邻近相应一个LDD区域的端部，并且每个袋区域在栅极下方具有比在其它区域中更深的深度。

112. 发明授权

US07268050B2 Method for fabricating a MOS transistor in a semiconductor device including annealing in a nitrogen environment to form a nitrided oxide film 失效
标题翻译：在半导体器件中制造MOS晶体管的方法，包括在氮气环境中退火以形成氮化氧化物膜
公开(公告)号：US07268050B2
公开(公告)日：2007-09-11
申请号：US11025696
申请日：2004-12-28
申请人： Min Ho Jeong
发明人： Min Ho Jeong
IPC分类号： H01L21/336
CPC分类号： H01L21/28202 , H01L21/2652 , H01L21/28035 , H01L21/28176 , H01L21/28247 , H01L21/324 , H01L29/518 , H01L29/6656 , H01L29/6659
摘要： A method for fabricating a MOS transistor in a semiconductor device is disclosed. An example method subjects a surface of a semiconductor substrate to thermal oxidation to form an oxide film for forming a gate insulating film, deposits a polysilicon layer on the oxide film for forming a gate, applies a coat of photoresist onto the polysilicon layer, and performs exposure and development by using an exposure mask which defines the gate to form a photoresist pattern covering a region where the gate is to be formed. The example method also performs dry etching to remove the polysilicon layer for forming the gate and the oxide film for forming the gate insulating film, which are not protected with the photoresist pattern, to form a gate pattern,performs annealing under a nitrogen environment to form a nitrided oxide film, and forms buried lightly doped impurity ion layers on opposite sides of the gate pattern. Additionally, the example method deposits an insulating layer on the substrate to cover the gate pattern and etches back the insulating layer to expose the surface of the semiconductor substrate to form sidewall spacers, forms buried heavily doped impurity ion layers in the semiconductor substrate at exposed active regions by using the gate pattern and the sidewall spacers as an ion injection mask, and performs annealing to diffuse impurity ions for forming source/drain junctions to form lightly doped impurity diffusion regions and heavily doped impurity diffusion regions.
摘要翻译：公开了一种在半导体器件中制造MOS晶体管的方法。示例性方法使半导体衬底的表面经受热氧化以形成用于形成栅极绝缘膜的氧化膜，在用于形成栅极的氧化物膜上沉积多晶硅层，在多晶硅层上施加一层光致抗蚀剂，并执行通过使用限定栅极以形成覆盖要形成栅极的区域的光致抗蚀剂图案的曝光掩模来曝光和显影。该示例方法还进行干蚀刻以去除用于形成栅极的多晶硅层和用于形成栅极绝缘膜的氧化膜，其不被光致抗蚀剂图案保护以形成栅极图案，在氮气环境下进行退火以形成氮化氧化物膜，并且在栅极图案的相对侧上形成埋入的轻掺杂杂质离子层。此外，该示例性方法在衬底上沉积绝缘层以覆盖栅极图案并蚀刻绝缘层以暴露半导体衬底的表面以形成侧壁间隔物，在暴露的活性物质上在半导体衬底中形成埋入重掺杂杂质离子层通过使用栅极图案和侧壁间隔物作为离子注入掩模，进行退火以扩散用于形成源极/漏极结的杂质离子，以形成轻掺杂杂质扩散区域和重掺杂杂质扩散区域。

113. 发明授权

US07259092B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07259092B2
公开(公告)日：2007-08-21
申请号：US10930164
申请日：2004-08-30
申请人： Byung Hyun Jung
发明人： Byung Hyun Jung
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/28562 , H01L21/76876 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method for fabricating the same is disclosed, to prevent a defective contact of a line in a method of completely filling a minute contact hole having a high aspect ratio with a refractory metal layer, which includes the steps of forming a contact hole in an insulating interlayer of a semiconductor substrate; depositing a barrier metal layer on an inner surface of the contact hole and an upper surface of the insulating interlayer, wherein the process of depositing the barrier metal is performed by sequentially progressing one cycle of: injecting a reaction gas of SiH4 to the chamber, injecting a first purging gas to the chamber, injecting a reaction gas of WF6 to the chamber; injecting a second purging gas to the chamber, injecting a reaction gas of NH3 to the chamber, and injecting a third purging gas to the chamber; depositing a first metal layer for nucleation on the barrier metal layer by the atomic layer deposition process; and depositing a second metal layer on the first metal layer inside the contact hole, to fill the contact hole completely.
摘要翻译：公开了一种半导体器件及其制造方法，以防止在与难熔金属层完全填充具有高纵横比的微小接触孔的方法中线的接触不良，其包括形成接触的步骤在半导体衬底的绝缘中间层中的孔; 在接触孔的内表面和绝缘中间层的上表面上沉积阻挡金属层，其中沉积阻挡金属的过程是通过依次进行一个循环来进行的：将SiH 4的反应气体注入向室内注入第一吹扫气体，向室内注入WF 6反应气体，向所述室注入第二吹扫气体，将NH 3的反应气体注入所述室，并向所述室注入第三吹扫气体; 通过原子层沉积工艺在阻挡金属层上沉积成核的第一金属层; 以及在接触孔内的第一金属层上沉积第二金属层，以完全填充接触孔。

114. 发明授权

US07259053B2 Methods for forming a device isolation structure in a semiconductor device 有权
标题翻译：在半导体器件中形成器件隔离结构的方法
公开(公告)号：US07259053B2
公开(公告)日：2007-08-21
申请号：US10946717
申请日：2004-09-22
申请人： Hak Dong Kim
发明人： Hak Dong Kim
IPC分类号： H01L21/8238 , H01L21/76
CPC分类号： H01L21/76213 , H01L21/823878
摘要： Methods of forming a device isolation structure in a semiconductor device are disclosed. A disclosed method comprises forming a p-type well and an n-type well in a semiconductor substrate; sequentially depositing a gate insulating layer and a gate electrode material layer; depositing a protective layer on the gate electrode material layer; removing a portion of the protective layer, a portion of the gate electrode material layer, and a portion of the gate insulating layer to expose a surface area of the semiconductor substrate; performing ion implantation and heat treatment processes to form a device isolation structure; forming a gate electrode by removing a portion of the gate electrode material layer; forming an LDD region by implanting low concentration impurity ions in the semiconductor substrate; forming a spacers on a sidewall of the gate electrode; and forming a source/drain region by implanting high concentration impurity ions.
摘要翻译：公开了在半导体器件中形成器件隔离结构的方法。所公开的方法包括在半导体衬底中形成p型阱和n型阱; 依次沉积栅极绝缘层和栅电极材料层; 在栅电极材料层上沉积保护层; 去除所述保护层的一部分，所述栅电极材料层的一部分和所述栅极绝缘层的一部分以暴露所述半导体衬底的表面区域; 执行离子注入和热处理工艺以形成器件隔离结构; 通过去除栅电极材料层的一部分来形成栅电极; 通过在半导体衬底中注入低浓度杂质离子形成LDD区; 在所述栅电极的侧壁上形成间隔物; 以及通过注入高浓度杂质离子形成源极/漏极区域。

115. 发明授权

US07256096B2 Semiconductor device having a dual-damascene gate and manufacturing method thereof 失效
标题翻译：具有双镶嵌栅极的半导体器件及其制造方法
公开(公告)号：US07256096B2
公开(公告)日：2007-08-14
申请号：US11024629
申请日：2004-12-30
申请人： Jung Gyu Kim
发明人： Jung Gyu Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/2652 , H01L29/42376 , H01L29/665 , H01L29/66545 , H01L29/7833
摘要： A method of manufacturing a semiconductor device having a dual-damascene gate including forming LDD regions by forming a gate oxide film on a semiconductor substrate, and by implanting lowly-concentrated impurities in the semiconductor substrate in accordance with a predetermined LDD pattern, and forming a nitride film on the gate oxide film, and forming a wide nitride film in accordance with the wide nitride pattern. The method also includes forming a narrow nitride film by a narrow etching process on the wide nitride film in accordance with a predetermined narrow nitride film pattern, forming a dual-damascene gate by depositing a polysilicon layer on an exposed entire surface and smoothing the deposited polysilicon layer to a top surface of the nitride film, and forming a gate electrode by removing a predetermined region of the polysilicon layer. The method further includes forming a sidewall nitride film on the gate electrode by etching the exposed nitride film in accordance with a nitride film pattern, and forming source/drain regions by performing an ion implantation process on the source/drain regions.
摘要翻译：一种制造具有双镶嵌栅极的半导体器件的方法，包括通过在半导体衬底上形成栅极氧化膜形成LDD区，并且根据预定的LDD图案在半导体衬底中注入低浓度的杂质，并形成氮化物膜，并且根据宽氮化物图案形成宽的氮化物膜。该方法还包括通过狭窄的蚀刻工艺在宽氮化物膜上根据预定的窄氮化物膜图案形成窄的氮化物膜，通过在暴露的整个表面上沉积多晶硅层并平滑沉积的多晶硅来形成双镶嵌栅极层到氮化膜的顶表面，并且通过去除多晶硅层的预定区域来形成栅电极。该方法还包括通过根据氮化物膜图案蚀刻暴露的氮化物膜而在栅极上形成侧壁氮化物膜，以及通过在源极/漏极区域上执行离子注入工艺来形成源极/漏极区域。

116. 发明授权

US07247917B2 Nonvolatile semiconductor memory devices and methods of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07247917B2
公开(公告)日：2007-07-24
申请号：US11023314
申请日：2004-12-27
申请人： Tae Ho Choi
发明人： Tae Ho Choi
IPC分类号： H01L29/78
CPC分类号： H01L27/11521 , H01L27/115
摘要： Nonvolatile semiconductor memory devices and methods of manufacturing the same are disclosed. A disclosed nonvolatile semiconductor memory cell includes a semiconductor substrate; first and second semiconductor cells positioned on the semiconductor substrate at a distance from each other; a first source and a second source adjacent the first and second semiconductor cells; a first drain contact between the first and second semiconductor cells; first and second cap dielectrics formed on the first and second semiconductor cells, respectively; first and second sidewall spacers formed on sidewalls of the first and second semiconductor cells, respectively; an inter metal dielectric layer covering the first and second cap dielectrics and the first and second sidewall spacers, a drain contact hole exposing the drain; and a second drain contact connected to the first drain contact through the drain contact hole.
摘要翻译：公开了非易失性半导体存储器件及其制造方法。所公开的非易失性半导体存储单元包括半导体衬底; 位于半导体衬底上彼此间隔一定距离的第一和第二半导体单元; 邻近第一和第二半导体单元的第一源极和第二源极; 第一和第二半导体单元之间的第一漏极接触; 分别形成在第一和第二半导体单元上的第一和第二盖电介质; 分别形成在第一和第二半导体单元的侧壁上的第一和第二侧壁间隔物; 覆盖第一和第二盖电介质以及第一和第二侧壁间隔物的金属间介电层，暴露漏极的漏极接触孔; 以及通过漏极接触孔连接到第一漏极接触的第二漏极接触。

117. 发明授权

US07247565B2 Methods for fabricating a copper interconnect 有权
标题翻译：制造铜互连的方法
公开(公告)号：US07247565B2
公开(公告)日：2007-07-24
申请号：US10925078
申请日：2004-08-24
申请人： Dong Yeal Keum
发明人： Dong Yeal Keum
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating a copper interconnect are disclosed. A disclosed method comprises: employing a damascene process to form a first trench in a first insulating layer; depositing a first barrier layer and a first copper layer on the first insulating layer; forming a bottom copper interconnect by planarizing the first copper layer; depositing and planarizing a second barrier layer; depositing a second insulating layer; forming a via hole in the second insulating layer; employing a damascene process to form a second trench in the second insulating layer; and forming a via and an upper copper interconnect by depositing a third barrier layer and a second copper layer on the second insulating layer.
摘要翻译：公开了制造铜互连的方法。所公开的方法包括：采用镶嵌工艺在第一绝缘层中形成第一沟槽; 在所述第一绝缘层上沉积第一阻挡层和第一铜层; 通过平坦化第一铜层形成底部铜互连; 沉积和平坦化第二阻挡层; 沉积第二绝缘层; 在所述第二绝缘层中形成通孔; 采用镶嵌工艺在第二绝缘层中形成第二沟槽; 以及通过在所述第二绝缘层上沉积第三阻挡层和第二铜层来形成通孔和上铜互连。

118. 发明授权

US07247507B2 Method for forming LOCOS layer in semiconductor device 失效
标题翻译：在半导体器件中形成LOCOS层的方法
公开(公告)号：US07247507B2
公开(公告)日：2007-07-24
申请号：US11322750
申请日：2005-12-30
申请人： Woong Je Sung
发明人： Woong Je Sung
IPC分类号： H01L21/00
CPC分类号： H01L29/42368 , H01L21/7621 , H01L29/66659 , H01L29/7835
摘要： A method for forming a LOCOS layer in a semiconductor device includes steps of oxidizing a high voltage region of the semiconductor device to form a LOCOS layer in the high voltage region; and etching the LOCOS layer according to a pattern.
摘要翻译：在半导体器件中形成LOCOS层的方法包括以下步骤：氧化半导体器件的高电压区域，以在高压区域形成LOCOS层; 并根据图案蚀刻LOCOS层。

119. 发明申请

US20070166932A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070166932A1
公开(公告)日：2007-07-19
申请号：US11645545
申请日：2006-12-27
申请人： Dae Kim
发明人： Dae Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/02332 , H01L21/02238 , H01L21/0228 , H01L21/28167 , H01L21/28202 , H01L21/3141 , H01L21/3144 , H01L29/4916 , H01L29/6659
摘要： A method of fabricating a semiconductor device consistent with the present invention, the method comprising: forming an insulation film on a substrate; forming a mono-atomic layer of barrier ions at the insulation film; forming a gate insulation film in which the barrier ions are stabilized by an annealing process; forming a gate electrode on the gate insulation film; forming a spacer at a side surface of the gate electrode; and forming source/drain impurity regions at a side surface of the gate electrode.
摘要翻译：一种制造符合本发明的半导体器件的方法，所述方法包括：在衬底上形成绝缘膜; 在绝缘膜上形成阻挡离子的单原子层; 形成通过退火工艺使阻挡离子稳定的栅极绝缘膜; 在栅极绝缘膜上形成栅电极; 在栅电极的侧面形成间隔物; 以及在栅电极的侧表面处形成源/漏杂质区。

120. 发明申请

US20070164758A1 Method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device 失效
标题翻译：测量MOS晶体管器件中栅极氧化物的平带状态电容的方法
公开(公告)号：US20070164758A1
公开(公告)日：2007-07-19
申请号：US11646515
申请日：2006-12-28
申请人： Chang Jang
发明人： Chang Jang
IPC分类号： G01R27/26
CPC分类号： G01R31/2621 , G01R27/2605 , H01L22/14
摘要： A method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device, comprises: mounting a measurement object wafer in a probe station connected to a capacitance measuring unit; measuring accumulation capacitance (Cox) of a gate oxide of the wafer using the capacitance measuring unit; measuring capacitance (Cmeas) from the gate while changing a gate voltage (Vgs) of the wafer using the capacitance measuring unit; computing the thickness of a depletion layer (Winv) using the measured accumulation capacitance (Cox) and the measured gate capacitance (Cmeas); computing bulk density (Nx) on the basis of the gate voltage (Vgs) in the case that depth of a depletion layer is 90% of a predetermined reference depth; computing debye length LD using the bulk density (Nx); and computing flat-band status capacitance using the accumulation capacitance (Cox) of the gate oxide and the debye length LD.
摘要翻译：一种测量MOS晶体管器件中的栅极氧化物的平带状态电容的方法，包括：将测量对象晶片安装在连接到电容测量单元的探测台中; 使用所述电容测量单元测量所述晶片的栅极氧化物的累积电容（C ox ox）; 使用所述电容测量单元改变所述晶片的栅极电压（V SUB），从所述栅极测量电容（C 测量）; 使用所测量的累积电容（C ox ox）和所测量的栅极电容（C SUB）来计算耗尽层的厚度（W＆gt; inv＆lt; / SUB） ; 在耗尽层的深度为预定参考深度的90％的情况下，基于栅极电压（V SUB）来计算体积密度（Nx）; 使用体积密度（Nx）计算去拜耳长度L D D

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