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111. 发明授权

US07566927B2 Flash memory device 有权
标题翻译：闪存设备
公开(公告)号：US07566927B2
公开(公告)日：2009-07-28
申请号：US10840580
申请日：2004-05-07
申请人： Moo-Sung Kim , Yeong-Taek Lee , Seung-Jae Lee
发明人： Moo-Sung Kim , Yeong-Taek Lee , Seung-Jae Lee
IPC分类号： H01L29/788
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , H01L27/115
摘要： A flash memory device may include a memory cell array having a plurality of word lines, bit lines, and memory cells. Each memory cell may be arranged at an intersection of a corresponding word line and a corresponding bit line. The device may include a bit line voltage setting circuit for setting a voltage on a bit line of a given memory cell to be programmed to a variable bit line voltage or to a ground voltage. A variable bit line voltage generating circuit may be provided in the flash memory device for generating the variable bit line voltage. To facilitating programming of the device, a bit line voltage of a given memory cell to be programmed may be set based on a supply voltage of the device, so as to maintain a voltage difference based on the set bit line voltage above a given threshold voltage.
摘要翻译：闪存器件可以包括具有多个字线，位线和存储器单元的存储单元阵列。每个存储单元可以被布置在对应的字线和对应的位线的交叉点处。该设备可以包括位线电压设置电路，用于将要编程的给定存储器单元的位线上的电压设置为可变位线电压或接地电压。可变位线电压产生电路可以设置在闪存器件中，用于产生可变位线电压。为了便于设备的编程，可以基于设备的电源电压来设置要编程的给定存储器单元的位线电压，以便基于设定的位线电压维持高于给定阈值电压的电压差。

112. 发明申请

US20090162713A1 STACK FOR FUEL CELL AND BIPOLAR PLATE AND COOLING PLATE ADOPTED IN THE SAME 审中-公开
标题翻译：用于燃料电池和双极板和冷却板的堆叠同时通过
公开(公告)号：US20090162713A1
公开(公告)日：2009-06-25
申请号：US12047627
申请日：2008-03-13
申请人： Jie PENG , Jae-Young Shin , Seung-Jae Lee
发明人： Jie PENG , Jae-Young Shin , Seung-Jae Lee
IPC分类号： H01M8/02 , F28D15/00
CPC分类号： H01M2/1083 , F28F3/12
摘要： Provided is a stack of a fuel cell in which a plurality of unit cells are stacked to perform an electricity generation reaction. The stack includes a membrane electrode assembly in which an anode, an electricity membrane, and a cathode are stacked; a bipolar plate having reactant channels through which fluids to be supplied to the anode and the cathode flow and a plurality of inner manifolds that are formed in positions not directly connected to the reactant channels so that a coolant pass through; and a cooling plate having a coolant channels through which a coolant flows and a plurality of inner manifolds that are formed corresponding to the inner manifolds of the bipolar plate so that the coolant pass through.
摘要翻译：提供了堆叠多个单位电池进行发电反应的燃料电池的堆叠。堆叠包括其中堆叠阳极，电膜和阴极的膜电极组件; 具有反应物通道的双极板，待供应到阳极和阴极流的流体和多个内歧管，其形成在不直接连接到反应物通道的位置，使得冷却剂通过; 以及具有冷却剂流过的冷却剂通道的冷却板和对应于双极板的内部歧管形成的多个内部歧管，使得冷却剂通过。

113. 发明申请

US20090158437A1 METHOD AND SYSTEM FOR DIGITAL RIGHTS MANAGEMENT AMONG APPARATUSES 失效
标题翻译：设备数字管理方法与系统
公开(公告)号：US20090158437A1
公开(公告)日：2009-06-18
申请号：US12092536
申请日：2006-10-31
申请人： Te-Hyun Kim , Seung-Jae Lee
发明人： Te-Hyun Kim , Seung-Jae Lee
IPC分类号： G06F21/00
CPC分类号： H04L9/0825 , H04L9/0891 , H04L63/06 , H04L63/0853 , H04L2209/603 , H04L2463/101
摘要： A digital rights management (DRM) method and system between devices are disclosed. In order to allow a first device connected with a second device to use a rights object (RO) bound to the second device, the second device decodes the particular content or the RO and transmits the decoded particular content or the decoded RO to the first device. State information of the RO according to a usage amount of the particular content used by the first device is managed by the second device.
摘要翻译：披露了设备之间的数字版权管理（DRM）方法和系统。为了允许与第二设备连接的第一设备使用与第二设备绑定的权限对象（RO），第二设备对特定内容或RO进行解码，并将解码的特定内容或解码的RO发送到第一设备。根据第一设备使用的特定内容的使用量的RO的状态信息由第二设备管理。

114. 发明授权

US07512020B2 Nonvolatile memory device with load-free wired-OR structure and an associated driving method 有权
标题翻译：非易失性存储器件，具有无负载的有线OR结构和相关的驱动方法
公开(公告)号：US07512020B2
公开(公告)日：2009-03-31
申请号：US11319324
申请日：2005-12-27
申请人： Seung-Jae Lee
发明人： Seung-Jae Lee
IPC分类号： G11C7/10
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/24 , G11C16/3454
摘要： A nonvolatile semiconductor memory device includes an internal output line, and a page buffers. Each page buffer is coupled to at least one bitline, the internal output line, and a data input line physically distinct from the internal output line, and configured to pull the internal output line to an output drive voltage in response to a bitline voltage on one of the bitlines coupled to the page buffer.
摘要翻译：非易失性半导体存储器件包括内部输出线和页缓冲器。每个页缓冲器耦合到至少一个位线，内部输出线和物理上不同于内部输出线的数据输入线，并且被配置为响应于一个位线电压将内部输出线拉到输出驱动电压的位线耦合到页面缓冲区。

115. 发明授权

US07442607B2 Method of manufacturing transistor having recessed channel 失效
标题翻译：制造具有凹槽的晶体管的方法
公开(公告)号：US07442607B2
公开(公告)日：2008-10-28
申请号：US11533273
申请日：2006-09-19
申请人： Min Kim , Ju-Bum Lee , Hyeong-Deok Lee , Seung-Jae Lee
发明人： Min Kim , Ju-Bum Lee , Hyeong-Deok Lee , Seung-Jae Lee
IPC分类号： H01L21/00
CPC分类号： H01L29/66621 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/7835
摘要： A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.
摘要翻译：提供一种制造具有凹槽的晶体管的方法。该方法包括在半导体衬底上形成用于凹陷沟道的沟槽，在其上形成有沟槽的半导体衬底上沉积隔离层，在半导体衬底上沉积栅极电介质层，使得栅极电介质层可以延伸到底部，沟槽的侧壁，形成用于填充沟槽的栅极，以及在与栅极相邻的半导体衬底中形成源区和漏区。

116. 发明申请

US20080155646A1 Rights Object, Rights Object Issuing Method, and Contents Controlling Method Using the Same in Digital Rights Management 审中-公开
标题翻译：权利对象，权利对象发布方法和数字版权管理中的使用内容控制方法
公开(公告)号：US20080155646A1
公开(公告)日：2008-06-26
申请号：US11911709
申请日：2006-05-23
申请人： Seung-Jae Lee
发明人： Seung-Jae Lee
IPC分类号： G06F21/00
CPC分类号： G06F21/10 , G06F2221/2135 , G06F2221/2137
摘要： Provided are a rights object, a rights object issuing method, and a contents controlling method using the same, wherein when a Digital Rights Management (DRM) having received a request for operating a certain content receives a rights object including pre-use constraint information with respect to another content in order to use the corresponding certain content, the DRM agent operates the corresponding content if every operation designated in the pre-use constraint information or at least one or more of the operations are performed to thus satisfy the constraint.
摘要翻译：提供了一种权利对象，权利对象发布方法和使用该权利对象发布方法的内容控制方法，其中当已经接收到用于操作某个内容的操作的请求的数字版权管理（DRM）接收到包括预先使用的约束信息的权利对象时，为了使用相应的特定内容，DRM代理操作相应的内容，如果执行在预先使用约束信息中指定的每个操作或执行至少一个或多个操作以满足约束条件。

117. 发明申请

US20070038576A1 Method for moving rights object in digital rights management 审中-公开
标题翻译：在数字版权管理中移动权利对象的方法
公开(公告)号：US20070038576A1
公开(公告)日：2007-02-15
申请号：US11502460
申请日：2006-08-11
申请人： Seung-Jae Lee
发明人： Seung-Jae Lee
IPC分类号： G06Q99/00
CPC分类号： H04L63/065 , G06F21/10 , G06F2221/0786 , H04L63/0428 , H04L63/104 , H04L2463/101
摘要： A method for moving Rights Object (RO) in a Digital Rights Management (DRM). RO for content is partially or entirely moved between Devices in the same group, so that the RO can be shared between the Devices and a utility thereof can be enhanced.
摘要翻译：一种在数字版权管理（DRM）中移动权限对象（RO）的方法。用于内容的RO部分或全部在同一组中的设备之间移动，从而可以在设备之间共享RO，并且可以增强其效用。

118. 发明申请

US20070028155A1 Flash memory device having single page buffer structure and related programming method 失效
标题翻译：具有单页缓冲结构和相关编程方法的闪存器件
公开(公告)号：US20070028155A1
公开(公告)日：2007-02-01
申请号：US11363030
申请日：2006-02-28
申请人： Moo-Sung Kim , Seung-Jae Lee
发明人： Moo-Sung Kim , Seung-Jae Lee
IPC分类号： H03M13/00
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5622 , G11C2216/14
摘要： A flash memory device is disclosed that comprises memory cells, a sense node connected to a selected bit line, a sense circuit configured to selectively provide a first voltage to a common node in accordance with a voltage level of the sense node, a first register connected to the sense node and the common node and configured to store data in accordance with a voltage level of the common node,a second register configured to store data in accordance with the voltage level of the sense node, a switch configured to provide a second voltage to the second register, and a discharge circuit configured to selectively discharge the sense node in accordance with the data stored in the second register.
摘要翻译：公开了一种闪速存储器件，其包括存储器单元，连接到所选位线的感测节点，感测电路，被配置为根据感测节点的电压电平有选择地向公共节点提供第一电压;第一寄存器连接到所述感测节点和所述公共节点，并且被配置为根据所述公共节点的电压电平来存储数据;第二寄存器，被配置为根据所述感测节点的电压电平来存储数据;被配置为提供第二电压以及放电电路，其被配置为根据存储在第二寄存器中的数据选择性地放电感测节点。

119. 发明申请

US20070020882A1 METHOD OF MANUFACTURING TRANSISTOR HAVING RECESSED CHANNEL 失效
标题翻译：制造具有通道的晶体管的方法
公开(公告)号：US20070020882A1
公开(公告)日：2007-01-25
申请号：US11533273
申请日：2006-09-19
申请人： Min Kim , Ju-Bum Lee , Hyeong-Deok Lee , Seung-Jae Lee
发明人： Min Kim , Ju-Bum Lee , Hyeong-Deok Lee , Seung-Jae Lee
IPC分类号： H01L21/76
CPC分类号： H01L29/66621 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/7835
摘要： A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.
摘要翻译：提供一种制造具有凹槽的晶体管的方法。该方法包括在半导体衬底上形成用于凹陷沟道的沟槽，在其上形成有沟槽的半导体衬底上沉积隔离层，在半导体衬底上沉积栅极电介质层，使得栅极电介质层可以延伸到底部，沟槽的侧壁，形成用于填充沟槽的栅极，以及在与栅极相邻的半导体衬底中形成源区和漏区。

120. 发明申请

US20060109715A1 NAND flash memory device capable of improving read speed 有权
标题翻译： NAND闪存器件能够提高读取速度
公开(公告)号：US20060109715A1
公开(公告)日：2006-05-25
申请号：US11285273
申请日：2005-11-22
申请人： Seung-Jae Lee , Jung-Hoon Park
发明人： Seung-Jae Lee , Jung-Hoon Park
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C29/846
摘要： A NAND flash memory device according to the present invention is provided which includes a first page buffer circuit reading main data bits from the main field during a read operation, a second page buffer circuit reading redundant data bits from the redundancy field during the read operation, a first column gate circuit configured to select a part of the read main data bits and a part of the read redundant data bits in response to first column selection signals at the same time, and a second column gate circuit configured to select a part of the selected main data bits in response to second column selection signals.
摘要翻译：提供了根据本发明的NAND闪速存储器件，其包括在读操作期间从主场读取主数据位的第一页缓冲电路，在读操作期间从冗余字段读取冗余数据位的第二页缓冲电路，第一列门电路，被配置为响应于第一列选择信号同时选择读取的主数据位的一部分和读取的冗余数据位的一部分;以及第二列门电路，被配置为选择一部分选择的主数据位响应于第二列选择信号。

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