专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07442607B2 Method of manufacturing transistor having recessed channel 失效
标题翻译：制造具有凹槽的晶体管的方法
公开(公告)号：US07442607B2
公开(公告)日：2008-10-28
申请号：US11533273
申请日：2006-09-19
申请人： Min Kim , Ju-Bum Lee , Hyeong-Deok Lee , Seung-Jae Lee
发明人： Min Kim , Ju-Bum Lee , Hyeong-Deok Lee , Seung-Jae Lee
IPC分类号： H01L21/00
CPC分类号： H01L29/66621 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/7835
摘要： A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.
摘要翻译：提供一种制造具有凹槽的晶体管的方法。该方法包括在半导体衬底上形成用于凹陷沟道的沟槽，在其上形成有沟槽的半导体衬底上沉积隔离层，在半导体衬底上沉积栅极电介质层，使得栅极电介质层可以延伸到底部，沟槽的侧壁，形成用于填充沟槽的栅极，以及在与栅极相邻的半导体衬底中形成源区和漏区。

2. 发明申请

US20070020882A1 METHOD OF MANUFACTURING TRANSISTOR HAVING RECESSED CHANNEL 失效
标题翻译：制造具有通道的晶体管的方法
公开(公告)号：US20070020882A1
公开(公告)日：2007-01-25
申请号：US11533273
申请日：2006-09-19
申请人： Min Kim , Ju-Bum Lee , Hyeong-Deok Lee , Seung-Jae Lee
发明人： Min Kim , Ju-Bum Lee , Hyeong-Deok Lee , Seung-Jae Lee
IPC分类号： H01L21/76
CPC分类号： H01L29/66621 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/7835
摘要： A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.
摘要翻译：提供一种制造具有凹槽的晶体管的方法。该方法包括在半导体衬底上形成用于凹陷沟道的沟槽，在其上形成有沟槽的半导体衬底上沉积隔离层，在半导体衬底上沉积栅极电介质层，使得栅极电介质层可以延伸到底部，沟槽的侧壁，形成用于填充沟槽的栅极，以及在与栅极相邻的半导体衬底中形成源区和漏区。

3. 发明授权

US07125774B2 Method of manufacturing transistor having recessed channel 失效
标题翻译：制造具有凹槽的晶体管的方法
公开(公告)号：US07125774B2
公开(公告)日：2006-10-24
申请号：US10937532
申请日：2004-09-08
申请人： Min Kim , Ju-Bum Lee , Hyeon-Deok Lee , Seung-Jae Lee
发明人： Min Kim , Ju-Bum Lee , Hyeon-Deok Lee , Seung-Jae Lee
IPC分类号： H01L21/336 , H01L21/76 , H01L21/3205
CPC分类号： H01L29/66621 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/7835
摘要： A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.
摘要翻译：提供一种制造具有凹槽的晶体管的方法。该方法包括在半导体衬底上形成用于凹陷沟道的沟槽，在其上形成有沟槽的半导体衬底上沉积隔离层，在半导体衬底上沉积栅极电介质层，使得栅极电介质层可以延伸到底部，沟槽的侧壁，形成用于填充沟槽的栅极，以及在与栅极相邻的半导体衬底中形成源区和漏区。

4. 发明申请

US20050054163A1 Method of manufacturing transistor having recessed channel 失效
标题翻译：制造具有凹槽的晶体管的方法
公开(公告)号：US20050054163A1
公开(公告)日：2005-03-10
申请号：US10937532
申请日：2004-09-08
申请人： Min Kim , Ju-Bum Lee , Hyeon-Deok Lee , Seung-Jae Lee
发明人： Min Kim , Ju-Bum Lee , Hyeon-Deok Lee , Seung-Jae Lee
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/51 , H01L29/78
CPC分类号： H01L29/66621 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/7835
摘要： A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.
摘要翻译：提供一种制造具有凹槽的晶体管的方法。该方法包括在半导体衬底上形成用于凹陷沟道的沟槽，在其上形成有沟槽的半导体衬底上沉积隔离层，在半导体衬底上沉积栅极电介质层，使得栅极电介质层可以延伸到底部，沟槽的侧壁，形成用于填充沟槽的栅极，以及在与栅极相邻的半导体衬底中形成源区和漏区。

5. 发明申请

US20050101143A1 Methods of fabricating a semiconductor device and forming a trench region in a semiconductor device 审中-公开
标题翻译：制造半导体器件并在半导体器件中形成沟槽区域的方法
公开(公告)号：US20050101143A1
公开(公告)日：2005-05-12
申请号：US10911730
申请日：2004-08-05
申请人： Seung-Jae Lee , Min Kim , Jai-Dong Lee , Kyoung-Seok Kim , Hyeon-Deok Lee , Ju-Bum Lee , Hun-Hyeoung Leam
发明人： Seung-Jae Lee , Min Kim , Jai-Dong Lee , Kyoung-Seok Kim , Hyeon-Deok Lee , Ju-Bum Lee , Hun-Hyeoung Leam
IPC分类号： H01L21/76 , H01L21/308 , H01L21/311 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/3081 , H01L21/3086
摘要： In a method of forming a shallow trench isolation (STI) region in a semiconductor device, a pad oxide layer and a pad nitride layer may be formed on a semiconductor substrate. The pad nitride layer and pad oxide layer may be patterned to form an isolation region with exposed portions on the pad nitride layer, pad oxide layer and semiconductor substrate. A radical oxide layer may be formed on the exposed portions, and a trench may be formed in the isolation region by etching the semiconductor substrate and radical oxide layer. The STI region may be formed by filling an insulating layer in the trench.
摘要翻译：在半导体器件中形成浅沟槽隔离（STI）区域的方法中，衬底氧化物层和衬底氮化物层可以形成在半导体衬底上。衬垫氮化物层和焊盘氧化物层可以被图案化以形成具有在衬垫氮化物层，焊盘氧化物层和半导体衬底上的暴露部分的隔离区域。可以在暴露部分上形成自由基氧化物层，并且可以通过蚀刻半导体衬底和自由基氧化物层在隔离区域中形成沟槽。可以通过在沟槽中填充绝缘层来形成STI区域。

6. 发明授权

US07439150B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07439150B2
公开(公告)日：2008-10-21
申请号：US11245367
申请日：2005-10-05
申请人： Shin-Hye Kim , Ju-Bum Lee , Min Kim
发明人： Shin-Hye Kim , Ju-Bum Lee , Min Kim
IPC分类号： H01L21/20
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： In one embodiment, to fabricate a semiconductor device, a first insulation interlayer is formed on a substrate. A contact pad is formed through the first insulation interlayer. An etch stop layer and a second insulation interlayer are sequentially formed on the first insulation interlayer and the pad. A contact hole exposing at least a portion of the contact pad is formed by partially etching the second insulation interlayer and the etch stop layer. A preliminary lower electrode is formed in the hole. The preliminary lower electrode is isotropically etched to form a lower electrode contacting the contact pad. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.
摘要翻译：在一个实施例中，为了制造半导体器件，在衬底上形成第一绝缘中间层。通过第一绝缘夹层形成接触垫。在第一绝缘夹层和衬垫上依次形成蚀刻停止层和第二绝缘中间层。通过部分蚀刻第二绝缘夹层和蚀刻停止层来形成暴露接触焊盘的至少一部分的接触孔。在孔中形成初级下电极。预备下电极被各向同性地蚀刻以形成接触接触垫的下电极。电介质层和上电极依次形成在下电极上。

7. 发明申请

US20050009293A1 Method of forming trench isolations 失效
标题翻译：形成沟槽隔离的方法
公开(公告)号：US20050009293A1
公开(公告)日：2005-01-13
申请号：US10822378
申请日：2004-04-12
申请人： Hong-Rae Kim , Ju-Bum Lee , Min Kim
发明人： Hong-Rae Kim , Ju-Bum Lee , Min Kim
IPC分类号： H01L21/76 , H01L21/762 , H01L21/336
CPC分类号： H01L21/76229
摘要： Methods of forming trench isolations are provided. A method includes providing a semiconductor substrate having a cell array region and a peripheral region. At least one cell trench in the cell array region and at least one peripheral trench wider than the cell trench in the peripheral region of the substrate are formed. The cell and the peripheral trenches have sidewalls. A first dielectric layer that partially fills the cell and peripheral trenches is formed over the substrate. At least one photoresist pattern that exposes at least the cell trench partially filled with the first dielectric layer is formed over the substrate. The first dielectric layer formed on the sidewalls of the exposed cell trench is etched by using the photoresist pattern as a etch mask. Subsequently, the photoresist pattern is removed. A second dielectric layer filling the cell and peripheral trenches is formed over the substrate where the photoresist pattern is removed.
摘要翻译：提供了形成沟槽隔离的方法。一种方法包括提供具有单元阵列区域和周边区域的半导体衬底。形成电池阵列区域中的至少一个电池沟道和比衬底的周边区域中的电池沟槽宽的至少一个外围沟槽。电池和外围沟槽具有侧壁。部分填充电池和外围沟槽的第一电介质层形成在衬底上。在衬底上形成至少一个曝光至少部分填充有第一介电层的单元沟道的光致抗蚀剂图案。通过使用光致抗蚀剂图案作为蚀刻掩模蚀刻形成在暴露的单元沟槽的侧壁上的第一介电层。随后，去除光致抗蚀剂图案。在衬底上形成填充电池和外围沟槽的第二电介质层，其中光致抗蚀剂图案被去除。

8. 发明申请

US20060073669A1 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20060073669A1
公开(公告)日：2006-04-06
申请号：US11245367
申请日：2005-10-05
申请人： Shin-Hye Kim , Ju-Bum Lee , Min Kim
发明人： Shin-Hye Kim , Ju-Bum Lee , Min Kim
IPC分类号： H01L21/20
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： In one embodiment, to fabricate a semiconductor device, a first insulation interlayer is formed on a substrate. A contact pad is formed through the first insulation interlayer. An etch stop layer and a second insulation interlayer are sequentially formed on the first insulation interlayer and the pad. A contact hole exposing at least a portion of the contact pad is formed by partially etching the second insulation interlayer and the etch stop layer. A preliminary lower electrode is formed in the hole. The preliminary lower electrode is isotropically etched to form a lower electrode contacting the contact pad. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.
摘要翻译：在一个实施例中，为了制造半导体器件，在衬底上形成第一绝缘中间层。通过第一绝缘夹层形成接触垫。在第一绝缘夹层和衬垫上依次形成蚀刻停止层和第二绝缘中间层。通过部分蚀刻第二绝缘夹层和蚀刻停止层来形成暴露接触焊盘的至少一部分的接触孔。在孔中形成初级下电极。预备下电极被各向同性地蚀刻以形成接触接触垫的下电极。电介质层和上电极依次形成在下电极上。

9. 发明授权

US07033909B2 Method of forming trench isolations 失效
标题翻译：形成沟槽隔离的方法
公开(公告)号：US07033909B2
公开(公告)日：2006-04-25
申请号：US10822378
申请日：2004-04-12
申请人： Hong-Rae Kim , Ju-Bum Lee , Min Kim
发明人： Hong-Rae Kim , Ju-Bum Lee , Min Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： Methods of forming trench isolations are provided. A method includes providing a semiconductor substrate having a cell array region and a peripheral region. At least one cell trench in the cell array region and at least one peripheral trench wider than the cell trench in the peripheral region of the substrate are formed. The cell and the peripheral trenches have sidewalls. A first dielectric layer that partially fills the cell and peripheral trenches is formed over the substrate. At least one photoresist pattern that exposes at least the cell trench partially filled with the first dielectric layer is formed over the substrate. The first dielectric layer formed on the sidewalls of the exposed cell trench is etched by using the photoresist pattern as a etch mask. Subsequently, the photoresist pattern is removed. A second dielectric layer filling the cell and peripheral trenches is formed over the substrate where the photoresist pattern is removed.
摘要翻译：提供了形成沟槽隔离的方法。一种方法包括提供具有单元阵列区域和周边区域的半导体衬底。形成电池阵列区域中的至少一个电池沟道和比衬底的周边区域中的电池沟槽宽的至少一个外围沟槽。电池和外围沟槽具有侧壁。部分填充电池和外围沟槽的第一电介质层形成在衬底上。在衬底上形成至少一个曝光至少部分填充有第一介电层的单元沟道的光致抗蚀剂图案。通过使用光致抗蚀剂图案作为蚀刻掩模蚀刻形成在暴露的单元沟槽的侧壁上的第一介电层。随后，去除光致抗蚀剂图案。在衬底上形成填充电池和外围沟槽的第二电介质层，其中光致抗蚀剂图案被去除。

10. 发明授权

US07163869B2 Shallow trench isolation structure with converted liner layer 有权
标题翻译：浅沟槽隔离结构具有转换内衬层
公开(公告)号：US07163869B2
公开(公告)日：2007-01-16
申请号：US10947481
申请日：2004-09-22
申请人： Shin-Hye Kim , Min Kim , Seung-Jae Lee
发明人： Shin-Hye Kim , Min Kim , Seung-Jae Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A STI (shallow trench isolation) structure is formed with a liner layer that is converted from an initial material to a subsequent material. For example, the liner layer is initially comprised of nitride during wet etch-back of a dielectric fill material comprised of oxide to protect an oxide layer on a semiconductor substrate. Thereafter, an exposed portion of the liner layer is converted into the subsequent material of oxide to protect the dielectric fill material within the STI opening during etching away of masking layers to prevent formation of dents in the STI structure.
摘要翻译： STI（浅沟槽隔离）结构形成有从初始材料转换成后续材料的衬里层。例如，在由氧化物构成的介电填充材料的湿法回蚀期间，衬垫层最初由氮化物组成，以保护半导体衬底上的氧化物层。此后，衬里层的暴露部分被转换成随后的氧化物材料，以在蚀刻掉掩模层期间保护STI开口内的介电填充材料，以防止在STI结构中形成凹痕。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式