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111. 发明申请

US20100109675A1 METHOD TO DIGITIZE ANALOG SIGNALS IN A SYSTEM UTILIZING DYNAMIC ANALOG TEST MULTIPLEXER FOR DIAGNOSTICS 有权
标题翻译：用于诊断动态模拟测试多路复用器的系统中的模拟信号的方法
公开(公告)号：US20100109675A1
公开(公告)日：2010-05-06
申请号：US12263290
申请日：2008-10-31
申请人： Wilson Wong , Allen Chan , Sergey Shumarayev
发明人： Wilson Wong , Allen Chan , Sergey Shumarayev
IPC分类号： G01R31/02
CPC分类号： G01R31/3167
摘要： An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.
摘要翻译：提出了一种能够监视模拟模块内的模拟电压的集成电路。集成电路具有模拟测试复用器（多路复用器），其输入端连接到模拟模块内的感兴趣的模拟电压。模拟测试复用器将选定的模拟电压从模拟模块引导到模拟测试复用器的输出。集成电路还包括模拟监视状态机，其向模拟测试多路复用器提供选择位，使得能够随机访问模拟块内的模拟电压。集成电路还包括用于将来自模拟测试多路复用器的所选模拟电压转换为数字表示的模数转换器。

112. 发明申请

US20100086017A1 Automatic calibration in high-speed serial interface receiver circuitry 有权
标题翻译：高速串行接口电路自动校准
公开(公告)号：US20100086017A1
公开(公告)日：2010-04-08
申请号：US12287009
申请日：2008-10-02
申请人： Sergey Shumarayev , Wilson Wong
发明人： Sergey Shumarayev , Wilson Wong
IPC分类号： H04L27/01
CPC分类号： H04L25/03885 , H04B3/04 , H04L1/205 , H04L25/03019
摘要： Circuitry for receiving a serial data signal (e.g., a high-speed serial data signal) includes adjustable equalizer circuitry for producing an equalized version of the serial data signal. The equalizer circuitry may include controllably variable DC gain and controllably variable AC gain. The circuitry may further include eye height and eye width monitor circuitry for respectively producing first and second output signals indicative of the height and width of the eye of the equalized version. The first output signal may be used in control of the DC gain of the equalizer circuitry, and the second output signal may be used in control of the AC gain of the equalizer circuitry.
摘要翻译：用于接收串行数据信号（例如，高速串行数据信号）的电路包括用于产生串行数据信号的均衡版本的可调均衡器电路。均衡器电路可以包括可控制的可变DC增益和可控可变的AC增益。电路还可以包括眼睛高度和眼睛宽度监视器电路，用于分别产生指示均衡版本的眼睛的高度和宽度的第一和第二输出信号。第一输出信号可用于控制均衡器电路的直流增益，并且第二输出信号可用于控制均衡器电路的AC增益。

113. 发明申请

US20100073094A1 Techniques For Generating Fractional Clock Signals 有权
标题翻译：用于生成小数时钟信号的技术
公开(公告)号：US20100073094A1
公开(公告)日：2010-03-25
申请号：US12234114
申请日：2008-09-19
申请人： Tim Tri Hoang , Wilson Wong , Sergey Shumarayev
发明人： Tim Tri Hoang , Wilson Wong , Sergey Shumarayev
IPC分类号： H03L7/085
CPC分类号： H03L7/099 , H03L7/18
摘要： A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency divided signal. The first and the second frequency divided signals are routed to the phase detection circuitry as the feedback signal during different time intervals.
摘要翻译：电路包括相位检测电路，时钟信号发生电路，第一分频器和第二分频器。相位检测电路将输入时钟信号与反馈信号进行比较以产生控制信号。时钟信号产生电路响应于控制信号产生周期性输出信号。第一分频器将周期性输出信号的频率除以第一值，以产生第一分频信号。第二分频器将周期性输出信号的频率除以第二值，以产生第二分频信号。在不同的时间间隔期间，第一和第二分频信号作为反馈信号被路由到相位检测电路。

114. 发明申请

US20090302888A1 INCREASED SENSITIVITY AND REDUCED OFFSET VARIATION IN HIGH DATA RATE HSSI RECEIVER 有权
标题翻译：在高数据速率HSSI接收器中提高灵敏度和降低偏移
公开(公告)号：US20090302888A1
公开(公告)日：2009-12-10
申请号：US12134777
申请日：2008-06-06
申请人： Sergey Shumarayev , Thungoc M. Tran , Wilson Wong , Simardeep Maangat
发明人： Sergey Shumarayev , Thungoc M. Tran , Wilson Wong , Simardeep Maangat
IPC分类号： H03K19/0175
CPC分类号： H03K19/018514 , H03F3/45197 , H03F2203/45494 , H03F2203/45686
摘要： Signal offset variation caused by transistor variation/mismatch in integrated circuits may be reduced. In one embodiment, a buffer circuit has variable-valued circuits elements. Offset variation measurements are made and the variable-valued circuit elements are calibrated to reduce the measured offset variation. In another embodiment, each amplifying stage of a multi-stage buffer provides variable gain. The total DC gain of the cascade is distributed unevenly across the stages, with more DC gain being provided by amplifier stages at the beginning of the cascade than at the end. An additional pre-amplifier stage can also be provided at the beginning of the cascade.
摘要翻译：集成电路中晶体管变化/失配引起的信号偏移变化可能会降低。在一个实施例中，缓冲电路具有可变值电路元件。进行偏移变化测量，并校准可变值电路元件以减少测量的偏移变化。在另一个实施例中，多级缓冲器的每个放大级提供可变增益。级联的总直流增益不均匀地分布在整个级中，在级联开始时比放大器级提供更多的直流增益。在级联开始时也可以提供一个额外的前级放大器级。

115. 发明申请

US20080258765A1 Low-power transceiver architectures for programmable logic integrated circuit devices 有权
标题翻译：用于可编程逻辑集成电路器件的低功耗收发器架构
公开(公告)号：US20080258765A1
公开(公告)日：2008-10-23
申请号：US12214466
申请日：2008-06-18
申请人： Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Richard G. Cliff
发明人： Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Richard G. Cliff
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/17744 , H03K19/17784
摘要： High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit (“PLD”) includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In the latter case, any one or more of various features can be used to help reduce power consumption.
摘要翻译：可编程逻辑器件集成电路（“PLD”）上的高速串行接口或收发器电路包括允许PLD满足广泛可能的用户需求或应用的功能。该范围包括高性能应用和PLD降低功耗很重要的应用。在后一种情况下，可以使用各种特征中的任何一种或多种来帮助降低功耗。

116. 发明授权

US07414429B1 Integration of high-speed serial interface circuitry into programmable logic device architectures 有权
标题翻译：将高速串行接口电路集成到可编程逻辑器件架构中
公开(公告)号：US07414429B1
公开(公告)日：2008-08-19
申请号：US11486867
申请日：2006-07-14
申请人： In Whan Kim , Sergey Shumarayev , Tim Tri Hoang , Wilson Wong , Thungoc M. Tran
发明人： In Whan Kim , Sergey Shumarayev , Tim Tri Hoang , Wilson Wong , Thungoc M. Tran
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177 , H03K19/0175 , H01L25/00
CPC分类号： H03K19/17744
摘要： The architecture of a programmable logic device (“PLD”) is modified in one or more of several respects to facilitate inclusion of high-speed serial interface (“HSSI”) circuitry in the PLD. For example, the HSSI circuitry is preferably located along one side of the device, taking the place of regular peripheral IO circuitry in that area. Certain portions of the core logic circuitry are modified to better interface with the HSSI circuitry.
摘要翻译：可编程逻辑器件（“PLD”）的架构在几个方面中的一个或多个方面进行了修改，以便于在PLD中包含高速串行接口（“HSSI”）电路。例如，HSSI电路优选地位于设备的一侧，代替该区域中的常规外设IO电路。核心逻辑电路的某些部分被修改以更好地与HSSI电路接口。

117. 发明申请

US20070237186A1 Heterogeneous transceiver architecture for wide range programmability of programmable logic devices 有权
标题翻译：异构收发器架构，用于可编程逻辑器件的广泛可编程性
公开(公告)号：US20070237186A1
公开(公告)日：2007-10-11
申请号：US11402417
申请日：2006-04-11
申请人： Sergey Shumarayev , Bill Bereza , Chong Lee , Rakesh Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill Bereza , Chong Lee , Rakesh Patel , Wilson Wong
IPC分类号： H04J3/04
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

118. 发明申请

US20070013411A1 Apparatus and methods for programmable slew rate control in transmitter circuits 审中-公开
标题翻译：发射机电路中可编程转换速率控制的装置和方法
公开(公告)号：US20070013411A1
公开(公告)日：2007-01-18
申请号：US11183288
申请日：2005-07-14
申请人： Kazi Asaduzzaman , Sergey Shumarayev , Thungoc Tran , Wilson Wong , Rakesh Patel
发明人： Kazi Asaduzzaman , Sergey Shumarayev , Thungoc Tran , Wilson Wong , Rakesh Patel
IPC分类号： H03K19/094
CPC分类号： H03K17/164
摘要： High speed transmitter drivers and other types of driver circuitry may be required to produce output signals with variable slew rates. Driver circuitry and methods for providing variable slew rate control are described. Pre-driver circuitry with variable slew-rate may be used to supply signals with variable slew rate at the driver input. The driver and/or pre-driver circuits may include transistors with variable drive strengths. The driver and/or pre-driver circuits may also include selectably enabled stages for varying the circuit drive strength. The pre-driver circuitry may be delay matched to maintain signal quality. Other circuitry and methods are also described.
摘要翻译：可能需要高速变送器驱动器和其他类型的驱动电路来产生具有可变转换速率的输出信号。描述了用于提供可变转换速率控制的驱动电路和方法。可以使用具有可变转换速率的前驱动器电路在驱动器输入端提供具有可变转换速率的信号。驱动器和/或预驱动器电路可以包括具有可变驱动强度的晶体管。驱动器和/或预驱动器电路还可以包括用于改变电路驱动强度的可选择地启用的级。预驱动器电路可以被延迟匹配以保持信号质量。还描述了其它电路和方法。

119. 发明申请

US20060220681A1 Methods and apparatus to DC couple LVDS driver to CML levels 有权
标题翻译：将LVDS驱动程序直接耦合到CML级别的方法和设备
公开(公告)号：US20060220681A1
公开(公告)日：2006-10-05
申请号：US11098832
申请日：2005-04-04
申请人： Wilson Wong , Tim Hoang , Sergey Shumarayev , Rakesh Patel , Simardeep Maangat
发明人： Wilson Wong , Tim Hoang , Sergey Shumarayev , Rakesh Patel , Simardeep Maangat
IPC分类号： H03K19/094
CPC分类号： H03K19/017545
摘要： Circuitry and methods are provided for an LVDS-like transmitter that may be able to DC couple to a receiver having a CML termination scheme. Replacing the common mode voltage source of an LVDS transmitter with a resistive pulldown to ground may allow the transmitter to interface in a DC coupled fashion with a CML receiver. Further, the resistive pulldown may be programmable. This LVDS-like transmitter may be able to support a wider customer base by allowing it to DC couple to a wider range of termination voltage levels, such as CML termination voltage levels.
摘要翻译：为能够将DC耦合到具有CML终止方案的接收机的类似LVDS的发射机提供电路和方法。将具有电阻下拉到地的LVDS发射机的共模电压源替换可允许发射机以直流耦合方式与CML接收器接口。此外，电阻下拉可以是可编程的。这种类似LVDS的发射机可能能够通过允许其将DC耦合到更广泛的终止电压电平范围（例如CML终止电压电平）来支持更广泛的客户群。

120. 发明授权

US06980023B1 Dynamically adjustable signal detector 失效
标题翻译：动态可调信号检测器
公开(公告)号：US06980023B1
公开(公告)日：2005-12-27
申请号：US10668811
申请日：2003-09-22
申请人： Wilson Wong , Sergey Shumarayev
发明人： Wilson Wong , Sergey Shumarayev
IPC分类号： G01R31/3167 , G01R31/3193 , H03K5/1252 , H03K19/003 , H04L25/02
CPC分类号： G01R31/31932 , G01R31/3167 , H03K5/1252 , H03K19/003 , H04L25/0292
摘要： A dynamically adjustable signal detector receives a differential input signal and outputs a signal indicative of whether a valid signal is being received based on dynamically adjustable threshold settings. The threshold settings can include differential voltage, peak power, average power, or other suitable settings, and can have a dynamically adjustable value for a selected threshold setting. The threshold settings and the value for a selected threshold setting can be set using control signals that are set by programmable logic resource circuitry, by soft intellectual property programmed into a programmable logic resource, by a processor, by circuitry external to a programmable logic resource, or by user input.
摘要翻译：动态可调信号检测器接收差分输入信号，并且基于动态可调的阈值设置输出表示是否正在接收有效信号的信号。阈值设置可以包括差分电压，峰值功率，平均功率或其他适当的设置，并且可以为所选阈值设置具有动态可调整的值。可以使用由可编程逻辑资源电路设置的控制信号，通过编程到可编程逻辑资源中的软知识产权，由处理器，可编程逻辑资源外部的电路设置阈值设置和值，或用户输入。

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