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111. 发明授权

US06587924B2 Scarfing within a hierarchical memory architecture 有权
标题翻译：在分层内存架构中进行扫描
公开(公告)号：US06587924B2
公开(公告)日：2003-07-01
申请号：US09903727
申请日：2001-07-12
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , Y10S707/99931
摘要： A method and system for scarfing data during a data access transaction within a hierarchical data storage system. A data access request is delivered from a source device to a plurality of data storage devices. The access request includes a target address and a source path tag, wherein the source path tag includes a device identification tag that uniquely identifies a data storage device within a given level of the system traversed by the access request. A device identification tag that uniquely identifies the third party transactor within a given memory level is appended to the source path tag such that the third party transactor can scarf returning data without reserving a scarf queue entry.
摘要翻译：一种用于在分层数据存储系统内的数据访问事务期间对数据进行分页的方法和系统。数据访问请求从源设备传送到多个数据存储设备。访问请求包括目标地址和源路径标签，其中源路径标签包括唯一地标识由访问请求遍历的系统的给定级别内的数据存储设备的设备标识标签。唯一地标识给定存储器级别内的第三方交易者的设备识别标签被附加到源路径标签，使得第三方交易者可以围绕返回数据而不预留围巾队列条目。

112. 发明授权

US06505277B1 Method for just-in-time delivery of load data by intervening caches 失效
标题翻译：通过插入缓存来及时传送负载数据的方法
公开(公告)号：US06505277B1
公开(公告)日：2003-01-07
申请号：US09344057
申请日：1999-06-25
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0806 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F12/0811 , G06F12/0859
摘要： A method for ordering the time of issue of a load instruction from a lower level (L2) intervening cache, interlinked by a system bus to a first L2 cache. The method comprises the steps of (i) appending a cycle of dependency (CoD) value to said load instruction, where the CoD value corresponds to a specified time, measured in cycles, on a synchronized timer (ST) at which the data is required by a downstream dependency, (ii) monitoring when a search of the first cache by said load instruction results in a miss, (iii) searching the load instruction at the second cache when the miss is detected, and (iv) providing the data requested by the load instruction from the intervening cache to a pipeline of a system resource of said first L2 cache at the specified time.
摘要翻译：一种用于从由下一级（L2）中间缓存发出加载指令的时间的方法，该系统总线与第一L2高速缓存相互连接。该方法包括以下步骤：（i）将附加循环（CoD）值附加到所述加载指令，其中CoD值对应于在需要数据的同步定时器（ST）上以周期测量的指定时间通过下游依赖性，（ii）监视当所述加载指令对第一高速缓存的搜索导致错过时，（iii）在检测到未命中时搜索第二高速缓存上的加载指令，以及（iv）提供所请求的数据通过在指定时间从中间缓存到所述第一L2高速缓存的系统资源的流水线的加载指令。

113. 发明授权

US06374330B1 Cache-coherency protocol with upstream undefined state 失效
标题翻译：具有上行未定义状态的缓存一致性协议
公开(公告)号：US06374330B1
公开(公告)日：2002-04-16
申请号：US08839545
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0811 , G06F12/0831
摘要： A method of maintaining cache-coherency in a multi-processor computer system provides new states to indicate that a sector in an upstream cache has been modified, without executing unnecessary bus transactions for the lower-level cache(s). These new “U” states can indicate which sector in the cache line was modified, or if the cache line was the subject of a cachable write-through operation. The protocol is implemented as an improvement to the prior-art “MESI” cache-coherency protocol. The new protocol is especially useful in handling allocate-and-zero instructions wherein data is modified in the cache (zeroed out) without first fetching the old data from memory. In the embodiment wherein there are only two sectors in a given cache line, three new states are provided to indicate which sector was modified, or whether any cachable write-through operation was performed on the cache line of the first-level cache.
摘要翻译：在多处理器计算机系统中维持高速缓存一致性的方法提供新状态以指示上游缓存中的扇区已被修改，而不对下级缓存执行不必要的总线事务。这些新的“U”状态可以指示高速缓存行中的哪个扇区被修改，或者高速缓存行是高速缓存直写操作的主题。该协议被实现为对现有技术的“MESI”高速缓存一致性协议的改进。新协议在处理分配和零指令时特别有用，其中数据在缓存中被修改（清零），而无需先从存储器中取出旧数据。在给定高速缓存行中只有两个扇区的实施例中，提供了三个新状态来指示哪个扇区被修改，或者是否在第一级高速缓存的高速缓存行上执行了任何可高速缓存的直写操作。

114. 发明授权

US06341336B1 Cache coherency protocol having tagged state used with cross-bars 失效
标题翻译：具有标记状态的缓存一致性协议与交叉条使用
公开(公告)号：US06341336B1
公开(公告)日：2002-01-22
申请号：US09024676
申请日：1998-02-17
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1214
CPC分类号： G06F12/0833
摘要： A cache coherency protocol uses a “Tagged” coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migrate across the caches (horizontally) when assigned to a cache line that has most recently loaded the modified value. Historical states relating to the Tagged state may further be used. The invention may also be applied to a multi-processor computer system having clustered processing units, such that the Tagged state can be applied to one of the cache lines in each group of caches that support separate processing unit clusters. Priorities are assigned to different cache states, including the Tagged state, for responding to a request to access a corresponding memory block. Any tagged intervention response can be forwarded only to selected caches that could be affected by the intervention response, using cross-bars. The Tagged protocol can be combined with existing and new cache coherency protocols. The invention further contemplates independent optimization of cache operations using the Tagged state.
摘要翻译：高速缓存一致性协议使用“标记”一致性状态跟踪将修改后的值写回系统内存的责任，允许干预该值而不会立即将其写回系统内存，从而增加内存带宽。当分配给最近加载修改值的高速缓存行时，Tagged状态可以跨缓存迁移（水平）。与Tagged状态有关的历史状态可能会被进一步使用。本发明还可以应用于具有群集处理单元的多处理器计算机系统，使得标签状态可以应用于支持单独处理单元群集的每组高速缓存中的一个高速缓存行。优先级被分配给不同的缓存状态，包括标签状态，用于响应访问对应的存储器块的请求。任何标记的干预响应只能转发到可能受到干预响应影响的所选高速缓存，使用交叉条。标签协议可以与现有的和新的高速缓存一致性协议相结合。本发明进一步考虑使用标签状态对高速缓存操作的独立优化。

115. 发明授权

US06334172B1 Cache coherency protocol with tagged state for modified values 失效
标题翻译：缓存一致性协议，具有修改值的带状态
公开(公告)号：US06334172B1
公开(公告)日：2001-12-25
申请号：US09024393
申请日：1998-02-17
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0815
摘要： A cache coherency protocol uses a “Tagged” coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migrate across the caches (horizontally) when assigned to a cache line that has most recently loaded the modified value. Historical states relating to the Tagged state may further be used. The invention may also be applied to a multi-processor computer system having clustered processing units, such that the Tagged state can be applied to one of the cache lines in each group of caches that support separate processing unit clusters. Priorities are assigned to different cache states, including the Tagged state, for responding to a request to access a corresponding memory block. Any tagged intervention response can be forwarded only to selected caches that could be affected by the intervention response, using cross-bars. The Tagged protocol can be combined with existing and new cache coherency protocols. The invention further contemplates independent optimization of cache operations using the Tagged state.
摘要翻译：高速缓存一致性协议使用“标记”一致性状态跟踪将修改后的值写回系统内存的责任，允许干预该值而不会立即将其写回系统内存，从而增加内存带宽。当分配给最近加载修改值的高速缓存行时，Tagged状态可以跨缓存迁移（水平）。与Tagged状态有关的历史状态可能会被进一步使用。本发明还可以应用于具有群集处理单元的多处理器计算机系统，使得标签状态可以应用于支持单独处理单元群集的每组高速缓存中的一个高速缓存行。优先级被分配给不同的缓存状态，包括标签状态，用于响应访问对应的存储器块的请求。任何标记的干预响应只能转发到可能受到干预响应影响的所选高速缓存，使用交叉条。标签协议可以与现有的和新的高速缓存一致性协议相结合。本发明进一步考虑使用标签状态对高速缓存操作的独立优化。

116. 发明授权

US6157980A Cache directory addressing scheme for variable cache sizes 失效
标题翻译：用于可变缓存大小的缓存目录寻址方案
公开(公告)号：US6157980A
公开(公告)日：2000-12-05
申请号：US46016
申请日：1998-03-23
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/0864
摘要： To avoid multiplexing within the critical address path, the same field from an address is employed to index rows within a cache directory and memory regardless of the size of the cache memory. Depending on the size of the cache memory being employed, different address bits (such as Add[12] or Add[25] are employed as a "late select" for the last stage of multiplexing within the cache directory and cache memory. Since smaller address tag fields are employed for the larger cache memory size, the extra address tag bit is forced to a logic 1 within the cache directory and compared to a logic 1 by address tag comparators at the output of the cache directory.
摘要翻译：为了避免在关键地址路径中进行多路复用，来自地址的相同字段用于对高速缓存目录和存储器内的行进行索引，而与高速缓冲存储器的大小无关。根据所使用的高速缓冲存储器的大小，不同的地址位（例如Add [12]或Add [25]）被用作高速缓存目录和高速缓冲存储器内的最后一个复用阶段的“晚期选择” 地址标签字段用于较大的高速缓存存储器大小，额外地址标签位被强制为高速缓存目录内的逻辑1，并与高速缓存目录的输出处的地址标签比较器与逻辑1进行比较。

117. 发明授权

US6115794A Method and system of providing a pseudo-precise inclusivity scheme in a sectored cache memory for maintaining cache coherency within a data-processing system 失效
标题翻译：在扇区高速缓冲存储器中提供伪精确包含方案的方法和系统，用于维持数据处理系统内的高速缓存一致性
公开(公告)号：US6115794A
公开(公告)日：2000-09-05
申请号：US839544
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson
发明人： Ravi Kumar Arimilli , John Steven Dodson
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0811
摘要： A method and system of providing a pseudo-precise inclusivity scheme in a sectored cache memory for maintaining cache coherency within a data-processing system is disclosed. In accordance with the method and system of the present invention, a cache memory includes a multiple of cache lines. The data field of the cache lines is divided into multiple sectors. A state-bit field is associated with each of the cache lines, and the state-bit field is utilized to identify at least four different states of the corresponding cache line. An inclusive-bit field is associated with each of the sectors within each cache lines, and the inclusive-bit field is utilized to identify an inclusivity state of an associated sector. A first of the four states is assigned to provide precise inclusivity states of an associated cache line. A second and a third of the four states is assigned to provide an imprecise inclusivity state of an associated cache line for improving cache line state decoding efficiency.
摘要翻译：公开了一种在扇区缓存存储器中提供伪精确包含方案以在数据处理系统内维持高速缓存一致性的方法和系统。根据本发明的方法和系统，高速缓冲存储器包括多个高速缓存行。高速缓存线的数据字段被分成多个扇区。状态位字段与每个高速缓存行相关联，并且状态位字段用于标识对应高速缓存行的至少四个不同状态。包含位字段与每个高速缓存行中的每个扇区相关联，并且包含位字段用于识别相关扇区的包含状态。分配四个状态中的第一个以提供相关联的高速缓存行的精确包含状态。分配四个状态中的第二和第三个状态来提供相关联的高速缓存行的不精确包容状态，以提高高速缓存行状态解码效率。

118. 发明授权

US06112270A Method and system for high speed transferring of strictly ordered bus operations by reissuing bus operations in a multiprocessor system 失效
标题翻译：通过在多处理器系统中重新发布总线操作，高速传输严格有序的总线操作的方法和系统
公开(公告)号：US06112270A
公开(公告)日：2000-08-29
申请号：US833227
申请日：1997-10-31
申请人： Jerry Don Lewis , John Steven Dodson , Ravi Kumar Arimilli
发明人： Jerry Don Lewis , John Steven Dodson , Ravi Kumar Arimilli
IPC分类号： G06F13/36 , G06F13/00
CPC分类号： G06F13/36
摘要： A system and method for high speed transferring of bus operations which are preferably strictly ordered in a processing system is provided. A system and method in accordance with the present invention comprises issuing a plurality of bus operation requests by a processor and determining if a first response has been received by the same processor indicating that one of the plurality of bus operation requests should be reissued. Then, if the first response is received, the processor provides a second response indicating that at least another of the issued bus operation requests should be reissued.
摘要翻译：提供了优选地在处理系统中严格排序的总线操作的高速传输的系统和方法。根据本发明的系统和方法包括：由处理器发出多个总线操作请求，并确定是否已经由同一个处理器接收到指示应该重新发出多个总线操作请求之一的第一响应。然后，如果接收到第一响应，则处理器提供第二响应，指示应该重发发出的总线操作请求中的至少另一个。

119. 发明授权

US6105112A Dynamic folding of cache operations for multiple coherency-size systems 失效
标题翻译：用于多个一致性大小系统的缓存操作的动态折叠
公开(公告)号：US6105112A
公开(公告)日：2000-08-15
申请号：US834120
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
IPC分类号： G06F9/30 , G06F12/08 , G06F12/00
CPC分类号： G06F9/30047 , G06F12/0831
摘要： A method is disclosed of managing architectural operations in a computer system whose architecture includes components having varying coherency granule sizes. A queue is provided for receiving as entries a plurality of the architectural operations, the entries of the queue are compared with a new architectural operation to determine if the new architectural operation is redundant with any of the entries. If the new architectural operation is not redundant with any of the entries, it is loaded in the queue. The computer system may include a cache having a processor granularity size and a system bus granularity size which is larger than the processor granularity size, and the architectural operations are cache instructions. The comparison may be performed in an associative manner based on the varying coherency granule sizes.
摘要翻译：公开了一种在计算机系统中管理架构操作的方法，该系统的架构包括具有变化的一致性粒度大小的组件。提供了用于作为条目接收多个架构操作的队列，将队列的条目与新的架构操作进行比较，以确定新的架构操作是否与任何条目冗余。如果新架构操作对于任何条目都不是冗余的，则它将被加载到队列中。计算机系统可以包括具有处理器粒度大小和大于处理器粒度大小的系统总线粒度大小的高速缓存，并且架构操作是高速缓存指令。可以基于变化的一致性粒度大小的关联方式来进行比较。

120. 发明授权

US6078991A Method and system for speculatively requesting system data bus for sourcing cache memory data within a multiprocessor data-processing system 失效
标题翻译：用于在多处理器数据处理系统中推测性请求系统数据总线用于采购缓存存储器数据的方法和系统
公开(公告)号：US6078991A
公开(公告)日：2000-06-20
申请号：US839555
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： A method and system for speculatively sourcing cache memory data within a multiprocessor data-processing system is disclosed. In accordance with the method and system of the present invention, the data-processing system has multiple processing units, each of the processing units including at least one cache memory. In response to a request for data by a first processing unit within the data-processing system, an intervention response is issued from a second processing unit within the data-processing system that contains the requested data. A system bus is then requested for sourcing the requested data from a cache memory within the second processing unit before a combined response from all the processing units returns to the second processing unit.
摘要翻译：公开了一种用于在多处理器数据处理系统内推测地采购缓存存储器数据的方法和系统。根据本发明的方法和系统，数据处理系统具有多个处理单元，每个处理单元包括至少一个高速缓冲存储器。响应于数据处理系统内的第一处理单元对数据的请求，从包含所请求数据的数据处理系统内的第二处理单元发出干预响应。然后，在来自所有处理单元的组合响应返回到第二处理单元之前，系统总线被要求从第二处理单元内的高速缓存存储器中提取所请求的数据。

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