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111. 发明授权

US08122275B2 Write-leveling implementation in programmable logic devices 有权
标题翻译：在可编程逻辑器件中编写调平实现
公开(公告)号：US08122275B2
公开(公告)日：2012-02-21
申请号：US11843123
申请日：2007-08-22
申请人： Yan Chong , Bonnie I. Wang , Chiakang Sung , Joseph Huang , Michael H. M. Chu
发明人： Yan Chong , Bonnie I. Wang , Chiakang Sung , Joseph Huang , Michael H. M. Chu
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/222
摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.
摘要翻译：用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。在一个示例性校准例程中，向接收设备提供时钟信号。还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。

112. 发明授权

US06946872B1 Multiple data rate interface architecture 失效
标题翻译：多数据速率接口架构
公开(公告)号：US06946872B1
公开(公告)日：2005-09-20
申请号：US10623394
申请日：2003-07-18
申请人： Philip Pan , Chiakang Sung , Joseph Huang , Yan Chong , Bonnie I. Wang
发明人： Philip Pan , Chiakang Sung , Joseph Huang , Yan Chong , Bonnie I. Wang
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/1774 , H03K19/17744
摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.
摘要翻译：用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。模块化架构便于引脚从一代PLD迁移到下一代。

113. 发明授权

US06271729B1 Phase-locked loop or delay-locked loop circuitry for programmable logic devices 有权
公开(公告)号：US06271729B1
公开(公告)日：2001-08-07
申请号：US09736065
申请日：2000-12-13
申请人： Chiakang Sung , Joseph Huang , Bonnie I. Wang , Robert R. N. Bielby
发明人： Chiakang Sung , Joseph Huang , Bonnie I. Wang , Robert R. N. Bielby
IPC分类号： H03L706
摘要： A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.

114. 发明授权

US06177844B1 Phase-locked loop or delay-locked loop circuitry for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的锁相环或延迟锁定环电路
公开(公告)号：US06177844B1
公开(公告)日：2001-01-23
申请号：US09393036
申请日：1999-09-09
申请人： Chiakang Sung , Joseph Huang , Bonnie I. Wang , Robert R. N. Bielby
发明人： Chiakang Sung , Joseph Huang , Bonnie I. Wang , Robert R. N. Bielby
IPC分类号： H03L706
CPC分类号： G06F1/10 , H03L7/0812 , H03L7/0996 , H03L7/0997
摘要： A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides aL substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.
摘要翻译：可编程逻辑器件提供有锁相环（“PLL”）或延迟锁定环（“DLL”）电路，其中反馈回路电路在接收的设备上基本平行并复制时钟信号分配网络的一部分主PLL / DLL输出信号。以这种方式，分布式反馈回路电路更容易地提供对通过PLL / DLL电路服务的时钟信号分配网络传播的信号所经历的分布延迟的基本精确匹配。

115. 再颁专利

USRE38651E1 Variable depth and width memory device 失效
标题翻译：可变深度和宽度的存储设备
公开(公告)号：USRE38651E1
公开(公告)日：2004-11-09
申请号：US09096917
申请日：1998-06-12
申请人： Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff , L. Todd Cope , Cameron R. McClintock , William Leong , James A. Watson , Bahram Ahanin
发明人： Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff , L. Todd Cope , Cameron R. McClintock , William Leong , James A. Watson , Bahram Ahanin
IPC分类号： G06F1200
CPC分类号： G11C8/12 , G01R31/318516
摘要： A programmable variable depth and width random-access memory circuit is provided. The memory circuit contains rows and columns of memory cells for storing data. A row decoder is used to address individual rows of the memory cells. Column address circuitry receives a column address signal and a width and depth selection signal. A column decoder within the column address circuitry addresses one or more columns of memory cells of the RAM array based on the selected width of the array. The output of the column decoder is routed to the appropriate column or columns of memory cells by a pattern of fixed connections and a group of programmable multiplexers. The number of data output lines to which data signals are provided is determined by the selected width of the RAM array. The output circuitry contains a group of programmable demultiplexers and a routing array having a pattern of fixed connections suitable for passing data signals from the RAM array to the selected number of data output lines.

116. 发明授权

US5828229A Programmable logic array integrated circuits 失效
标题翻译：可编程逻辑阵列集成电路
公开(公告)号：US5828229A
公开(公告)日：1998-10-27
申请号：US847004
申请日：1997-05-01
申请人： Richard G. Cliff , L. Todd Cope , Cameron McClintock , William Leong , James Allen Watson , Joseph Huang , Bahram Ahanin , Chiakang Sung , Wanli Chang
发明人： Richard G. Cliff , L. Todd Cope , Cameron McClintock , William Leong , James Allen Watson , Joseph Huang , Bahram Ahanin , Chiakang Sung , Wanli Chang
IPC分类号： G01R31/3185 , G11C8/12 , G11C8/16 , G11C29/32 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , G11C29/32 , G11C8/12 , G11C8/16 , H03K19/17704 , H03K19/17728 , H03K19/1776 , H03K19/17764 , G01R31/318516
摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors. A relatively large block of random access memory ("RAM") may be provided on the device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic. The RAM block is connected in the circuitry of the device so that it can be programmed and verified compatibly with other memory on the device. Thereafter the circuitry of the RAM block allows it to be switched over to operation as RAM or ROM during logic operation of the device.
摘要翻译：可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的网络。提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。随机存取存储器（“RAM”）相对较大的块可以在设备的操作期间被提供在设备上用作只读存储器（“ROM”）或RAM，以执行逻辑。 RAM块连接在设备的电路中，使其可以与设备上的其他存储器进行编程和验证。此后，RAM块的电路允许在设备的逻辑运行期间将其切换到作为RAM或ROM的操作。

117. 发明授权

US5633830A Random access memory block circuitry for programmable logic array integrated circuit devices 失效
标题翻译：用于可编程逻辑阵列集成电路器件的随机存取存储器块电路
公开(公告)号：US5633830A
公开(公告)日：1997-05-27
申请号：US555106
申请日：1995-11-08
申请人： Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff
发明人： Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff
IPC分类号： G01R31/3185 , G11C8/12 , G11C8/16 , G11C29/32 , H03K19/173 , H03K19/177 , G11C7/00
CPC分类号： H03K19/1737 , G11C29/32 , G11C8/12 , G11C8/16 , H03K19/17704 , H03K19/17728 , H03K19/1776 , H03K19/17764 , G01R31/318516
摘要： A relatively large block of random access memory ("RAM") may be provided on a programmable logic array integrated circuit device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic. The RAM block is connected in the circuitry of the device so that it can be programmed and verified compatibly with other memory on the device. Thereafter the circuitry of the RAM block allows it to be switched over to operation as RAM or ROM during logic operation of the device.
摘要翻译：可以在可编程逻辑阵列集成电路装置上提供相对较大的随机存取存储器块（“RAM”），用于在设备操作期间用作只读存储器（“ROM”）或RAM以执行逻辑。 RAM块连接在设备的电路中，使其可以与设备上的其他存储器进行编程和验证。此后，RAM块的电路允许在设备的逻辑运行期间将其切换到作为RAM或ROM的操作。

118. 发明授权

US6128692A Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices 失效
标题翻译：可编程逻辑阵列集成电路器件中随机存取存储器块的编程和验证地址生成
公开(公告)号：US6128692A
公开(公告)日：2000-10-03
申请号：US96251
申请日：1998-06-11
申请人： Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff , L. Todd Cope , William Leong, deceased , by Louis Leong, legal representative
发明人： Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff , L. Todd Cope , William Leong, deceased , by Louis Leong, legal representative
IPC分类号： G11C8/04 , G11C8/12 , H03K19/177 , G06F12/02
CPC分类号： G11C8/04 , G11C8/12 , H03K19/17704 , H03K19/1776 , H03K19/17764
摘要： A programmable logic array integrated circuit device has a relatively large block of programmable memory cells in addition to the usual programmable logic modules and the usual programmable interconnection conductor network. In order to simplify the circuitry associated with the large block, and especially the circuitry for addressing that block during programming and/or verification of the device, the address decoder that is normally used to address the block during use of the device to perform logic is also used during programming and/or verification. During programming and/or verification a counter or other similar coded address signal generating circuitry is used to supply address information to the decoder.
摘要翻译：可编程逻辑阵列集成电路器件除了通常的可编程逻辑模块和通常的可编程互连导体网络之外，还具有相对较大的可编程存储单元块。为了简化与大块相关联的电路，特别是用于在设备的编程和/或验证期间寻址该块的电路，在使用设备执行逻辑期间通常用于寻址块的地址解码器是也在编程和/或验证期间使用。在编程和/或验证期间，使用计数器或其它类似的编码地址信号产生电路来向解码器提供地址信息。

119. 发明申请

US20060220703A1 Programmable high speed interface 有权
标题翻译：可编程高速接口
公开(公告)号：US20060220703A1
公开(公告)日：2006-10-05
申请号：US11446483
申请日：2006-06-02
申请人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： H03B1/00
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

120. 发明申请

US20050134332A1 Programmable high speed I/O interface 有权
标题翻译：可编程高速I / O接口
公开(公告)号：US20050134332A1
公开(公告)日：2005-06-23
申请号：US10886015
申请日：2004-07-06
申请人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： G06F3/00 , G06F13/38 , H03K19/0175 , H03K19/173 , H03K19/177 , H03K17/16
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

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