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111. 发明申请

US20090146850A1 TRANSMITTING/RECEIVING METHODS AND SYSTEMS FOR DC BALANCE ENCODED DATA INCLUDING SIMULTANEOUS SWITCHING NOISE REDUCING PREAMBLES 有权
标题翻译：用于直流平衡编码数据的发送/接收方法和系统，包括同时开关噪声减少前提
公开(公告)号：US20090146850A1
公开(公告)日：2009-06-11
申请号：US12367134
申请日：2009-02-06
申请人： Seung-Jun Bae , Seong-Jin Jang
发明人： Seung-Jun Bae , Seong-Jin Jang
IPC分类号： H03M5/00
CPC分类号： H03M5/145
摘要： DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.
摘要翻译：通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

112. 发明授权

US07542372B2 Circuit and methods for eliminating skew between signals in semiconductor integrated circuit 有权
标题翻译：消除半导体集成电路中信号之间的偏差的电路和方法
公开(公告)号：US07542372B2
公开(公告)日：2009-06-02
申请号：US11770766
申请日：2007-06-29
申请人： Seung-Jun Bae , Kwang-Il Park , Seong-Jin Jang
发明人： Seung-Jun Bae , Kwang-Il Park , Seong-Jin Jang
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C5/063 , G11C7/02 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/222
摘要： A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.
摘要翻译：一种用于消除半导体存储器件和存储器控制器之间的接口中的数据与时钟信号之间的偏斜的电路，包括存储从半导体存储器件输出的边沿信息的边缘信息存储单元，伪数据模式生成单元，其输出伪数据，包括与实际发送的数据类似的模式;相位检测单元，其从边缘信息存储单元接收边缘信息，并从伪数据模式产生单元接收伪数据，以检测数据和时钟信号之间的相位差，并产生相应的检测结果，以及相位控制单元，其根据来自相位检测单元的相应检测结果控制时钟信号的相位，以便消除数据写入和读取操作中的每数据输入/输出引脚偏移的半导体存储器件。

113. 发明授权

US07391634B2 Semiconductor memory devices having controllable input/output bit architectures 有权
标题翻译：具有可控输入/输出位体系结构的半导体存储器件
公开(公告)号：US07391634B2
公开(公告)日：2008-06-24
申请号：US11358798
申请日：2006-02-21
申请人： Sung-Hoon Kim , Seong-Jin Jang , Su-Jin Park
发明人： Sung-Hoon Kim , Seong-Jin Jang , Su-Jin Park
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C7/22
摘要： A semiconductor memory device may include a semiconductor substrate, a first unit memory device on the substrate, and a second unit memory device on the substrate. The first unit memory device may be configured to receive first through Nth data bits and/or to provide first through Nth data bits to an external device in response to a command signal, an address signal, and a clock signal, and in response to a first chip selection signal. The second unit memory device may be configured to receive (N+1)th through 2Nth data bits and/or to provide (N+1)th through 2Nth data bits to an external device in response to the command signal, the address signal, and the clock signal, and in response to a second chip selection signal. Related methods are also discussed.
摘要翻译：半导体存储器件可以包括半导体衬底，衬底上的第一单元存储器件和衬底上的第二单元存储器件。第一单元存储器件可以被配置为响应于命令接收第一至第N个/或以上数据位和/或向外部设备提供第一至第N个/ 信号，地址信号和时钟信号，以及响应于第一芯片选择信号。第二单元存储器件可以被配置为通过2N个第（N）个数据位接收（N + 1）个第个和/或提供（N + 1）响应于命令信号，地址信号和时钟信号，以及响应于第二芯片选择信号，向外部设备提供/ SUP>至2N第数据位。还讨论了相关方法。

114. 发明授权

US07388417B2 Output circuit of a semiconductor memory device and method of outputting data in a semiconductor memory device 有权
标题翻译：半导体存储器件的输出电路和在半导体存储器件中输出数据的方法
公开(公告)号：US07388417B2
公开(公告)日：2008-06-17
申请号：US11519252
申请日：2006-09-12
申请人： Kyoung-Ho Kim , Seong-Jin Jang , Joung-Yeal Kim
发明人： Kyoung-Ho Kim , Seong-Jin Jang , Joung-Yeal Kim
IPC分类号： H03K17/62
CPC分类号： G11C7/1039 , G11C7/1051 , G11C7/106 , H03K3/356156
摘要： An output circuit of a semiconductor memory device includes a first data path, a second data path and a third data path. The first data path transfers a sense output signal, and latches the sense output signal to output the sense output signal to a first node. The second data path transfers the sense output signal, and latches the sense output signal to output the sense output signal to the first node. The third data path latches a signal of the first node, and transfers the signal of the first node to generate output data. Accordingly, the semiconductor memory device including the output circuit can operate at a relatively higher frequency using a pseudo-pipeline structured circuit, which combines a wave pipeline structure with a full pipeline structure.
摘要翻译：半导体存储器件的输出电路包括第一数据路径，第二数据路径和第三数据路径。第一数据路径传送感测输出信号，并锁存感测输出信号以将感测输出信号输出到第一节点。第二数据路径传送感测输出信号，并锁存感测输出信号以将感测输出信号输出到第一节点。第三数据路径锁存第一节点的信号，并传送第一节点的信号以产生输出数据。因此，包括输出电路的半导体存储器件可以使用将波形管线结构与完整管线结构组合在一起的伪流水线结构化电路以相对较高的频率工作。

115. 发明授权

US07362648B2 Memory system, memory device, and output data strobe signal generating method 有权
公开(公告)号：US07362648B2
公开(公告)日：2008-04-22
申请号：US11251787
申请日：2005-10-18
申请人： Kwang-Il Park , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-Il Park , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C8/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.

116. 发明申请

US20070290902A1 Semiconductor devices, a system including semiconductor devices and methods thereof 有权
标题翻译：半导体器件，包括半导体器件的系统及其方法
公开(公告)号：US20070290902A1
公开(公告)日：2007-12-20
申请号：US11802886
申请日：2007-05-25
申请人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Woo-Jin Lee
发明人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Woo-Jin Lee
IPC分类号： H03M9/00
CPC分类号： H03K19/00346 , H04L25/03866 , H04L25/14 , H04L25/4908
摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.
摘要翻译：提供半导体器件，包括所述半导体器件的系统及其方法。半导体器件的示例可以接收被调度用于发送的数据，对接收到的数据内的比特数进行加扰，按照给定的伪随机序列排列的加扰顺序。所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。然后可以发送平衡和加扰的接收数据。示例半导体器件可以以任何顺序执行加扰和平衡操作。类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。

117. 发明申请

US20070285121A1 Reference voltage generators for reducing and/or eliminating termination mismatch 有权
标题翻译：用于减少和/或消除终止失配的参考电压发生器
公开(公告)号：US20070285121A1
公开(公告)日：2007-12-13
申请号：US11790014
申请日：2007-04-23
申请人： Kwang-II Park , Seung-Jun Bae , Seong-Jin Jang
发明人： Kwang-II Park , Seung-Jun Bae , Seong-Jin Jang
IPC分类号： H03K19/003
CPC分类号： H03K19/017545
摘要： A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.
摘要翻译：一种包括多个传输线的系统，向多个传输线中的每一个输出相应信号的发射机，经由各个传输线接收多个信号中的每一个的接收机，所述接收机包括连接到终端电压的连接路径，多个终端电路沿着连接路径分布，每个终端电路从连接路径接收唯一的终端电压，接收相应的信号并输出终止的输入信号;参考电压发生器，包括连接到公共电压的多个参考电压发生器单元，每个参考电压发生器单元独特地接收至少一个唯一的终端电压并输出参考电压，以及多个数据输入缓冲器，其接收相应的信号和从参考电压发生器输出的多个参考电压的适当参考电压。

118. 发明授权

US07280412B2 Circuits and methods for data bus inversion in a semiconductor memory 有权
公开(公告)号：US07280412B2
公开(公告)日：2007-10-09
申请号：US11369341
申请日：2006-03-07
申请人： Seong-Jin Jang , Jeong-Don Lim
发明人： Seong-Jin Jang , Jeong-Don Lim
IPC分类号： G11C7/06
CPC分类号： G11C7/1006 , G06F7/501 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C2207/108
摘要： A data bus inversion (DBI) circuit includes at least one DBI block configured to invert an input data signal based on the logic state of input data bits. The DBI block includes a comparison deciding unit configured to generate, in a first mode, a comparison signal based on the number of changed bits by comparing respective bit signals of the input data signal and a previous input data signal. The comparison deciding unit generates an inversion control signal which controls whether the input data will be inverted or not. In a second mode, the comparison deciding unit generates an inversion control signal based on the predominant logic state of the input data signal bits. A data converting unit is configured to invert the input data signal in response to the inversion control signal. Method embodiments are also disclosed.

119. 发明申请

US20070121397A1 Output circuit, semiconductor memory device having the same, and method of expanding a valid output data window 有权
标题翻译：输出电路，具有相同的半导体存储器件以及扩展有效输出数据窗口的方法
公开(公告)号：US20070121397A1
公开(公告)日：2007-05-31
申请号：US11601027
申请日：2006-11-17
申请人： Woo-Jin Lee , Hyun-Dong Kim , Seong-Jin Jang
发明人： Woo-Jin Lee , Hyun-Dong Kim , Seong-Jin Jang
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C7/1051 , G11C7/1069 , G11C29/1201 , G11C29/12015 , G11C29/14
摘要： A semiconductor memory device and a method of expanding a valid output data window are described. The semiconductor memory device includes a memory cell array and an output circuit. The memory cell array generates read data having a plurality of bits. The output circuit outputs the, read data sequentially in response to a clock signal in a normal mode. On the other hand, the output circuit selectively outputs the bits of the read data by latching bits to be tested among bits of the read data, and by electrically disconnecting bits not to be tested among bits of the read data in response to a plurality of switch control signals in a test mode. Therefore a valid data window of an output data may be expanded.
摘要翻译：描述半导体存储器件和扩展有效输出数据窗口的方法。半导体存储器件包括存储单元阵列和输出电路。存储单元阵列产生具有多个位的读取数据。输出电路响应于正常模式下的时钟信号顺序地输出读取数据。另一方面，输出电路通过在读取数据的比特之间锁存待测试的比特来选择性地输出读取的数据的比特，并且响应于多个读取数据，通过电连接在读取的数据的比特之间的不被测试的比特在测试模式下切换控制信号。因此，可以扩展输出数据的有效数据窗口。

120. 发明申请

US20070115733A1 Circuits and methods for data bus inversion in a semiconductor memory 有权
标题翻译：半导体存储器中数据总线反转的电路和方法
公开(公告)号：US20070115733A1
公开(公告)日：2007-05-24
申请号：US11369341
申请日：2006-03-07
申请人： Seong-Jin Jang , Jeong-Don Lim
发明人： Seong-Jin Jang , Jeong-Don Lim
IPC分类号： G11C7/06
CPC分类号： G11C7/1006 , G06F7/501 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C2207/108
摘要： A data bus inversion (DBI) circuit includes at least one DBI block configured to invert an input data signal based on the logic state of input data bits. The DBI block includes a comparison deciding unit configured to generate, in a first mode, a comparison signal based on the number of changed bits by comparing respective bit signals of the input data signal and a previous input data signal. The comparison deciding unit generates an inversion control signal which controls whether the input data will be inverted or not. In a second mode, the comparison deciding unit generates an inversion control signal based on the predominant logic state of the input data signal bits. A data converting unit is configured to invert the input data signal in response to the inversion control signal. Method embodiments are also disclosed.
摘要翻译：数据总线反转（DBI）电路包括至少一个DBI块，其被配置为基于输入数据位的逻辑状态反转输入数据信号。 DBI块包括比较判定单元，该比较判定单元被配置为通过比较输入数据信号和先前输入数据信号的各个比特信号，在第一模式中，基于改变的比特数来生成比较信号。比较判定单元生成控制输入数据是否反转的反转控制信号。在第二模式中，比较判定单元根据输入数据信号位的主要逻辑状态生成反转控制信号。数据转换单元被配置为响应于反转控制信号来反转输入数据信号。还公开了方法实施例。

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