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111. 发明授权

US06836421B2 Line drivers that fit within a specified line pitch 有权
标题翻译：适合指定线路间距的线路驱动器
公开(公告)号：US06836421B2
公开(公告)日：2004-12-28
申请号：US10613099
申请日：2003-07-01
申请人： Darrell Rinerson , Christophe J. Chevallier
发明人： Darrell Rinerson , Christophe J. Chevallier
IPC分类号： G11C502
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , G11C2213/77
摘要： Line drivers that fit within a specified line pitch. One method of placing line drivers completely underneath a cross point array requires splitting the line driver up so that a portion of the line drivers is on a first side of the cross point array and the other portion is on the opposite side. However, using this technique requires that the width of the drivers is no larger than the width of the memory cells that are being driven. This can be accomplished by stacking transistors such that line drivers fit within a specified line pitch, but are as long as is necessary to include all the necessary circuit.
摘要翻译：适合指定线路间距的线路驱动器。将线驱动器完全放置在交叉点阵列下方的一种方法需要将线驱动器向上分开，使得线驱动器的一部分位于交叉点阵列的第一侧，而另一部分在相对侧。然而，使用这种技术要求驱动器的宽度不大于被驱动的存储单元的宽度。这可以通过堆叠晶体管来实现，使得线路驱动器配合在指定的线间距内，但是必须包括所有必要的电路。

112. 发明申请

US20120292585A1 CONTINUOUS PLANE OF THIN-FILM MATERIALS FOR A TWO-TERMINAL CROSS-POINT MEMORY 审中-公开
标题翻译：连续两面终端薄膜材料的薄膜材料
公开(公告)号：US20120292585A1
公开(公告)日：2012-11-22
申请号：US13566584
申请日：2012-08-03
申请人： Robin Cheung , Darrell Rinerson , Travis Byonghyop Oh , Jon Bornstein , David Hansen
发明人： Robin Cheung , Darrell Rinerson , Travis Byonghyop Oh , Jon Bornstein , David Hansen
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L27/101 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1641 , H01L45/165
摘要： A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.
摘要翻译：公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。存储器件可以可选地包括与存储元件和第一和第二包层导体串联电的非欧姆器件。为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。包层导体可以包括由铜制成的芯材料。

113. 发明授权

US08237142B2 Continuous plane of thin-film materials for a two-terminal cross-point memory 有权
标题翻译：用于两端交叉点存储器的薄膜材料的连续平面
公开(公告)号：US08237142B2
公开(公告)日：2012-08-07
申请号：US12932642
申请日：2011-03-01
申请人： Robin Cheung , Jonathan Bornstein , David Hansen , Travis Byonghyop Oh , Darrell Rinerson
发明人： Robin Cheung , Jonathan Bornstein , David Hansen , Travis Byonghyop Oh , Darrell Rinerson
IPC分类号： H01L29/02 , H01L29/06
CPC分类号： H01L27/101 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1641 , H01L45/165
摘要： A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.
摘要翻译：公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。存储器件可以可选地包括与存储元件和第一和第二包层导体串联电的非欧姆器件。为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。包层导体可以包括由铜制成的芯材料。

114. 发明申请

US20100157647A1 Memory access circuits and layout of the same for cross-point memory arrays 审中-公开
标题翻译：存储器访问电路和布局相同的交叉点存储器阵列
公开(公告)号：US20100157647A1
公开(公告)日：2010-06-24
申请号：US12653898
申请日：2009-12-18
申请人： Darrell Rinerson , Christophe J. Chevallier , Chang Hua Siau
发明人： Darrell Rinerson , Christophe J. Chevallier , Chang Hua Siau
IPC分类号： G11C5/02 , H01L27/00 , G11C8/10
CPC分类号： G11C8/10 , G11C5/02 , G11C5/025 , H01L27/0688
摘要： An integrated circuit includes a substrate including active circuitry fabricated on the substrate and a cross-point memory array formed above the substrate. The cross-point memory array can include conductive array lines arranged in different directions, and re-writable memory cells. Further, the integrated circuit can also include a memory access circuit configured to perform data operations on the cross-point memory array. The integrated circuit can include a cross-point memory array interface layer positioned between the substrate and the cross-point array and including conductive paths configured to electrically couple portions of the memory access circuit with a subset of the conductive array lines. At least one layer of cross-point memory arrays can be formed over the substrate. The memory cells can be two-terminal memory cells that store data as a plurality of conductivity profiles (e.g., resistive states) that can be non-destructively determined by applying a read voltage across the terminals.
摘要翻译：集成电路包括：衬底，其包括在衬底上制造的有源电路和形成在衬底上方的交叉点存储器阵列。交叉点存储器阵列可以包括布置在不同方向的导电阵列线以及可重写存储器单元。此外，集成电路还可以包括被配置为在交叉点存储器阵列上执行数据操作的存储器访问电路。集成电路可以包括位于衬底和交叉点阵列之间的交叉点存储器阵列接口层，并且包括被配置为将存储器访问电路的一部分与导电阵列线的子集电耦合的导电路径。可以在衬底上形成至少一层交叉点存储器阵列。存储器单元可以是将数据存储为可以通过跨终端施加读取电压而非破坏性地确定的多个电导率分布（例如电阻状态）的两端存储单元。

115. 发明授权

US07505347B2 Method for sensing a signal in a two-terminal memory array having leakage current 有权
标题翻译：用于感测具有漏电流的双端存储器阵列中的信号的方法
公开(公告)号：US07505347B2
公开(公告)日：2009-03-17
申请号：US12072813
申请日：2008-02-28
申请人： Darrell Rinerson , Christophe J. Chevallier , Chang Hua Siau
发明人： Darrell Rinerson , Christophe J. Chevallier , Chang Hua Siau
IPC分类号： G11C7/02
CPC分类号： G11C11/16 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2013/0057 , G11C2211/5634 , G11C2213/31 , G11C2213/32 , G11C2213/34 , G11C2213/77
摘要： A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.
摘要翻译：双端存储器阵列包括多个第一和第二导电迹线。地址单元可操作地对所选择的第一和第二导电迹线对施加选择电压，并将非选择电压电势施加到未选择的迹线。在所选择的第一导电迹线中流动的总电流和流过未选择的第二导电迹线的漏电流在一个周期或两个周期的预读取操作中由感测单元感测。总和漏电流可以与参考信号组合以导出指示表示存储的数据的多个电导率分布之一的数据信号。电导率分布可以存储在与所选择的第一和第二导电迹线电串联的电阻状态存储元件中。

116. 发明申请

US20090027976A1 Threshold device for a memory array 失效
标题翻译：内存阵列的阈值设备
公开(公告)号：US20090027976A1
公开(公告)日：2009-01-29
申请号：US11881473
申请日：2007-07-26
申请人： Julie Casperson Brewer , Darrell Rinerson , Christophe J. Chevallier , Wayne Kinney , Roy Lambertson , Lawrence Schloss
发明人： Julie Casperson Brewer , Darrell Rinerson , Christophe J. Chevallier , Wayne Kinney , Roy Lambertson , Lawrence Schloss
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/71 , G11C2213/76 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/147
摘要： A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.
摘要翻译：公开了一种阈值装置，其包括彼此接触并且由多种不同介电材料制成的多个相邻隧道势垒层。具有第一和第二端子的存储器插头包括与第一和第二端子串联的阈值装置和存储数据作为多个导电率曲线的存储元件。阈值装置可操作以在数据操作期间根据施加的电压施加限定通过存储元件的电流的特征I-V曲线。阈值装置基本上减少或消除了通过半选择或未选择的存储器插头的电流，并且允许足够大的电流流过被选择用于读取和写入操作的存储器插头。阈值器件减少或消除半选择的存储器插头中的数据干扰，并在读取操作期间增加S / N比。

117. 发明授权

US07400006B1 Conductive memory device with conductive oxide electrodes 有权
标题翻译：具有导电氧化物电极的导电存储器件
公开(公告)号：US07400006B1
公开(公告)日：2008-07-15
申请号：US11405958
申请日：2006-04-18
申请人： Darrell Rinerson , Steve Kuo-Ren Hsia , Wayne Kinney , Steven W. Longcor
发明人： Darrell Rinerson , Steve Kuo-Ren Hsia , Wayne Kinney , Steven W. Longcor
IPC分类号： H01L31/062
CPC分类号： H01L27/2418 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/165
摘要： A multi-resistive state element that uses barrier electrodes is provided. If certain materials are used as electrodes, the electrodes can be used for multiple purposes. Oxides and nitrides are especially well suited for acting as a barrier layer, and possibly even an adhesion layer and a sacrificial layer.
摘要翻译：提供了使用阻挡电极的多电阻状态元件。如果使用某些材料作为电极，电极可用于多种用途。氧化物和氮化物特别适用于作为阻挡层，甚至可能甚至粘附层和牺牲层。

118. 发明授权

US07309616B2 Laser annealing of complex metal oxides (CMO) memory materials for non-volatile memory integrated circuits 失效
标题翻译：用于非易失性存储器集成电路的复合金属氧化物（CMO）记忆材料的激光退火
公开(公告)号：US07309616B2
公开(公告)日：2007-12-18
申请号：US10387799
申请日：2003-03-13
申请人： Makoto Nagashima , Darrell Rinerson , Steve Kuo-Ren Hisa
发明人： Makoto Nagashima , Darrell Rinerson , Steve Kuo-Ren Hisa
IPC分类号： H01L21/00
CPC分类号： H01L21/02356 , C23C14/5813 , H01L21/02175 , H01L21/02197 , H01L21/02354 , H01L21/31604 , H01L21/31691 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1625 , H01L45/1641
摘要： A method is disclosed to effectively achieve a low deposition temperature of CMO memory materials by depositing the CMO memory material at relatively low temperatures that give an amorphous film, then to later melt and re-crystallize the CMO memory material with a laser (laser annealing).
摘要翻译：公开了一种通过在相对较低的温度下沉积CMO记忆材料来有效地实现CMO记忆材料的低沉积温度的方法，然后再用激光（激光退火）熔化并再结晶CMO记忆材料，。

119. 发明授权

US07227775B2 Two terminal memory array having reference cells 有权
标题翻译：具有参考单元的两个终端存储器阵列
公开(公告)号：US07227775B2
公开(公告)日：2007-06-05
申请号：US11478520
申请日：2006-06-29
申请人： Darrell Rinerson , Christophe J. Chevallier , Steven W. Longcor
发明人： Darrell Rinerson , Christophe J. Chevallier , Steven W. Longcor
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2213/31 , G11C2213/71 , G11C2213/77
摘要： A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.
摘要翻译：提供包括参考单元的存储器。存储器具有地址解码电路和非易失性和可重写的存储器单元阵列。每个存储单元具有能够经历电阻变化的两端存储器插头。感应电路将激活的存储单元与参考电平进行比较。参考电平通常由可以在选择存储器单元的同时被选择的至少一个参考单元产生。

120. 发明授权

US07075817B2 Two terminal memory array having reference cells 失效
标题翻译：具有参考单元的两个终端存储器阵列
公开(公告)号：US07075817B2
公开(公告)日：2006-07-11
申请号：US10895218
申请日：2004-07-20
申请人： Darrell Rinerson , Christophe J. Chevallier , Steven W. Longcor
发明人： Darrell Rinerson , Christophe J. Chevallier , Steven W. Longcor
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2213/31 , G11C2213/71 , G11C2213/77
摘要： A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.
摘要翻译：提供包括参考单元的存储器。存储器具有地址解码电路和非易失性和可重写的存储器单元阵列。每个存储单元具有能够经历电阻变化的两端存储器插头。感应电路将激活的存储单元与参考电平进行比较。参考电平通常由可以在选择存储器单元的同时被选择的至少一个参考单元产生。

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