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111. 发明授权

US06681311B2 Translation lookaside buffer that caches memory type information 有权
标题翻译：缓存内存类型信息的翻译后备缓冲区
公开(公告)号：US06681311B2
公开(公告)日：2004-01-20
申请号：US09908909
申请日：2001-07-18
申请人： Darius D. Gaskins , G. Glenn Henry , Rodney E. Hooker
发明人： Darius D. Gaskins , G. Glenn Henry , Rodney E. Hooker
IPC分类号： G06F1200
CPC分类号： G06F12/1027
摘要： A translation lookaside buffer (TLB) that caches memory types of memory address ranges. A data unit includes a TLB which, in addition to caching page table entries including translated page base addresses of virtual page numbers as in a conventional TLB, also caches memory address range memory types provided by a memory type unit (MTU). In the case of a hit of a virtual address in the TLB, the TLB provides the memory type along with the page table entry, thereby avoiding the need for a serialized accessed to the MTU using the physical address output by the TLB. Logic which controls a processor bus access necessitated by the virtual address makes use of the memory type output by the TLB sooner than would be available from the MTU in conventional data units. If the MTU is updated, the TLB is flushed to insure consistency of memory type values.
摘要翻译：翻译后备缓冲区（TLB），缓存内存地址范围的内存类型。数据单元包括TLB，除了如在常规TLB中缓存包括虚拟页号的翻译页基地址的页表项之外，还缓存由存储器类型单元（MTU）提供的存储器地址范围存储器类型。在TLB中命中虚拟地址的情况下，TLB与页表项一起提供存储器类型，从而避免了使用TLB输出的物理地址对MTU的序列化访问的需要。控制由虚拟地址所必需的处理器总线访问的逻辑利用了比常规数据单元中MTU可用的存储器类型更早地由TLB输出的存储器类型。如果MTU更新，则刷新TLB以确保内存类型值的一致性。

112. 发明授权

US06675287B1 Method and apparatus for store forwarding using a response buffer data path in a write-allocate-configurable microprocessor 有权
标题翻译：用于在写入分配可配置的微处理器中使用响应缓冲器数据路径的存储转发的方法和装置
公开(公告)号：US06675287B1
公开(公告)日：2004-01-06
申请号：US09545026
申请日：2000-04-07
申请人： Darius D. Gaskins , G. Glenn Henry , Rodney E. Hooker
发明人： Darius D. Gaskins , G. Glenn Henry , Rodney E. Hooker
IPC分类号： G06F938
CPC分类号： G06F9/3834 , G06F9/3826
摘要： An apparatus for forwarding storehit data within a pipelined microprocessor is provided. The apparatus has a plurality of response buffers that receive data from a bus that couples a system memory to the microprocessor and multiplexing and forwarding logic. When a store instruction generates a miss of the microprocessor's instruction cache, the store results are written not only to store buffers for updating the cache, but also to one of the response buffers. The missing cache line implicated by the store miss is requested from the system memory, received into the response buffer, and merged with the store results. The cache is updated with the merged data. However, in addition, storehit conditions with the store results generated by load instructions coming down the pipeline are satisfied from the response buffer. The multiplexing and forwarding logic is capable of forwarding the store results from the response buffer to the pipeline both before and after the missing cache line is received.
摘要翻译：提供了一种用于在流水线微处理器内转发存储数据的装置。该装置具有多个响应缓冲器，其从总线接收数据，该总线将系统存储器耦合到微处理器以及复用和转发逻辑。当存储指令产生微处理器的指令高速缓存的未命中时，不仅将存储结果写入用于更新缓存的缓冲器，而且还写入缓冲器之一。由存储器未命中所涉及的丢失的高速缓存行被从系统存储器请求，被接收到响应缓冲器中，并与存储结果合并。缓存使用合并的数据进行更新。然而，另外，从响应缓冲器中，满足由流水线下载的加载指令产生的存储结果的存储条件。复用和转发逻辑能够在收到缺失的高速缓存行之前和之后将存储结果从响应缓冲器转发到流水线。

113. 发明授权

US06519696B1 Paired register exchange using renaming register map 有权
标题翻译：配对寄存器交换使用重命名寄存器映射
公开(公告)号：US06519696B1
公开(公告)日：2003-02-11
申请号：US09538314
申请日：2000-03-30
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F9302
CPC分类号： G06F9/30032 , G06F9/3017 , G06F9/30181 , G06F9/384 , G06F9/3853
摘要： An apparatus and method are provided for performing a floating point exchange operation in a pipeline microprocessor in zero effective clock cycles. The present invention exploits the pattern of floating point operations common to most floating point software algorithms where floating point exchange operations appear as every other instruction between floating point computational instructions. The apparatus includes translation logic, that pairs the operations directed by a floating point macro instruction and a floating point exchange macro instruction by generating a micro instruction with an exchange extension. The exchange extension directs the microprocessor to perform the floating point exchange operation in parallel with the operation prescribed by the floating point macro instruction within a single floating point unit. The apparatus also has floating point register logic that receives the micro instruction and exchange extension, and which performs the floating point exchange operation in parallel with the operation directed by the micro instruction.
摘要翻译：提供了一种用于在零有效时钟周期中在流水线微处理器中执行浮点交换操作的装置和方法。本发明利用大多数浮点软件算法共同的浮点运算模式，其中浮点交换操作在浮点计算指令之间出现为每隔一个指令。该装置包括翻译逻辑，其通过产生具有交换扩展的微指令来对对由浮点宏指令和浮点交换宏指令引导的操作。交换扩展指示微处理器与单个浮点单元中的浮点宏指令所规定的操作并行执行浮点交换操作。该装置还具有接收微指令和交换扩展的浮点寄存器逻辑，并且与由微指令执行的操作并行执行浮点交换操作。

114. 发明授权

US06499101B1 Static branch prediction mechanism for conditional branch instructions 有权
标题翻译：条件分支指令的静态分支预测机制
公开(公告)号：US06499101B1
公开(公告)日：2002-12-24
申请号：US09272225
申请日：1999-03-18
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F900
CPC分类号： G06F9/3846 , G06F9/3848
摘要： An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus includes a static branch predictor, a prediction correlator, and branch history update logic. If a branch instruction is known to exhibit a bias toward a particular outcome, then the static branch predictor directs the microprocessor, via a precedence signal, to take the particular outcome, regardless of what a dynamic branch prediction for the branch instruction may indicate. Thus, the predicted outcome takes precedence over the dynamic branch prediction for a biased outcome branch instruction. The branch history update logic updates a branch history entry corresponding to a branch instruction following its resolution, unless the precedence signal indicates that a particular outcome for the branch instruction was directed by the static branch predictor. In this case the corresponding branch history entry is not updated.
摘要翻译：提供了一种装置和方法，用于在流水线微处理器执行之前准确预测分支指令的结果。该装置包括静态分支预测器，预测相关器和分支历史更新逻辑。如果已知分支指令对特定结果表现偏见，则静态分支预测器将通过优先信号指导微处理器采取特定结果，而不管分支指令的动态分支预测是什么。因此，预测结果优先于偏向结果分支指令的动态分支预测。分支历史更新逻辑更新与其分辨率之后的分支指令相对应的分支历史条目，除非优先信号指示分支指令的特定结果由静态分支预测器指导。在这种情况下，相应的分支历史记录条目不被更新。

115. 发明授权

US06385716B1 Method and apparatus for tracking coherence of dual floating point and MMX register files 有权
标题翻译：用于跟踪双浮点和MMX寄存器文件的相干性的方法和装置
公开(公告)号：US06385716B1
公开(公告)日：2002-05-07
申请号：US09349441
申请日：1999-07-09
申请人： G. Glenn Henry , Albert J. Loper, Jr.
发明人： G. Glenn Henry , Albert J. Loper, Jr.
IPC分类号： G06F1212
CPC分类号： G06F9/3885 , G06F9/30036 , G06F9/3013 , G06F9/30185
摘要： An apparatus and method for tracking coherence between distinct floating point and MMX register files in a microprocessor is provided. The apparatus keeps track of the last time a floating point or MMX instruction was translated and what the instruction type of that previous instruction was by storing the previous instruction type in a register. When the current instruction is translated, the translator compares the current instruction type with the previous instruction type stored in the register to determine if they are different, i.e., if an instruction boundary (a change from MMX to floating point instruction or vice versa) was encountered. If so, the translator generates a signal to indicate that the two register files may be incoherent and need to be made consistent again.
摘要翻译：提供了一种用于跟踪微处理器中不同浮点和MMX寄存器文件之间的相干性的装置和方法。该装置跟踪上次浮点或MMX指令的翻译以及先前指令的指令类型是通过将先前的指令类型存储在寄存器中。当当前指令被翻译时，转换器将当前指令类型与存储在寄存器中的先前指令类型进行比较，以确定它们是否不同，即如果指令边界（从MMX到浮点指令的改变或反之亦然）遇到如果是这样，则翻译器产生一个信号以指示两个寄存器文件可能是不相干的，并且需要再次保持一致。

116. 发明授权

US06330657B1 Pairing of micro instructions in the instruction queue 有权
标题翻译：在指令队列中配对微指令
公开(公告)号：US06330657B1
公开(公告)日：2001-12-11
申请号：US09313907
申请日：1999-05-18
申请人： Gerard M. Col , G. Glenn Henry
发明人： Gerard M. Col , G. Glenn Henry
IPC分类号： G06F930
CPC分类号： G06F9/3885 , G06F9/28 , G06F9/3017 , G06F9/3853 , G06F9/3887
摘要： An apparatus and method are presented for increasing the throughput within a single-channel of a pipeline microprocessor. Back-to-back pairs of micro instructions are evaluated to determine if they can be combined for execution in parallel. If so, then they are combined and issued for concurrent execution. The apparatus includes a micro instruction queue that buffers and orders micro instructions for sequential execution by the pipeline microprocessor. Within the micro instruction queue, a second micro instruction is ordered to execute immediately following execution of a first micro instruction. Pairing logic is coupled to the micro instruction queue. The pairing logic combines the first and second micro instructions so that the first and second micro instructions are executed in parallel by the pipeline microprocessor.
摘要翻译：提出了一种用于增加流水线微处理器的单通道内的吞吐量的装置和方法。评估微指令的背对背对，以确定它们是否可以并行执行并行。如果是这样，那么它们被组合并发布用于并发执行。该装置包括微指令队列，其缓冲并命令用于由流水线微处理器顺序执行的微指令。在微指令队列中，第二微指令被命令在执行第一微指令之后立即执行。配对逻辑耦合到微指令队列。配对逻辑组合第一和第二微指令，使得第一和第二微指令由流水线微处理器并行执行。

117. 发明授权

US06247122B1 Method and apparatus for performing branch prediction combining static and dynamic branch predictors 有权
标题翻译：用于执行组合静态和动态分支预测器的分支预测的方法和装置
公开(公告)号：US06247122B1
公开(公告)日：2001-06-12
申请号：US09203884
申请日：1998-12-02
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F942
CPC分类号： G06F9/3846 , G06F9/3848
摘要： An apparatus and method for improving microprocessor performance by improving the prediction accuracy of conditional branch instructions is provided. A static branch predictor makes a prediction of the outcome of a conditional branch instruction based on the branch test type and the branch target address displacement sign. A branch history table stores a bit indicating whether the prediction of the static predictor agreed with the outcome of the last execution of the branch instruction. If the history table bit agrees, then the static prediction is used. Otherwise, the opposite of the static prediction is used.
摘要翻译：提供了一种通过提高条件分支指令的预测精度来提高微处理器性能的装置和方法。静态分支预测器基于分支测试类型和分支目标地址位移符号来预测条件分支指令的结果。分支历史表存储指示静态预测符的预测是否与分支指令的最后执行的结果一致的位。如果历史表位同意，则使用静态预测。否则，使用静态预测的相反。

118. 发明授权

US6161188A Microprocessor having fuse control and selection of clock multiplier 有权
标题翻译：微处理器具有熔丝控制和选择时钟倍增器
公开(公告)号：US6161188A
公开(公告)日：2000-12-12
申请号：US193303
申请日：1998-11-17
申请人： Darius D. Gaskins , G. Glenn Henry
发明人： Darius D. Gaskins , G. Glenn Henry
IPC分类号： G06F1/08 , G06F1/04
CPC分类号： G06F1/08
摘要： A microprocessor is provided having selective control features to determine its core-to-bus clock ratio. The microprocessor includes a fuse and buffer/control logic. The fuse, fabricated on the microprocessor's metalization or poly layer, can be blown with a laser during fabrication. When blown, the fuse provides a permanent state that prescribes a fixed core-to-bus clock ratio. The buffer/control logic is coupled to the fuse. The buffer/control logic accepts the permanent state and directs the microprocessor to set the core-to-bus clock ratio to a fix value, thus disabling control of the core-to-bus clock ratio via external clock ratio control signals.
摘要翻译：提供了具有选择性控制特征以确定其核心到总线时钟比的微处理器。微处理器包括熔丝和缓冲器/控制逻辑。在微处理器的金属化或多层制造的保险丝可以在制造过程中用激光吹扫。当熔断器熔断时，保险丝提供一个固定的核心到总线的时钟比例。缓冲器/控制逻辑耦合到保险丝。缓冲器/控制逻辑接受永久状态并指示微处理器将核心到总线的时钟比率设置为固定值，从而通过外部时钟比率控制信号禁止对核心到总线时钟比的控制。

119. 发明授权

US6014736A Apparatus and method for improved floating point exchange 失效
标题翻译：改进浮点交换的装置和方法
公开(公告)号：US6014736A
公开(公告)日：2000-01-11
申请号：US48524
申请日：1998-03-26
申请人： Timothy A. Elliott , G. Glenn Henry , Albert J. Loper, Jr.
发明人： Timothy A. Elliott , G. Glenn Henry , Albert J. Loper, Jr.
IPC分类号： G06F9/315 , G06F9/38
CPC分类号： G06F9/30032 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A microprocessor is provided for executing a floating point exchange micro instruction sequence to swap the contents a first location and a second location. The microprocessor includes register/control logic that receives a floating point micro instruction, determines that the contents of the first location depend upon resolution of a preceding floating point micro instruction, and provides a signal indicating the dependency. The microprocessor also has interlock logic that, in the event of a dependency forwards a new target location to the preceding floating point micro instruction. The microprocessor also includes target location modification logic that receives the new target location and for provides the new target location to the preceding floating point micro instruction. Modification of the target location allows the floating point exchange micro instruction sequence to execute without resolution delay.
摘要翻译：提供微处理器用于执行浮点交换微指令序列以将内容交换第一位置和第二位置。微处理器包括接收浮点微指令的寄存器/控制逻辑，确定第一位置的内容取决于先前浮点微指令的分辨率，并提供指示依赖性的信号。微处理器还具有互锁逻辑，在依赖性的情况下将新的目标位置转发到前一个浮点微指令。微处理器还包括目标位置修改逻辑，其接收新的目标位置，并提供新的目标位置到先前的浮点微指令。目标位置的修改允许浮点交换微指令序列执行无分辨率延迟。

120. 发明授权

US5983344A Combining ALU and memory storage micro instructions by using an address latch to maintain an address calculated by a first micro instruction 失效
标题翻译：通过使用地址锁存器来保持由第一微指令计算的地址来组合ALU和存储器存储微指令
公开(公告)号：US5983344A
公开(公告)日：1999-11-09
申请号：US820576
申请日：1997-03-19
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F9/318 , G06F9/38 , G06F9/28
CPC分类号： G06F9/3017 , G06F9/3824
摘要： An apparatus and method for improving the execution speed of macro instructions which have an operand located in memory, and where the destination of the result is in memory. The apparatus includes an ALU Store which monitors micro instructions generated by a translator. When a macro instruction is fetched which has an operand located in memory, and the result is to be stored in the same location in memory, the translator generates a LOAD micro instruction followed immediately by an operation micro instruction which contains STORE indicia, such as a STORE suffix. The ALU Store latches the address created by the LOAD micro instruction, and uses this latched address in the following operation store micro instruction.
摘要翻译：一种用于提高具有位于存储器中的操作数并且结果的目的地在存储器中的宏指令的执行速度的装置和方法。该装置包括监视由翻译器产生的微指令的ALU存储器。当获取具有位于存储器中的操作数的宏指令，并且将结果存储在存储器中的相同位置时，转换器产生一个LOAD微指令，紧跟着包含STORE标记的操作微指令，例如 STORE后缀。 ALU存储器锁存由LOAD微指令创建的地址，并在以下操作存储器微指令中使用该锁存地址。

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