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111. 发明授权

US06754810B2 Instruction set for bi-directional conversion and transfer of integer and floating point data 有权
标题翻译：用于双向转换和传输整数和浮点数据的指令集
公开(公告)号：US06754810B2
公开(公告)日：2004-06-22
申请号：US10120538
申请日：2002-04-10
申请人： Timothy A. Elliott , G. Glenn Henry
发明人： Timothy A. Elliott , G. Glenn Henry
IPC分类号： G06F9315
CPC分类号： G06F9/30014 , G06F9/30025
摘要： An apparatus and method for bi-directional format conversion and transfer of data between integer and floating point registers is provided. A floating point register is configured to store floating point data, and integer data, in a variety of numerical formats. Data is moved in and out of the floating point register as integer data, and is converted into floating point format as needed. Separate processor instructions are provided for format conversion and data transfer to allow conversion and transfer operations to be separated.
摘要翻译：提供了一种用于在整数和浮点寄存器之间双向格式转换和数据传输的装置和方法。浮点寄存器被配置为以各种数字格式存储浮点数据和整数数据。数据作为整数数据移入和移出浮点寄存器，并根据需要转换为浮点格式。提供单独的处理器指令用于格式转换和数据传输，以允许转换和传输操作分离。

112. 发明授权

US06587929B2 Apparatus and method for performing write-combining in a pipelined microprocessor using tags 有权
标题翻译：在使用标签的流水线微处理器中执行写入组合的装置和方法
公开(公告)号：US06587929B2
公开(公告)日：2003-07-01
申请号：US09920568
申请日：2001-07-31
申请人： G. Glenn Henry , Rodney E. Hooker
发明人： G. Glenn Henry , Rodney E. Hooker
IPC分类号： G06F1200
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3834
摘要： A tag-based write-combining apparatus in a microprocessor. The apparatus includes a register that stores the store address of the last write-combinable store passing through the store stage of the pipeline. Tag allocation logic compares the last store address with the store address of a new store and allocates the same tag as was previously allocated to the last store if the addresses are in the same cache line, and assigns the next incremental tag otherwise. Tag registers store write buffer tags associated with store data in write buffers waiting to be written to memory on the processor bus. When the new store reaches the write buffer stage, tag comparators compare the new store tag with the write buffer store tags. If the tags match, the write buffer control logic combines the new store data with the store data in the write buffer with the matching tag.
摘要翻译：一种基于标签的写入组合装置。该装置包括一个寄存器，该寄存器存储通过流水线存储阶段的最后一个可写入组合存储区的存储地址。标签分配逻辑将最后一个存储地址与新存储的存储地址进行比较，如果地址在同一个高速缓存行中，则分配与之前分配给最后一个存储相同的标签，否则分配下一个增量标签。标签寄存器将与存储数据相关联的写入缓冲器标签存储在等待在处理器总线上写入存储器的写入缓冲器中。当新的存储器到达写入缓冲器级时，标签比较器将新的存储标签与写入缓冲器存储标签进行比较。如果标签匹配，则写入缓冲器控制逻辑将新的存储数据与写入缓冲器中的存储数据与匹配的标签组合。

113. 发明授权

US06550004B1 Hybrid branch predictor with improved selector table update mechanism 有权
标题翻译：具有改进的选择器表更新机制的混合分支预测器
公开(公告)号：US06550004B1
公开(公告)日：2003-04-15
申请号：US09434984
申请日：1999-11-05
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F932
CPC分类号： G06F9/3846 , G06F9/3848
摘要： A branch predictor for improving branch prediction accuracy is provided. The branch predictor includes global and local Agree dynamic branch predictors, one of which is selected for correlation with a static branch prediction made based upon a test type of a conditional branch instruction specifying a condition upon which the branch will be taken. In one embodiment, the selection is made by correlating a selection prediction made the static predictor based on the test type and an Agree prediction made by a selector history table based on the branch instruction address. In an alternate embodiment, the selection is made directly by the selector history table, without the benefit of the static prediction. In addition, the static predictor makes its predictions based upon an opcode of an instruction preceding the conditional branch instruction and upon a sign of a displacement for calculating a target address of the conditional branch instruction. The dynamic predictors are updated if they are selected and incorrectly predicted the outcome. The selector history table is updated if the selected dynamic predictor predicted incorrectly and the non-selected dynamic predictor predicted correctly.
摘要翻译：提供了一种用于提高分支预测精度的分支预测器。分支预测器包括全局和局部同意动态分支预测器，其中之一被选择用于基于指定将要采用分支的条件的条件分支指令的测试类型进行的静态分支预测相关。在一个实施例中，通过使基于测试类型的静态预测器的选择预测与基于分支指令地址的选择器历史表进行的同意预测相关联来进行选择。在替代实施例中，选择历史表直接进行选择，而没有静态预测的好处。此外，静态预测器基于条件分支指令之前的指令的操作码和用于计算条件转移指令的目标地址的位移的符号来进行预测。动态预测器如果被选择并且不正确地预测结果将被更新。如果所选择的动态预测器预测不正确并且未选择的动态预测器正确预测，则选择器历史表被更新。

114. 发明授权

US06546481B1 Split history tables for branch prediction 有权
标题翻译：拆分分支预测的历史表
公开(公告)号：US06546481B1
公开(公告)日：2003-04-08
申请号：US09434096
申请日：1999-11-05
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F938
CPC分类号： G06F9/3806 , G06F9/3844
摘要： An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus includes a bias indicator and a dynamic branch predictor. The bias indicator receives a branch instruction from an instruction buffer and provides an output indicating a particular outcome bias category for the branch instruction. The bias indicator provides the output as a function of a branch type and a displacement, where the branch type and the displacement are prescribed by the branch instruction The dynamic branch predictor is coupled to the bias indicator. The dynamic branch predictor receives the output and predicts an outcome for the branch instruction based upon contents of an entry in a particular branch history table, where the particular branch history table corresponds to the particular outcome bias category, and where the dynamic branch predictor maintains a plurality of branch history tables, each of the plurality of branch history tables corresponding to an outcome bias category, and where the outcome bias category is selected from a plurality of outcome bias categories, and where the plurality of outcome bias categories comprises a taken category and a not taken category.
摘要翻译：提供了一种装置和方法，用于在流水线微处理器执行之前准确预测分支指令的结果。该装置包括偏置指示器和动态分支预测器。偏置指示器从指令缓冲器接收分支指令，并提供指示分支指令的特定结果偏差类别的输出。偏置指示器提供输出作为分支类型和位移的函数，其中分支类型和位移由分支指令规定。动态分支预测器耦合到偏置指示器。动态分支预测器基于特定分支历史表中的条目的内容接收输出并预测分支指令的结果，其中特定分支历史表对应于特定结果偏差类别，并且动态分支预测器维持一个多个分支历史表，多个分支历史表中的每一个对应于结果偏差类别，并且其中结果偏差类别从多个结果偏差类别中选择，并且其中多个结果偏差类别包括取得的类别，以及一个不采取的类别。

115. 发明授权

US06526502B1 Apparatus and method for speculatively updating global branch history with branch prediction prior to resolution of branch outcome 有权
标题翻译：用于在分支结果解决之前用分支预测推测性地更新全局分支历史的装置和方法
公开(公告)号：US06526502B1
公开(公告)日：2003-02-25
申请号：US09690371
申请日：2000-12-16
申请人： Gerard M. Col , G. Glenn Henry , Dinesh K. Jain
发明人： Gerard M. Col , G. Glenn Henry , Dinesh K. Jain
IPC分类号： G06F940
CPC分类号： G06F9/3861 , G06F9/3842 , G06F9/3848
摘要： An apparatus and method for improving microprocessor performance by improving the prediction accuracy of conditional branch instructions is provided. A dynamic branch predictor speculatively updates global branch history information based on the prediction of a first branch instruction so that the predictor can predict the outcome of a second branch instruction following closely in the pipeline with the benefit of the first prediction. This improves the prediction accuracy where the first branch has not been resolved prior to the time when the second prediction is ready to be made. If the first prediction turns out to be incorrect, the global branch history is restored from a previously saved copy and updated with the first branch instruction's actual outcome.
摘要翻译：提供了一种通过提高条件分支指令的预测精度来提高微处理器性能的装置和方法。动态分支预测器基于第一分支指令的预测来推测性地更新全局分支历史信息，使得预测器可以预测第二分支指令的结果，紧随其后的第一预测的益处。这提高了在第二预测准备好之前第一分支尚未被解析的预测精度。如果第一个预测结果不正确，则全局分支历史将从先前保存的副本中恢复，并以第一个分支指令的实际结果进行更新。

116. 发明授权

US06453412B1 Method and apparatus for reissuing paired MMX instructions singly during exception handling 有权
标题翻译：在异常处理期间单独重新发布成对的MMX指令的方法和装置
公开(公告)号：US06453412B1
公开(公告)日：2002-09-17
申请号：US09357703
申请日：1999-07-20
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F948
CPC分类号： G06F9/3853 , G06F9/3861
摘要： In a computer having a single execution pipeline, the invention provides a method for executing paired MMX-type instructions. The method includes executing two MMX-type instructions as paired MMX instructions. If execution of the paired MMX instructions causes an exception, pairing of instructions is disabled, and the two MMX-type instructions are re-executed in sequential fashion. Paired execution is re-enabled following re-execution of the two MMX-type instructions.
摘要翻译：在具有单个执行流水线的计算机中，本发明提供了一种用于执行成对的MMX型指令的方法。该方法包括执行两个MMX类型的指令作为成对的MMX指令。如果配对的MMX指令的执行导致异常，则禁止配对指令，并且以连续的方式重新执行两个MMX型指令。在重新执行两个MMX类型的指令后，重新启用配对执行。

117. 发明授权

US06405306B2 Instruction set for bi-directional conversion and transfer of integer and floating point data 有权
标题翻译：用于双向转换和传输整数和浮点数据的指令集
公开(公告)号：US06405306B2
公开(公告)日：2002-06-11
申请号：US09866078
申请日：2001-05-25
申请人： Timothy A. Elliott , G. Glenn Henry
发明人： Timothy A. Elliott , G. Glenn Henry
IPC分类号： G06F9302
CPC分类号： G06F9/30014 , G06F9/30025
摘要： An apparatus and method for bi-directional format conversion and transfer of data between integer and floating point registers is provided. A floating point register is configured to store floating point data, and integer data, in a variety of numerical formats. Data is moved in and out of the floating point register as integer data, and is converted into floating point format as needed. Separate processor instructions are provided for format conversion and data transfer to allow conversion and transfer operations to be separated.
摘要翻译：提供了一种用于在整数和浮点寄存器之间双向格式转换和数据传输的装置和方法。浮点寄存器被配置为以各种数字格式存储浮点数据和整数数据。数据作为整数数据移入和移出浮点寄存器，并根据需要转换为浮点格式。提供单独的处理器指令用于格式转换和数据传输，以允许转换和传输操作分离。

118. 发明授权

US06233676B1 Apparatus and method for fast forward branch 有权
标题翻译：快进分支装置及方法
公开(公告)号：US06233676B1
公开(公告)日：2001-05-15
申请号：US09272226
申请日：1999-03-18
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F938
CPC分类号： G06F9/30069 , G06F9/30058 , G06F9/3802 , G06F9/3804
摘要： An apparatus and method are provided for executing a forward branch in a microprocessor. The apparatus has translation logic and instruction fetch logic. The translation logic utilizes a branch predictor to determine if a conditional branch should be taken or not. If the branch is predicted taken, then a branch accelerator in the instruction fetch logic determines if a branch target instruction has already been stored for translation in an instruction buffer by summing the length of the conditional branch instruction to a displacement provided by the conditional branch instruction. If the branch target instruction is already within the instruction buffer, contents of the instruction buffer are simply shifted by the number of bytes indicated by the sum to move the branch target instruction to the front of the buffer.
摘要翻译：提供了一种在微处理器中执行前向分支的装置和方法。该装置具有翻译逻辑和指令提取逻辑。翻译逻辑利用分支预测器来确定是否应该采用条件分支。如果预测分支，则指令提取逻辑中的分支加速器通过将条件分支指令的长度与由条件分支指令提供的位移相加来确定分支目标指令是否已经被存储在指令缓冲器中用于转换。如果分支目标指令已经在指令缓冲器内，则指令缓冲器的内容被简单地移位由和指示的字节数以将分支目标指令移动到缓冲器的前端。

119. 发明授权

US06230261B1 Method and apparatus for predicting conditional branch instruction outcome based on branch condition test type 有权
标题翻译：基于分支条件测试类型预测条件分支指令结果的方法和装置
公开(公告)号：US06230261B1
公开(公告)日：2001-05-08
申请号：US09203900
申请日：1998-12-02
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F932
CPC分类号： G06F9/3848 , G06F9/3846
摘要： An apparatus and method for improving the execution of conditional branch instructions is provided. A static branch predictor makes predictions about the outcomes of branch instructions based upon a combination of the test type (such as jump on overflow, jump if negative, jump if zero, jump on carry, etc.) and the sign of the displacement of the branch instruction. If the test type of the branch instruction is one of a subset of test types from which the branch outcome can accurately be predicted solely from the test type, then the predictor makes such a prediction. Otherwise, the predictor makes a prediction based upon the sign of the displacement used to calculate the branch target address. In this case, backward jumps are predicted taken and forward jumps are predicted not taken.
摘要翻译：提供了一种改进条件转移指令执行的装置和方法。静态分支预测器基于测试类型的组合（例如跳跃上溢，跳跃如果为负，跳跃如果为零，跳转等等）和分支指令的移位的符号，对分支指令的结果进行预测分支指令。如果分支指令的测试类型是测试类型的子集之一，则可以从测试类型的子集中精确地从测试类型预测分支结果，则预测器进行这样的预测。否则，预测器基于用于计算分支目标地址的位移的符号进行预测。在这种情况下，预测采取向后跳跃，并且预测未跳转跳跃。

120. 发明授权

US06226737B1 Apparatus and method for single precision multiplication 失效
标题翻译：单精度乘法的装置和方法
公开(公告)号：US06226737B1
公开(公告)日：2001-05-01
申请号：US09116189
申请日：1998-07-15
申请人： Timothy A. Elliott , G. Glenn Henry
发明人： Timothy A. Elliott , G. Glenn Henry
IPC分类号： G06F9302
CPC分类号： G06F9/3885 , G06F7/523 , G06F7/5324 , G06F9/30014 , G06F2207/382
摘要： An apparatus and method for performing single precision multiplication in a microprocessor are provided. The apparatus includes translation logic and extended precision floating point execution logic. The translation logic decodes a single precision multiply instruction into an associated micro instruction sequence directing the microprocessor to fetch a single precision operand from memory and convert it to extended precision format. In addition, the associated micro instruction sequence directs floating point execution logic employing a dual pass multiplication unit to skip a pass associated with computing an insignificant partial product. This insignificant partial product would otherwise result from multiplication of a multiplicand by zeros which are appended to the significand of the fetched operand when it is converted to extended precision format.
摘要翻译：提供了一种用于在微处理器中执行单精度乘法的装置和方法。该装置包括翻译逻辑和扩展精度浮点执行逻辑。翻译逻辑将单个精度乘法指令解码为相关联的微指令序列，指示微处理器从存储器获取单精度操作数并将其转换为扩展精度格式。此外，相关联的微指令序列引导使用双通乘法单元的浮点执行逻辑来跳过与计算不重要的部分乘积相关联的通过。否则，这种无关紧要的部分乘积将通过被乘数乘以零而产生，当被转换为扩展精度格式时，被乘数乘以所提取的操作数的有效位数。

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