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111. 发明申请

US20060164896A1 Memory cell array biasing method and a semiconductor memory device 有权
标题翻译：存储单元阵列偏置方法和半导体存储器件
公开(公告)号：US20060164896A1
公开(公告)日：2006-07-27
申请号：US11327967
申请日：2006-01-09
申请人： Beak-Hyung Cho , Du-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人： Beak-Hyung Cho , Du-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号： G11C7/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device are provided. The semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.
摘要翻译：提供了一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件。半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多条第一线路中的相应第一线路，而存储器单元的第二端子连接到多个第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

112. 发明申请

US20050270883A1 Memory device with reduced word line resistance 有权
标题翻译：具有减少字线电阻的存储器件
公开(公告)号：US20050270883A1
公开(公告)日：2005-12-08
申请号：US11035205
申请日：2005-01-12
申请人： Beak-Hyung Cho , Du-Eung Kim
发明人： Beak-Hyung Cho , Du-Eung Kim
IPC分类号： G11C13/00 , G11C8/00 , G11C8/08 , G11C8/14 , G11C13/02
CPC分类号： G11C13/0028 , G11C8/08 , G11C8/14 , G11C13/0004
摘要： A memory device includes a plurality of blocks, with each block having a respective array of memory cells and respective local word lines. The memory device also includes a respective switching device coupled between each local word line and a common voltage node. A global word line driver controls the respective switching devices to turn on for respective local word lines in a row across the blocks including an accessed memory cell. Thus, the common voltage node is in the current path of the accessed memory cell with minimized layout area and resistance of the current path.
摘要翻译：存储器件包括多个块，每个块具有相应的存储器单元阵列和相应的本地字线。存储器件还包括耦合在每个本地字线和公共电压节点之间的相应开关器件。全局字线驱动器控制相应的开关装置对跨越包括访问的存储器单元的块的行中的相应本地字线导通。因此，公共电压节点处于被访问的存储器单元的当前路径中，具有最小的布局面积和当前路径的电阻。

113. 发明申请

US20050169093A1 Phase-change memory device and method of writing a phase-change memory device 有权
标题翻译：相变存储器件以及相变存储器件的写入方法
公开(公告)号：US20050169093A1
公开(公告)日：2005-08-04
申请号：US10919371
申请日：2004-08-17
申请人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
发明人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
IPC分类号： G11C13/02 , G11C8/00 , G11C16/02
CPC分类号： G11C13/0004 , G11C13/0023 , G11C13/0069 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.
摘要翻译：相变单元存储器件包括多个相变存储器单元，地址电路，写入驱动器和写入驱动器控制电路。相变存储单元各自包括可在非晶态和晶态之间编程的材料体积。地址电路选择存储单元中的至少一个，并且写入驱动器产生复位脉冲电流以将由地址电路选择的存储单元编程为非晶状态，以及设置脉冲电流以对由地址选择的存储单元进行编程电路进入结晶状态。写入驱动器控制电路根据写入驱动器和由地址电路选择的存储器单元之间的负载来改变复位和设置脉冲电流中的至少一个的脉冲宽度和脉冲计数中的至少一个。

114. 发明授权

US06288926B1 Static semiconductor memory device and fabricating method thereof 有权
标题翻译：静态半导体存储器件及其制造方法
公开(公告)号：US06288926B1
公开(公告)日：2001-09-11
申请号：US09535871
申请日：2000-03-27
申请人： Du-Eung Kim , Byung-Gil Choi , Sang-Jib Han , Choong-Keun Kwak , Soon-Moon Jung , Sung-Bong Kim
发明人： Du-Eung Kim , Byung-Gil Choi , Sang-Jib Han , Choong-Keun Kwak , Soon-Moon Jung , Sung-Bong Kim
IPC分类号： G11C506
CPC分类号： G11C5/063 , G11C11/412
摘要： A semiconductor memory device is disclosed. The device is comprised of a plurality of word lines; a plurality of bit lines arranged in perpendicular to the word lines. In addition, a plurality of supply voltage lines extend in the same direction as the bit lines. Also, a plurality of first ground voltage lines are arranged in the same direction as the bit lines. Further, a plurality of second ground voltage lines are arranged in the same direction as the word lines. A plurality of memory cells are each connected between one of the word lines and one of the bit lines. Here, the ground voltage lines are arranged in a matrix shape to reduce the resistance of the ground voltage line and secure the margin between the supply voltage level and the ground voltage level of the data latched by the memory cells to thereby prevent an operational failure of the device.
摘要翻译：公开了一种半导体存储器件。该装置由多条字线组成; 垂直于字线布置的多个位线。此外，多个电源电压线沿与位线相同的方向延伸。此外，多个第一接地电压线被布置在与位线相同的方向上。此外，多个第二接地电压线布置在与字线相同的方向上。多个存储单元分别连接在一条字线和一条位线之间。这里，接地电压线被布置成矩阵形状以减小接地电压线的电阻并且确保由存储器单元锁存的数据的电源电压电平和接地电压电平之间的裕度，从而防止装置。

115. 发明授权

US5754487A Bit line precharge circuit 失效
标题翻译：位线预充电电路
公开(公告)号：US5754487A
公开(公告)日：1998-05-19
申请号：US749277
申请日：1996-11-13
申请人： Du-Eung Kim , Choong-Keun Kwak , Young-Ho Suh , Hyun-Geun Byun
发明人： Du-Eung Kim , Choong-Keun Kwak , Young-Ho Suh , Hyun-Geun Byun
IPC分类号： G11C11/41 , G11C7/12 , G11C11/407 , G11C7/00
CPC分类号： G11C7/12
摘要： An SRAM, which includes a plurality of bit line pairs, a memory cell connected between each pair of the bit lines, and an address transition detection circuit for detecting transition of the externally applied address signal to generate a detection pulse signal, is provided with an improved bit line precharge circuit requiring only two transistors per bit line pair. The new precharge circuit is controlled by a bit line precharge control signal generator for generating a control signal determined by a ratio of impedances connected between a source voltage and ground voltage.
摘要翻译：包括多个位线对的SRAM，连接在每对位线之间的存储单元，以及用于检测外部施加的地址信号的转换以产生检测脉冲信号的地址转换检测电路，改进的位线预充电电路每位线对只需要两个晶体管。新的预充电电路由位线预充电控制信号发生器控制，用于产生由源电压和接地电压之间连接的阻抗比确定的控制信号。

116. 发明授权

US08264905B2 Nonvolatile memory device using variable resistive element 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US08264905B2
公开(公告)日：2012-09-11
申请号：US12406441
申请日：2009-03-18
申请人： Byung-Gil Choi , Du-Eung Kim
发明人： Byung-Gil Choi , Du-Eung Kim
IPC分类号： G11C16/08
CPC分类号： G11C8/08 , G11C8/14 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50008 , G11C2029/1202
摘要： A nonvolatile memory device using variable resistive element with reduced layout size and improved performance is provided. The nonvolatile memory device comprising: a main word line; multiple sub-word lines, wherein each of the sub-word line is connected to multiple nonvolatile memory cells; and a section word line driver which controls voltage level of the multiple sub-word lines, wherein the section word line driver includes multiple pull-down elements which are connected to each of the multiple sub-word lines and a common node and a selection element which is connected to the common node and the main word line.
摘要翻译：提供了使用可变电阻元件的非易失性存储器件，其具有减小的布局尺寸和改进的性能。所述非易失性存储器件包括：主字线; 多个子字线，其中每个子字线连接到多个非易失性存储器单元; 以及区域字线驱动器，其控制所述多个子字线的电压电平，其中所述部分字线驱动器包括连接到所述多个子字线中的每一个的多个下拉元件，以及公共节点和选择元件其连接到公共节点和主字线。

117. 发明授权

US08179711B2 Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell 有权
标题翻译：具有堆叠存储单元的半导体存储器件和制造堆叠存储单元的方法
公开(公告)号：US08179711B2
公开(公告)日：2012-05-15
申请号：US12273225
申请日：2008-11-18
申请人： Sung-min Kim , Eun-jung Yun , Jong-soo Seo , Du-eung Kim , Beak-hyung Cho , Byung-seo Kim
发明人： Sung-min Kim , Eun-jung Yun , Jong-soo Seo , Du-eung Kim , Beak-hyung Cho , Byung-seo Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C5/02 , G11C7/18 , G11C11/15 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2213/71 , G11C2213/74 , G11C2213/79 , H01L27/24
摘要： In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.
摘要翻译：在半导体存储器件和方法中，提供了电阻变化存储单元，每个包括形成在不同层上的多个控制晶体管和包括电阻变化存储器的可变电阻器件。每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。在一个示例中，控制晶体管的数量是两个。半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个电阻变化存储单元组。每个电阻变化存储单元组中的每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。因此，可以增加半导体存储器件的集成密度和流过每个电阻变化存储单元的电流量。

118. 发明授权

US08085575B2 Nonvolatile memory device and method of driving the same 有权
标题翻译：非易失存储器件及其驱动方法
公开(公告)号：US08085575B2
公开(公告)日：2011-12-27
申请号：US12585728
申请日：2009-09-23
申请人： Byung-Gil Choi , Du-Eung Kim , Hye-Jin Kim
发明人： Byung-Gil Choi , Du-Eung Kim , Hye-Jin Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C7/02 , G11C7/12 , G11C7/18 , G11C13/00 , G11C13/0004 , G11C13/0026
摘要： A nonvolatile memory device and a method of driving the same are provided, which adopt an improved write operation. The method of driving a nonvolatile memory device includes providing the nonvolatile memory device including a plurality of memory banks each having a plurality of local bit lines and a plurality of variable resistance memory cells; selectively connecting read global bit lines for reading data with the local bit lines, and firstly discharging the selectively connected local bit lines by turning on local bit line discharge transistors coupled to the read global bit lines; and selectively connecting write global bit lines for writing data with the local bit lines, and secondly discharging the selectively connected local bit lines by turning on global bit line discharge transistors.
摘要翻译：提供一种非易失性存储器件及其驱动方法，其采用改进的写入操作。驱动非易失性存储器件的方法包括提供包括多个存储体的非易失性存储器件，每个存储器组具有多个局部位线和多个可变电阻存储器单元; 选择性地连接读取全局位线用于与局部位线一起读取数据，并且首先通过连接耦合到读出的全局位线的局部位线放电晶体管来放电选择性连接的局部位线; 并选择性地连接用于将数据写入本地位线的写入全局位线，以及其次通过导通全局位线放电晶体管对选择连接的局部位线进行放电。

119. 发明申请

US20110242886A1 Apparatus and Systems Using Phase Change Memories 有权
标题翻译：使用相变记忆的装置和系统
公开(公告)号：US20110242886A1
公开(公告)日：2011-10-06
申请号：US13091238
申请日：2011-04-21
申请人： Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
发明人： Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
IPC分类号： G11C11/21
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092
摘要： Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.
摘要翻译：提供了使用相变存储器件的装置和系统。相变存储器件可以包括多个相变存储器单元和被配置为输出多个顺序复位脉冲的复位脉冲发生电路。每个顺序复位脉冲被输出到多个复位线中相应的一个。多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。

120. 发明申请

US20110213922A1 PHASE CHANGE RANDOM ACCESS MEMORY DEVICE AND RELATED METHODS OF OPERATION 有权
标题翻译：相变随机访问存储器件及相关操作方法
公开(公告)号：US20110213922A1
公开(公告)日：2011-09-01
申请号：US13108143
申请日：2011-05-16
申请人： Hye-jin KIM , Kwang-jin LEE , Du-eung KIM
发明人： Hye-jin KIM , Kwang-jin LEE , Du-eung KIM
IPC分类号： G06F12/02
CPC分类号： G11C13/0064 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0092
摘要： A method of operating a phase change random access memory (PRAM) device includes performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.
摘要翻译：操作相变随机存取存储器（PRAM）装置的方法包括执行程序操作以将数据存储在所述装置的所选PRAM单元中，其中所述程序操作包括多个顺序程序循环。该方法还包括在编程操作的中间暂停编程操作，并且在暂停编程操作之后，响应于恢复命令恢复程序操作。

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