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101. 发明授权

US4859263A Process for the manufacture of printed circuits 失效
标题翻译：印刷电路制造工艺
公开(公告)号：US4859263A
公开(公告)日：1989-08-22
申请号：US169830
申请日：1988-03-17
申请人： Heinz-Jurgen Dziurla , Hans-Leo Weber , Dieter Freitag , Werner Waldenrath
发明人： Heinz-Jurgen Dziurla , Hans-Leo Weber , Dieter Freitag , Werner Waldenrath
IPC分类号： B41M5/26 , H05K3/04 , H05K3/22
CPC分类号： H05K3/046 , H05K2203/0528 , H05K2203/1105
摘要： A method for manufacturing printed electrical circuits which comprise a substrate and copper foil applied thereto by hot embossing in a predetermined circuit pattern, said method comprising(a) providing a laminate which comprises the sequence of a printed circuit substrate, a heat activated adhesive layer, a copper foil and a carrier film which is electrically conductive,(b) passing an electrical current between two electrodes and through the carrier film wherein one electrode has sufficiently large film contact area whereby substantially no resistance heating results from the current density and the other electrode serves as an embossing tool and is of sufficiently small film contact area whereby sufficient resistance heating results from the current density to activate the adhesive layer to bond the copper foil to the substrate in the pattern of said other electrode, and(c) removing from the laminate the carrier film and such copper foil overlying areas where the adhesive was not heat activated thereby leaving a copper foil pattern bonded to the substrate.
摘要翻译：一种制造印刷电路的方法，其包括以预定电路图案通过热压印施加到其上的基板和铜箔，所述方法包括（a）提供包括印刷电路基板，热活化粘合剂层，铜箔和导电的载体膜，（b）在两个电极之间通过电流并通过载体膜，其中一个电极具有足够大的膜接触面积，从而基本上不受电流密度的影响，另一个电极用作压花工具，并且具有足够小的膜接触面积，从而由电流密度产生足够的电阻加热，以激活粘合剂层，以将铜箔与基板以所述另一个电极的图案结合，以及（c）将载体膜和这种铜箔叠合在不粘合剂的区域上热激活，从而留下结合到基底的铜箔图案。

102. 发明授权

US4802944A Method of making deactivatable tags 失效
标题翻译：制造可去活标签的方法
公开(公告)号：US4802944A
公开(公告)日：1989-02-07
申请号：US177815
申请日：1988-03-28
申请人： S. Eugene Benge
发明人： S. Eugene Benge
IPC分类号： G06K19/067 , G08B13/24 , H01L21/70 , H05K1/16 , H05K3/04 , H05K3/20 , B32B31/16
CPC分类号： G08B13/242 , G06K19/0672 , G08B13/2437 , G08B13/244 , G08B13/2442 , H01L21/702 , H05K3/046 , H05K3/202 , H05K1/165 , H05K2203/0522 , H05K2203/1545 , Y10T156/1084
摘要： This invention relates to a deactivatable tag useable with an electronic article surveillance system and comprised of planar conductive material cut into a pair of inverse, first and second spiral conductors wrapped about each other and positioned for capacitive and inductive coupling. The invention also relates to method of making tags wherein conductors are cut from a planar web of conductive material in a continuous process in a manner that the cutting results in the formation of two spiral conductors without accompanying waste of conductive material, and thereafter positioning the conductors to provide resonant circuits.
摘要翻译：本发明涉及一种可用于电子物品监视系统的可失活标签，包括平面导电材料，该平面导电材料切割成一对相互缠绕并位于电容和电感耦合的反向，第一和第二螺旋导体。本发明还涉及制造标签的方法，其中以连续工艺从导电材料的平面网状物切割导体，使得切割导致形成两个螺旋导体而不伴随导电材料的浪费，然后定位导体以提供谐振电路。

103. 发明授权

US4789648A Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias 失效
标题翻译：在基板上制造共面多层金属/绝缘体膜并与螺柱通孔同时形成图案化导电线的方法
公开(公告)号：US4789648A
公开(公告)日：1988-12-06
申请号：US791887
申请日：1985-10-28
申请人： Melanie M. Chow , John E. Cronin , William L. Guthrie , Carter W. Kaanta , Barbara Luther , William J. Patrick , Kathleen A. Perry , Charles L. Standley
发明人： Melanie M. Chow , John E. Cronin , William L. Guthrie , Carter W. Kaanta , Barbara Luther , William J. Patrick , Kathleen A. Perry , Charles L. Standley
IPC分类号： H01L21/3205 , H01L21/302 , H01L21/304 , H01L21/3065 , H01L21/3213 , H01L21/768 , H05K3/04 , H05K3/10 , H05K3/46 , H01L21/306
CPC分类号： H01L21/7681 , H01L21/304 , H01L21/32134 , H01L21/7684 , H01L21/76877 , H05K3/04 , H05K3/107 , H05K3/4644
摘要： Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established. The first layer then is covered by an etch stop material. Contact holes are defined in the etch stop material at locations where stud connectors are required. The first layer of insulation is not etched at this time.Next, a second planarized layer of insulation, is deposited over the etch stop material. The second layer insulation, in turn, is etched by photolithography down to the etch stop material to define desired wiring channels, some of which will be in alignment with the previously formed contact holes in the etch stop material. In those locations where the contact holes are exposed, the etching is continued into the first layer of insulation to uncover the underlying first level of patterned conductive material.The channels and via holes are overfilled with metallization. The excess metallization is removed by etching or by chem-mech (chemical-mechanical) polishing.
摘要翻译：图案化的导线通过连接通过绝缘层与螺柱同时形成，以预先形成的多层VLSI芯片技术中的下面的图案化导电线。第一平坦化绝缘层沉积在要选择性地建立触点的图案化导电材料的第一层上。第一层然后被蚀刻停止材料覆盖。在需要螺柱连接器的位置处，在蚀刻停止材料中限定接触孔。此时第一层绝缘层不被蚀刻。接下来，将第二平坦化绝缘层沉积在蚀刻停止材料上。再次通过光刻将第二层绝缘层蚀刻到蚀刻停止材料上，以限定所需的布线通道，其中的一些布线通道将与蚀刻停止材料中先前形成的接触孔对准。在暴露接触孔的那些位置中，蚀刻继续进入第一绝缘层，以露出图案化的导电材料的下面的第一层。通道和通孔充满金属化。通过蚀刻或化学机械（chemical-mechanical）抛光去除多余的金属化。

104. 发明授权

US4707081A Linear light valve arrays having transversely driven electro-optic gates and method of making such arrays 失效
标题翻译：具有横向驱动的电光门的线性光阀阵列和制造这种阵列的方法
公开(公告)号：US4707081A
公开(公告)日：1987-11-17
申请号：US780873
申请日：1985-09-27
申请人： Jose M. Mir
发明人： Jose M. Mir
IPC分类号： G02F1/03 , G02F1/055 , H05K3/04
CPC分类号： G02F1/0551 , Y10T29/49156
摘要： A linear light valve array having transversely driven, discretely addressable, electro-optic gates which selectively change the polarization of incident light is disclosed. The array has a plurality of spaced gates. Each gate includes a planar light receiving top surface which receives incident polarized light, and first and second spaced parallel electrode receiving surfaces that are arranged substantially normal to the top receiving surface. Discretely addressable electrodes are formed on such receiving surfaces. In response to an applied voltage, the electrodes of a gate establish a transverse electric field which changes the plane of polarization of light passing through the gate and substrate. In another aspect of this invention, a method of making such a linear light valve array is disclosed. In accordance with this method, a strip of photoresist material is formed on a wafer of electro-optic material. Grooves are then cut in the wafer on each side of the strip. A conductive layer is formed on the top surface of the wafer in the grooves and on the strip. The photoresist and its overlying conductive layer are removed. A plurality of evenly spaced parallel grooves are then cut in the wafer to define the gates.
摘要翻译：公开了一种线性光阀阵列，其具有选择性地改变入射光的偏振的横向驱动的，可离散寻址的电光栅。阵列具有多个间隔开的栅极。每个门包括接收入射偏振光的平面光接收顶表面和基本上垂直于顶部接收表面布置的第一和第二间隔开的平行电极接收表面。可离散寻址的电极形成在这样的接收表面上。响应于施加的电压，栅极的电极建立横向电场，其改变通过栅极和衬底的光的偏振面。在本发明的另一方面，公开了制造这种线性光阀阵列的方法。根据该方法，在电光材料的晶片上形成光致抗蚀剂材料条。然后在条带的每一侧在晶片上切割槽。导电层形成在晶片的凹槽和带上的顶表面上。去除光致抗蚀剂及其上覆的导电层。然后在晶片中切割多个均匀间隔的平行凹槽以限定栅极。

105. 发明授权

US4663186A Screenable paste for use as a barrier layer on a substrate during maskless cladding 失效
标题翻译：可屏蔽浆料，用于在无掩模包层期间用作衬底上的阻挡层
公开(公告)号：US4663186A
公开(公告)日：1987-05-05
申请号：US855263
申请日：1986-04-24
申请人： Richard F. Indyk , Francisco J. Lamelas , Mark O. Neisser
发明人： Richard F. Indyk , Francisco J. Lamelas , Mark O. Neisser
IPC分类号： H01L23/12 , H01L21/48 , H01L23/498 , H05K3/02 , H05K3/04 , H05K3/14 , H05K3/16 , H05K3/24 , H05K3/28 , B05D3/12 , B05D5/12
CPC分类号： H05K3/048 , H01L21/4867 , H01L23/49883 , H01L2924/0002 , H05K3/143 , Y10T29/49155
摘要： Disclosed is a screening paste for covering a selected portion of a metallurgical pattern on a substrate while leaving other metallurgy uncovered. The paste is free of polymers and consists, in one example, of 75-80% of a ceramic particulate (such as alumina), 2-8% amorphous fumed silica and 15-20% of linear alcohol. The linear alcohol serves as a vehicle to deliver the solid particles in the paste. In use, after covering the selected portion of the metallurgical pattern with the paste, the alcohol content therein is expelled by subjecting to vacuum treatment at room temperature or heating to a low temperature below about 275.degree. C. thereby obtaining an inert, dry and crack-free protective coating. Upon evaporation of a new metal layer onto the substrate and removal of the protective coating and new metal layer from everywhere except the uncovered metallurgy, the metallurgical pattern is selectively coated with the new metal.
摘要翻译：公开了一种用于覆盖基材上的冶金图案的选定部分同时留下未被覆盖的其它冶金的筛选浆料。该浆料不含聚合物，在一个实例中包含75-80％的陶瓷颗粒（例如氧化铝），2-8％无定形热解法二氧化硅和15-20％直链醇。线性醇作为将固体颗粒输送到糊料中的载体。在使用中，在用糊料覆盖冶金图案的选定部分之后，通过在室温下进行真空处理或加热到低于约275℃的低温来排出其中的醇含量，从而获得惰性，干燥和裂纹 - 免保护涂层。当将新的金属层蒸发到基底上并从除了未覆盖的冶金之外的任何地方去除保护涂层和新的金属层时，冶金图案被选择性地涂覆有新的金属。

106. 依法登记的发明

USH133H Printed wiring board circuit isolator tool 失效
公开(公告)号：USH133H
公开(公告)日：1986-09-02
申请号：US698726
申请日：1985-02-06
申请人： Robert D. Huxsol , Leon J. Snyder
发明人： Robert D. Huxsol , Leon J. Snyder
IPC分类号： H05K3/04 , H05K3/22
CPC分类号： H05K3/043 , H05K3/225 , H05K2203/0242 , H05K2203/175
摘要： A tool for isolating a printed circuit wiring trace from a component pin, said tool having a rotatable shank with an internal cavity and external cutting flutes formed on an end thereof. The end of the tool is pushed over the exposed end of the pin such that the cutting flutes bear against the solder material which bridges the gap between the printed wiring trace and the component pin. The tool is then rotated to remove the solder bridge and any underlying wiring trace material to isolate the wiring trace and pin from each other.

107. 发明授权

US4579022A Making process of a die for stamping out patterns 失效
标题翻译：制作模具的过程用于冲压图案
公开(公告)号：US4579022A
公开(公告)日：1986-04-01
申请号：US539799
申请日：1983-10-07
申请人： Yasuo Kasai , Koichi Yamada , Teruo Sakuma , Masahiro Koguchi
发明人： Yasuo Kasai , Koichi Yamada , Teruo Sakuma , Masahiro Koguchi
IPC分类号： B23P15/40 , C23F1/04 , H01L21/48 , H05K3/04 , B21K5/20
CPC分类号： B23P15/406 , C23F1/04 , H01L21/4839 , H05K3/041 , H05K2203/0108
摘要： The invention provides a novel method for manufacturing a knife-edge die for stamping out a metal foil on an insulating base plate such as in the preparation of an electronic circuit board by a technique of photoetching. The method comprises a line pattern of a photoresist film on the die face corresponding to the contour of the desired pattern, subjecting the die face to a first etching to effect substantial side etching behind the photoresist film to leave an edge, removing the photoresist film and subjecting the die face to a second etching to sharpen the edge into a knife edge. The invention further proposes several improvements in the knife-edge die manufactured in the same principle of the method as above such as the adjustment of the depth of the inside recess surrounded by the knife edge with a filling material and knife-edge dies suitable for continuous stamping out provided with one or more of flat-headed presser dies for the preliminary bonding of the metal foil to the base plate prior to stamping out with the knife edge and one or more limiter dies provided on one or both sides of the knife edge in order to prevent unduly deep incision of the knife edge to the base plate.
摘要翻译：本发明提供了一种制造用于在绝缘基板上冲压出金属箔的新颖方法，例如通过光刻技术制备电子电路板。该方法包括在模具表面上对应于期望图案的轮廓的光致抗蚀剂膜的线图案，使模具面进行第一蚀刻以在光致抗蚀剂膜后面实质上的侧蚀刻留下边缘，去除光致抗蚀剂膜和对模具面进行第二次蚀刻以将边缘锐化成刀刃。本发明进一步提出了以与上述方法相同的原理制造的刀刃模具的几个改进，例如用适于连续的填充材料和刀刃模具调整由刀刃包围的内部凹部的深度冲压出设置有一个或多个平头压模，用于在用刀刃冲压出之前将金属箔预先粘合到基板上，并且在刀刃的一侧或两侧设置一个或多个限制器模具以防止刀刃过度切割到基板上。

108. 发明授权

US4517739A Method for making circuit boards with die stamped contact pads and conductive ink circuit patterns 失效
标题翻译：制造具有冲压接触焊盘和导电油墨电路图案的电路板的方法
公开(公告)号：US4517739A
公开(公告)日：1985-05-21
申请号：US553499
申请日：1983-11-21
申请人： George V. Lenaerts , Eugene W. Charchanko , Andrejs Dambenieks
发明人： George V. Lenaerts , Eugene W. Charchanko , Andrejs Dambenieks
IPC分类号： H05K1/09 , H05K1/11 , H05K3/04 , H05K3/40 , H05K3/10
CPC分类号： H05K3/4015 , H05K3/041 , H05K1/095 , H05K1/117 , H05K2203/0108 , H05K3/04 , H05K3/403 , Y10T29/49155
摘要： Printed circuit boards have copper contact pads cut from copper foil and bonded to the circuit board, followed by printing circuit patterns of conductive ink on the board, the pattern connecting with the contact pads. The contact pads are cut from a copper foil strip fed with the circuit board beneath a die. Bonding of the contact pads follows, then printing of the circuit patterns. Boards can be formed from strip material in which case the individual boards are cut from the strip material.
摘要翻译：印刷电路板具有从铜箔切割并接合到电路板的铜接触焊盘，随后印刷电路板上的导电油墨的电路图案，图案与接触焊盘连接。接触垫从在模具下方的电路板供给的铜箔条切割。接触垫的接合跟随，然后打印电路图案。板可以由条带材料形成，在这种情况下，单独的板从条带材料切割。

109. 发明授权

US4515505A Pressure foot assembly for an end mill delete cutter 失效
标题翻译：用于立铣刀的压脚组件删除刀具
公开(公告)号：US4515505A
公开(公告)日：1985-05-07
申请号：US437421
申请日：1982-10-28
申请人： Richard C. Frisbie , David E. Houser , Richard J. Morenus , Edwin L. Thomas
发明人： Richard C. Frisbie , David E. Houser , Richard J. Morenus , Edwin L. Thomas
IPC分类号： B23C9/00 , B23Q3/00 , B26F1/16 , B44B3/06 , H05K3/04 , H05K3/22 , B23C1/06
CPC分类号： B23Q3/002 , B26F1/16 , B44B3/061 , H05K3/043 , H05K3/225 , H05K2203/0195 , H05K2203/175 , Y10T408/56245 , Y10T408/5653 , Y10T409/305544 , Y10T409/30672
摘要： A pressure foot assembly is provided which makes use of a pressure ring mounted in a manner which allows it to float laterally around an end mill cutter which is used to delete circuit lands on a subcomposite printed circuit panel. Enough pressure is provided to keep the ring from rotating and allows the ring to impart a concentrated force very close around the cutter, thus holding the deleted circuit line in place during cutting and keeping cutting burrs to a minimum.
摘要翻译：提供了一种压脚组件，其使用以允许其横向绕侧端铣刀的方式安装的压力环，端铣刀用于删除副复合印刷电路板上的电路板。提供足够的压力以保持环不旋转，并允许环赋予围绕切割器非常接近的集中力，从而在切割期间将删除的电路线保持在适当位置，并将切割毛刺保持最小。

110. 发明授权

US4457972A Enhanced adhesion by high energy bombardment 失效
标题翻译：通过高能量轰击增强附着力
公开(公告)号：US4457972A
公开(公告)日：1984-07-03
申请号：US327896
申请日：1981-12-07
申请人： Joseph E. Griffith , Yuanxun Qiu , Thomas A. Tombrello
发明人： Joseph E. Griffith , Yuanxun Qiu , Thomas A. Tombrello
IPC分类号： B29C35/08 , B29C65/14 , C23C26/02 , H01L21/263 , H01L21/3105 , H01L21/48 , H01L31/0224 , H01L31/0392 , H05K1/03 , H05K3/04 , H05K3/38 , B32B7/04 , B32B15/04
CPC分类号： B29C65/1425 , B29C65/1403 , B29C65/1496 , B29C66/45 , B29C66/472 , B32B37/06 , C23C26/02 , H01L21/263 , H01L21/3105 , H01L21/4846 , H01L31/0224 , H05K3/381 , B29C2035/0872 , B29C66/71 , B29C66/7392 , B29C66/7394 , B32B2310/0881 , B32B2311/02 , B32B2311/12 , H05K1/0306 , H05K1/032 , H05K2201/015 , H05K2203/0528 , H05K2203/107 , H05K3/04 , H05K3/388 , Y02E10/50 , Y10S228/903 , Y10S428/901 , Y10T428/24917 , Y10T428/263 , Y10T428/264 , Y10T428/265 , Y10T428/31536 , Y10T428/31544 , Y10T428/31678 , Y10T428/31692 , Y10T428/31699
摘要： Films (12) of gold, copper, silicon nitride, or other materials are firmly bonded to insulator substrates (12) such as silica, a ferrite, or Teflon (polytetrafluorethylene) by irradiating the interface with high energy ions. Apparently, track forming processes in the electronic stopping region cause intermixing in a thin surface layer resulting in improved adhesion without excessive doping. Thick layers can be bonded by depositing or doping the interfacial surfaces with fissionable elements or alpha emitters.
摘要翻译：金，铜，氮化硅或其他材料的薄膜（12）通过用高能离子照射界面而牢固地结合到绝缘体基底（12）如二氧化硅，铁氧体或特氟隆（聚四氟乙烯）上。显然，电子停止区域中的轨迹形成过程导致在薄的表面层中混合，导致改善的粘合性而不会过度掺杂。可以通过用可裂变元件或α发射体沉积或掺杂界面来结合厚层。

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