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101. 发明授权

US5877656A Programmable clock generator 失效
公开(公告)号：US5877656A
公开(公告)日：1999-03-02
申请号：US865342
申请日：1997-05-29
申请人： Eric N. Mann , John Q. Torode
发明人： Eric N. Mann , John Q. Torode
IPC分类号： G06F1/08 , H03L7/07 , H03L7/183 , H03L7/16
CPC分类号： H03L7/07 , G06F1/08 , H03L7/183
摘要： A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.

102. 发明授权

US5850422A Apparatus and method for recovering a clock signal which is embedded in an incoming data stream 失效
标题翻译：用于恢复嵌入在输入数据流中的时钟信号的装置和方法
公开(公告)号：US5850422A
公开(公告)日：1998-12-15
申请号：US505044
申请日：1995-07-21
申请人： Dao-Long Chen
发明人： Dao-Long Chen
IPC分类号： H03L7/06 , H03L7/07 , H03L7/099 , H04L7/033 , H04L7/00
CPC分类号： H03L7/0996 , H03L7/07 , H04L7/0337
摘要： A method of recovering a clock signal which is embedded in an incoming data stream. The method includes the steps of providing the incoming data stream to a data sampler circuit, first operating the data sampler circuit to select one of a plurality of clock phases wherein the selected clock phase is indicative of the embedded clock signal, generating a recovered clock signal based on the selected clock phase, second operating a retiming circuit in a normal data tracking mode to retime the incoming data stream based on the recovered clock signal, and disabling operation of the data sampler circuit while the retiming circuit is operating in the normal data tracking mode. An apparatus for recovering a clock signal which is embedded in an incoming data stream is also disclosed.
摘要翻译：一种恢复嵌入在输入数据流中的时钟信号的方法。该方法包括以下步骤：将输入数据流提供给数据采样器电路，首先操作数据采样器电路以选择多个时钟相位中的一个，其中选择的时钟相位指示嵌入的时钟信号，产生恢复的时钟信号基于所选择的时钟相位，第二操作在正常数据跟踪模式中的重定时电路，以基于恢复的时钟信号重新输入输入数据流，并且在重新定时电路在正常数据跟踪中操作时禁止数据采样器电路的操作模式。还公开了一种用于恢复嵌入在输入数据流中的时钟信号的装置。

103. 发明授权

US5828257A Precision time interval division with digital phase delay lines 失效
标题翻译：精准时间间隔与数字相位延迟线
公开(公告)号：US5828257A
公开(公告)日：1998-10-27
申请号：US915306
申请日：1997-08-19
申请人： Robert Paul Masleid
发明人： Robert Paul Masleid
IPC分类号： H03K5/156 , H03L7/07 , H03K5/13 , H03K5/159
CPC分类号： H03L7/07 , H03K5/1565
摘要： A time interval division circuit that generates a delayed signal that is a precise integer fraction of the clock cycle. A digital delay loop including a digital delay line is locked to the clock cycle and controls a second digital delay line. The delay line characteristics determine the fraction of the clock cycle generated. The time interval division circuit tracks the clock cycle, rather than on-chip circuit delays as conventional delay lines.
摘要翻译：时间间隔分割电路，其产生作为时钟周期的精确整数分数的延迟信号。包括数字延迟线的数字延迟回路被锁定到时钟周期并且控制第二数字延迟线。延迟线特性决定了所产生的时钟周期的分数。时间间隔分割电路跟踪时钟周期，而不是像传统延迟线一样进行片上电路延迟。

104. 发明授权

US5822387A Apparatus for fast phase-locked loop (PLL) frequency slewing during power on 失效
标题翻译：上电时快速锁相环（PLL）频率回转装置
公开(公告)号：US5822387A
公开(公告)日：1998-10-13
申请号：US622531
申请日：1996-03-25
申请人： Monte F. Mar
发明人： Monte F. Mar
IPC分类号： H03L3/00 , H03L7/07 , H03L7/089 , H03L7/095 , H04L7/00
CPC分类号： H03L7/095 , H03L3/00 , H03L7/07 , H03L7/0891
摘要： A clock synthesizer is disclosed that includes a phase-locked loop circuit having two modes of operation: a non-slewing mode of operation, and a frequency-slewing mode of operation. During the power-up of the system, the PLL is controlled to operate in the non-slewing mode of operation to effect rapid variations in the output frequency. A power-on reset circuit is disclosed which determines when the system is in the power-up interval, and generates a power-on-reset signal to so indicate. The PLL operates in a frequency-slewing mode after power-up to provide controlled transitions in the frequency of the output reference signal of the PLL. A phase-locked loop circuit having structure to implement both modes is provided, as well as an adjustable lock detector circuit. The output of the lock detector, a logical lock signal, is used to enable the frequency-slewing mode of the PLL circuit. During power-up, the power-on-reset signal is deasserted, and disables the lock detector from generating the frequency-slewing mode enable signal. The PLL thus operates in a non-slewing mode during power-up. After the power-on-reset signal has been asserted, the lock detector is permitted to generate the frequency-mode enable signal as soon as the PLL achieves phase lock. Once phase lock has been achieved, the enable signal from the lock detector places the PLL in a frequency-slewing mode. The phase-locked loop circuit includes structure that limits the rate of variation in the frequency of the output reference signal, as well as limits the UP, and DOWN signals, by way of a reference window signal mechanism, to ensure that the lock detector, after power-up, always detects lock to thereby generate the frequency-slewing mode enable signal.
摘要翻译：公开了一种时钟合成器，其包括具有两种操作模式的锁相环电路：非回转工作模式和频率回转操作模式。在系统上电期间，PLL被控制为在非回转工作模式下工作，以实现输出频率的快速变化。公开了一种上电复位电路，其确定系统何时处于上电间隔，并产生如上所述的上电复位信号。 PLL在上电后以频率回转模式工作，以提供PLL输出参考信号频率的受控转换。提供具有实现两种模式的结构的锁相环电路以及可调锁定检测器电路。锁定检测器（逻辑锁定信号）的输出用于使能PLL电路的频率回转模式。在上电期间，上电复位信号被断言，并禁止锁定检测器产生频率回转模式使能信号。因此，PLL在上电期间以非回转模式工作。在上电复位信号被置位之后，一旦PLL达到锁相，就允许锁定检测器产生频率模式使能信号。一旦实现了相位锁定，来自锁定检测器的使能信号将PLL置于频率回转模式。锁相环电路包括限制输出参考信号的频率变化率的结构，以及通过参考窗口信号机制限制UP和DOWN信号，以确保锁定检测器，上电后，始终检测到锁定，从而产生频率回转模式使能信号。

105. 发明授权

US5818305A Automatic substitution of a reference oscillator for synchronizing two transmitter co-channel local oscillators 失效
标题翻译：自动替换参考振荡器来同步两个发射机同信道本地振荡器
公开(公告)号：US5818305A
公开(公告)日：1998-10-06
申请号：US688371
申请日：1996-07-30
申请人： Seong-Min Jeon
发明人： Seong-Min Jeon
IPC分类号： H03L7/00 , H03B5/18 , H03D7/00 , H03J5/24 , H03L7/07 , H04B1/04
CPC分类号： H03L7/07 , H03J5/244 , H03B5/1864 , H03D7/00
摘要： A circuit for automatically substituting a reference oscillator for synchronizing two transmitter co-channel local oscillators. The circuit includes a first bias switching device for switching a first power supply to a first reference oscillator and a second bias switching device for switching a second power supply to a second reference oscillator. The first and second reference oscillators generate first and second reference signals for synchronizing the oscillator frequencies. A first divider firstly and secondly divides and outputs the power of the first reference signal. A second divider firstly and secondly divides and outputs the power of the second reference signal. A first combining device inputs the power of the firstly-divided first reference signal and the secondly-divided second reference signal and outputs the power to the phase locked dielectric resonator oscillator for the vertical polarization wave. A second combining device inputs the power of the firstly-divided second reference signal and the secondly-divided first reference signal and outputs the power to the phase locked dielectric resonator oscillator for the horizontal polarization wave. A first switching control switches the second bias switching device in response to generation of the first reference signal secondly-divided in the first divider. A second switching control switches the first bias switching device in response to generation of the second reference signal secondly-divided in the second divider.
摘要翻译：用于自动替换参考振荡器以同步两个发射机同信道本地振荡器的电路。电路包括用于将第一电源切换到第一参考振荡器的第一偏置开关装置和用于将第二电源切换到第二基准振荡器的第二偏置开关装置。第一和第二参考振荡器产生用于使振荡器频率同步的第一和第二参考信号。第一分频器首先分频并输出第一参考信号的功率。第一分频器首先分频并输出第二参考信号的功率。第一组合装置输入第一分频第一参考信号和第二分频第二参考信号的功率，并将功率输出到用于垂直偏振波的锁相介质谐振器振荡器。第二组合装置输入第一分频第二参考信号和第二分频第一参考信号的功率，并输出到用于水平偏振波的锁相介质谐振器振荡器。第一开关控制器响应于在第一分压器中被二次分压的第一参考信号的产生来切换第二偏置开关装置。第二开关控制器响应于在第二分频器中被二次分频的第二参考信号的产生来切换第一偏置开关装置。

106. 发明授权

US5801570A Semiconductor intergrated circuit with MOS transistors compensated of characteristic and performance deviations and deviation compensation system therein 失效
标题翻译：具有MOS晶体管的半导体集成电路补偿其特性和性能偏差以及偏差补偿系统
公开(公告)号：US5801570A
公开(公告)日：1998-09-01
申请号：US859089
申请日：1997-05-20
申请人： Masayuki Mizuno , Masakazu Yamashina
发明人： Masayuki Mizuno , Masakazu Yamashina
IPC分类号： H01L27/04 , G05F3/24 , G11C11/407 , H01L21/822 , H03K17/30 , H03K19/00 , H03K19/003 , H03L7/07 , H03L7/081 , H03L7/089 , G06G7/12
CPC分类号： H03L7/0805 , H03K19/0013 , H03K19/00384 , H03L7/07 , H03L7/0812 , G05F3/247 , H03L7/0891
摘要： A plurality of MOS transistors connected to each other at a substrate electrode thereof to have a substrate potential are deviation-compensated by a combination of a power source having a power source potential independent from the substrate potential, a power supply line connected to a source electrode of each of the MOS transistors, a sample circuit composed of a sampled one of the MOS transistors, detection circuitry for detecting an action of the sample circuit to provide a detection signal representing a difference between the detected action of the sample circuit and a reference action therefor, and a voltage generator connected between the power source and the power supply line, the voltage generator generating a voltage depending on the detection signal.
摘要翻译：在其基板电极处彼此连接以具有衬底电位的多个MOS晶体管通过具有独立于衬底电位的电源电位的电源的组合进行偏差补偿，连接到源电极的电源线的每个MOS晶体管的采样电路，由采样的一个MOS晶体管构成的采样电路，检测电路，用于检测采样电路的动作，以提供表示检测到的采样电路的动作与参考动作之间的差异的检测信号以及连接在电源和电源线之间的电压发生器，电压发生器根据检测信号产生电压。

107. 发明授权

US5801562A Variable delay circuit 失效
标题翻译：可变延迟电路
公开(公告)号：US5801562A
公开(公告)日：1998-09-01
申请号：US687037
申请日：1996-07-25
申请人： Haruhiko Fujii
发明人： Haruhiko Fujii
IPC分类号： H03K5/14 , G06F1/12 , H03K5/135 , H03L7/07 , H03L7/081 , H04L7/02 , H03K5/00
CPC分类号： H03L7/0805 , H03K5/135 , H03L7/07 , H03L7/0812
摘要： A variable delay circuit is disclosed comprising first and second clock delay sections, first and second phase comparison circuits, first and second data delay sections, and a selector. The first and second clock delay sections delay a clock signal to generate first and second delayed clock signals. The first and second phase comparison circuits respectively detect a phase difference between the clock signal and the first delayed clock signal and a phase difference between the clock signal and the second delayed clock signal. The first and second phase comparison circuits then respectively supply first and second delay control signals indicating the phase differences to the first and second clock delay sections so as to equalize the delay times of the clock delay sections to a period of the clock signal. The first and second data delay circuits delay a data signal. The delay times of the first and second data delay sections are respectively controlled based on the first and second delay control signals so as to be proportional to the period of the clock signal. One of the output signals of the first and second data delay sections is selected by the selector based on a delay designating data.
摘要翻译：公开了一种可变延迟电路，包括第一和第二时钟延迟部分，第一和第二相位比较电路，第一和第二数据延迟部分以及选择器。第一和第二时钟延迟部分延迟时钟信号以产生第一和第二延迟的时钟信号。第一和第二相位比较电路分别检测时钟信号和第一延迟时钟信号之间的相位差以及时钟信号和第二延迟时钟信号之间的相位差。然后，第一和第二相位比较电路分别向第一和第二时钟延迟部分提供指示相位差的第一和第二延迟控制信号，以将时钟延迟部分的延迟时间均衡到时钟信号的周期。第一和第二数据延迟电路延迟数据信号。分别基于第一和第二延迟控制信号来控制第一和第二数据延迟部分的延迟时间，以便与时钟信号的周期成比例。基于延迟指定数据，选择器选择第一和第二数据延迟部分的输出信号之一。

108. 发明授权

US5799051A Delay stage circuitry for a ring oscillator 失效
标题翻译：环形振荡器的延迟级电路
公开(公告)号：US5799051A
公开(公告)日：1998-08-25
申请号：US711908
申请日：1996-09-12
申请人： Wingyu Leung , Mark Alan Horowitz
发明人： Wingyu Leung , Mark Alan Horowitz
IPC分类号： H03K3/0231 , H03K3/03 , H03K3/354 , H03L7/06 , H03L7/07 , H03L7/099 , H04J3/06 , H04L7/033 , H03D3/24
CPC分类号： H03L7/0996 , H03K3/0231 , H03K3/0322 , H03K3/354 , H03L7/06 , H03L7/07 , H04L7/0337
摘要： A ring oscillator includes an even-numbered plurality of ring coupled delay stages. Each delay stage includes a differential amplifier, a voltage clamping circuit, and a current source. The differential amplifier receives first and second input signals from a preceding delay stage. The differential amplifier provides a first output signal and a complementary second output signal at first and second nodes, respectively. The voltage clamping circuit is coupled between the first and second nodes to limit a peak-to-peak voltage swing of each of the first and second output signals. The current source is coupled to the differential amplifier and varies a bias current in accordance with a delay bias voltage.
摘要翻译：环形振荡器包括偶数个多个环形耦合延迟级。每个延迟级包括差分放大器，钳位电路和电流源。差分放大器接收来自前一延迟级的第一和第二输入信号。差分放大器分别在第一和第二节点处提供第一输出信号和互补的第二输出信号。电压钳位电路耦合在第一和第二节点之间以限制第一和第二输出信号中的每一个的峰 - 峰电压摆幅。电流源耦合到差分放大器，并根据延迟偏置电压改变偏置电流。

109. 发明授权

US5789987A Low-noise frequency synthesizer 失效
标题翻译：低噪音频率合成器
公开(公告)号：US5789987A
公开(公告)日：1998-08-04
申请号：US589362
申请日：1996-01-22
申请人： James Gregory Mittel , Scott Humphreys
发明人： James Gregory Mittel , Scott Humphreys
IPC分类号： H03L7/07 , H03L7/093 , H03L7/06 , H03C1/06
CPC分类号： H03L7/0805 , H03L7/07 , H03L7/093
摘要： A frequency synthesizer (100) is utilized for producing an output signal (124) which is phase locked to a reference signal (110) operating at a reference frequency. The frequency synthesizer (100) comprises a main phase lock loop (PLL) (102), and a tracker PLL (128). The main PLL (102) includes a phase detector (112), two frequency dividers (108, 126), a loop filter (116), a notch filter (118), and a controlled oscillator (122). The tracker PLL (128) phase locks to the reference signal (110), and biases the notch filter (118) in order to maintain an accurate lock on the notch frequency which is proportional to the reference frequency. All circuits are integrated in the same monolithic device in order to track parametric tolerances such as transconductances of the operational transconductance devices included in the tracker PLL (128) and the notch filter (118).
摘要翻译：频率合成器（100）用于产生与参考频率工作的参考信号（110）相位锁定的输出信号（124）。频率合成器（100）包括主锁相环（PLL）（102）和跟踪器PLL（128）。主PLL（102）包括相位检测器（112），两个分频器（108,126），环路滤波器（116），陷波滤波器（118）和受控振荡器（122）。跟踪器PLL（128）相锁定到参考信号（110），并且偏置陷波滤波器（118），以便保持与参考频率成比例的陷波频率的准确锁定。所有电路都集成在相同的单片设备中，以便跟踪参数公差，例如包括在跟踪器PLL（128）和陷波滤波器（118）中的工作跨导器件的跨导。

110. 发明授权

US5786953A Arrangement for reproducing n digital signals having n phase-locked loops each including a phase shifter, controlled by an integrating element, arranged between a VCO output and a phase detector 失效
标题翻译：用于再现具有n个锁相环的n个数字信号的装置，每个锁相环包括由积分元件控制的移相器，布置在VCO输出和相位检测器之间
公开(公告)号：US5786953A
公开(公告)日：1998-07-28
申请号：US798589
申请日：1997-02-11
申请人： Joahnnes J. W. Kalfs
发明人： Joahnnes J. W. Kalfs
IPC分类号： G11B5/008 , G11B20/10 , G11B20/14 , G11B20/20 , H03L7/07 , H03L7/081 , H03L7/087 , G11B5/09 , G11B15/12
CPC分类号： H03L7/07 , G11B20/1403 , G11B20/20 , H03L7/081 , H03L7/087 , G11B20/10527 , G11B5/0083
摘要： For clock extraction (Cl.sub.n) from n digital signals read from each of n tracks (T.sub.a.1 to T.sub.a.n), there are provided n phase-locked loops (13,n). Voltage-controlled oscillator (21) is common to the n phase-locked loops. Each phase-locked loop further includes a phase-shifter unit (25.n) having an input coupled to the output of the voltage-controlled oscillator (21) and an output coupled to the second input of the phase comparator (17,n) in the loop. The phase shift in the phase-shifter unit (25.n) is controlled under the influence of a control signal which is derived by a control signal generator (26.n) and applied to a control signal input (29) of the phase-shifter unit (25.n). The control signal generator unit (26.n) is an integrating element.
摘要翻译：对于从n个磁道（Ta.1至Ta.n）中的每一个读取的n个数字信号的时钟提取（Cln），提供了n个锁相环（13，n）。压控振荡器（21）对于n个锁相环是共同的。每个锁相环还包括具有耦合到压控振荡器（21）的输出的输入和耦合到相位比较器（17，n）的第二输入的输出的移相器单元（25.n）在循环。在由控制信号发生器（26.n）导出的控制信号的影响下控制移相器单元（25.n）中的相移，并施加到相位偏移单元（25.n）的控制信号输入端（29）移位器单元（25.n）。控制信号发生器单元（26.n）是积分元件。

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