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101. 发明申请

US20130021181A1 NON-BINARY SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER 有权
标题翻译：非二进制近似逼近模拟数字转换器
公开(公告)号：US20130021181A1
公开(公告)日：2013-01-24
申请号：US13188482
申请日：2011-07-22
申请人： Nishit Harshad Shah
发明人： Nishit Harshad Shah
IPC分类号： H03M1/12
CPC分类号： H03M1/0692 , H03M1/468
摘要： A successive approximation analog to digital converter (SA-ADC) employs a binary-weighted digital to analog converter (DAC) to perform a non-binary search in determining a digital representation of a sample of an analog signal. In an embodiment, a subset of iterations needed to convert an analog sample to a digital value is performed using non-binary search with a radix of conversion less than two. As a result, search windows in iterations corresponding to the non-binary search overlap, and correction of errors due to a comparator used in the SA-ADC is rendered possible. Error correction being possible due to the non-binary search, the comparator is operated in a low-bandwidth, and hence low-power, mode during the non-binary search. The non-binary search in combination with the binary-weighted architecture of the DAC offer several benefits such as for example, less-complex implementation, shorter conversion time, easier and compact layout and lower power consumption.
摘要翻译：逐次逼近模数转换器（SA-ADC）采用二进制加权数模转换器（DAC）来执行非二进制搜索以确定模拟信号样本的数字表示。在一个实施例中，使用转换小于2的非二进制搜索来执行将模拟样本转换为数字值所需的迭代子集。结果，对应于非二进制搜索的迭代中的搜索窗口重叠，并且由于在SA-ADC中使用的比较器导致的错误校正成为可能。由于非二进制搜索可能导致误差校正，比较器在非二进制搜索期间以低带宽，因此低功耗模式运行。结合DAC的二进制加权架构的非二进制搜索提供了几个好处，例如，较不复杂的实现，较短的转换时间，更简单和紧凑的布局以及更低的功耗。

102. 发明申请

US20120326900A1 SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER AND CONVERSION METHOD THEREOF 有权
标题翻译：数字近似寄存器模拟数字转换器及其转换方法
公开(公告)号：US20120326900A1
公开(公告)日：2012-12-27
申请号：US13479021
申请日：2012-05-23
申请人： Meng Hsuan WU , Yung-Hui CHUNG
发明人： Meng Hsuan WU , Yung-Hui CHUNG
IPC分类号： H03M1/38
CPC分类号： H03M1/0673 , H03M1/468
摘要： A SAR ADC is provided. A DAC provides an intermediate analog signal according to an analog input signal, a most significant bit capacitance and a plurality of significant bit capacitances smaller than the most significant bit capacitance. A first switched capacitor array selectively provides the most significant bit capacitance or the significant bit capacitances according to a select signal. Sum of the significant bit capacitances is equal to the most significant bit capacitance. The second switched capacitor array provides the significant bit capacitances when the first switched capacitor array provides the most significant bit capacitance, and provides the most significant bit capacitance when the first switched capacitor array provides the significant bit capacitances. A comparator provides a comparison result according to the intermediate analog signal. A SAR logic provides an digital output signal according to the comparison result.
摘要翻译：提供了一个SAR ADC。 DAC根据模拟输入信号，最高有效位电容和小于最高有效位电容的多个有效位电容提供中间模拟信号。第一开关电容器阵列根据选择信号选择性地提供最高有效位电容或有效位电容。有效位电容的总和等于最高有效位电容。当第一开关电容器阵列提供最高有效位电容时，第二开关电容器阵列提供有效位电容，并且当第一开关电容器阵列提供有效位电容时提供最高有效位电容。比较器根据中间模拟信号提供比较结果。 SAR逻辑根据比较结果提供数字输出信号。

103. 发明申请

US20120319886A1 HIGH SPEED RESISTOR-DAC FOR SAR DAC 有权
标题翻译：用于SAR DAC的高速电阻DAC
公开(公告)号：US20120319886A1
公开(公告)日：2012-12-20
申请号：US13164478
申请日：2011-06-20
申请人： Abhijit Kurmar DAS , Krishnasawamy NAGARAJ , Joonsung PARK
发明人： Abhijit Kurmar DAS , Krishnasawamy NAGARAJ , Joonsung PARK
IPC分类号： H03M1/34 , H03M1/12
CPC分类号： H03M1/68 , H03M1/468 , H03M1/765 , H03M1/804
摘要： A singled-ended, successive approximation register analog-to-digital converter convert an analog input voltage to a digital representation comprising m upper order bits and a number of lower order bits. The SAR ADC comprises SAR logic, a resistive network, multiple switches, and first and second LSB capacitors. The switches also comprises two sets of switches coupled to the resistive network, each set of switches is configured to couple a selected tap to each of the first and second LSB capacitors. When determining the lower order bits, the SAR logic is configured to control the sets of switches to change the first and second taps from one cycle in which one of the lower order bits is determined to a next cycle in which the next of the lower order bits is determined so that the voltage of both taps changes by a decreasing amount with each succeeding bit being determined.
摘要翻译：单端逐次逼近寄存器模数转换器将模拟输入电压转换成包括m个高位位和多个低位位的数字表示。 SAR ADC包括SAR逻辑，电阻网络，多个开关以及第一和第二LSB电容。开关还包括耦合到电阻网络的两组开关，每组开关被配置为将所选择的抽头耦合到第一和第二LSB电容器中的每一个。当确定低阶位时，SAR逻辑被配置为控制开关组，以将第一和第二抽头从其中一个较低位确定的下一个周期改变为下一个较低阶的下一个周期确定位，使得两个抽头的电压随着每个后续位被确定而减小量。

104. 发明授权

US08310388B2 Subrange analog-to-digital converter and method thereof 有权
标题翻译：子范围模数转换器及其方法
公开(公告)号：US08310388B2
公开(公告)日：2012-11-13
申请号：US13050449
申请日：2011-03-17
申请人： Soon-Jyh Chang , Ying-Zu Lin , Chun-Cheng Liu
发明人： Soon-Jyh Chang , Ying-Zu Lin , Chun-Cheng Liu
IPC分类号： H03M1/12
CPC分类号： H03M1/145 , H03M1/365 , H03M1/466 , H03M1/468
摘要： The configurations and adjusting method of a subrange analog-to-digital converter (ADC) are provided. The provided subrange ADC includes a X.5-bit flash ADC, a Y-bit SAR ADC and a (X+Y)-bit segmented capacitive digital-to-analog converter (DAC).
摘要翻译：提供了一个子域模数转换器（ADC）的配置和调整方法。提供的子范围ADC包括X.5位闪存ADC，Y位SAR ADC和（X + Y）位分段电容数模转换器（DAC）。

105. 发明申请

US20120280841A1 Zero-power sampling SAR ADC circuit and method 有权
标题翻译：零功率采样SAR ADC电路及方法
公开(公告)号：US20120280841A1
公开(公告)日：2012-11-08
申请号：US13068192
申请日：2011-05-04
申请人： Yan Wang , Timothy V. Kalthoff , Michael A. Wu
发明人： Yan Wang , Timothy V. Kalthoff , Michael A. Wu
IPC分类号： H03M1/12 , H03M1/00
CPC分类号： H03M1/1295 , H03M1/468
摘要： A switched-capacitor circuit (10, 32 or 32A) samples a first signal (VIN+) onto a first capacitor (C1 or CIN1) by switching a top plate thereof via a summing conductor (13) to a first reference voltage (VSS) and switching a bottom plate thereof to the first signal. A second signal (VIN−) is sampled onto a second capacitor (C3 or CIN3) by switching a top plate thereof to the second signal and switching a bottom plate thereof to the first reference voltage. After the sampling, the top plate of the second capacitor is coupled to the top plate of the first capacitor. The bottom plate of the second capacitor is coupled to the first reference voltage. The bottom plate of the first capacitor is coupled to a second reference voltage (VDD or VREF), to thereby cancel at least a portion of a common mode input voltage component from the first conductor (13), hold the sampled differential charge on the summing conductor and establish a predetermined common mode voltage thereon, and prevent the summing conductor from having a voltage which allows the leakage of charge therefrom. The switched-capacitor circuit may be a SAR, an integrator, or an amplifier.
摘要翻译：开关电容器电路（10,32或32A）通过将加法导体（13）的顶板切换到第一参考电压（VSS）而将第一信号（VIN +）采样到第一电容器（C1或CIN1）上，并且将其底板切换到第一信号。将第二信号（VIN-）通过将其顶板切换到第二信号并将其底板切换到第一参考电压而被采样到第二电容器（C3或CIN3）上。在采样之后，第二电容器的顶板耦合到第一电容器的顶板。第二电容器的底板耦合到第一参考电压。第一电容器的底板耦合到第二参考电压（VDD或VREF），从而从第一导体（13）消除共模输入电压分量的至少一部分，将采样的差分电荷保持在求和并在其上建立预定的共模电压，并且防止求和导体具有允许从其中泄漏电荷的电压。开关电容电路可以是SAR，积分器或放大器。

106. 发明申请

US20120229313A1 ANALOG TO DIGITAL CONVERTER CIRCUIT 有权
标题翻译：模拟到数字转换器电路
公开(公告)号：US20120229313A1
公开(公告)日：2012-09-13
申请号：US13232442
申请日：2011-09-14
申请人： Sai-Weng SIN , He-Gong WEI , Franco MALOBERTI , Li DING , Yan ZHU , Chi-Hang CHAN , U-Fat CHIO , Seng-Pan U , Rui Paulo da Silva MARTINS
发明人： Sai-Weng SIN , He-Gong WEI , Franco MALOBERTI , Li DING , Yan ZHU , Chi-Hang CHAN , U-Fat CHIO , Seng-Pan U , Rui Paulo da Silva MARTINS
IPC分类号： H03M1/12
CPC分类号： H03M1/1225 , H03M1/0695 , H03M1/1215 , H03M1/164 , H03M1/468
摘要： The present invention provides an analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design
摘要翻译：本发明提供一种包括两个时间交错的逐次逼近寄存器（SAR）ADC的模数转换器（ADC）电路。两个时间交织的SAR ADC中的每一个包括第一级SAR子ADC，残差放大器，第二级SAR子ADC和数字纠错逻辑。剩余放大器在时间交织路径之间共享，具有减小的增益并且在子阈值中操作以实现功率有效设计

107. 发明申请

US20120212357A1 D/A CONVERSION CIRCUIT, A/D CONVERSION CIRCUIT AND ELECTRONIC APPARATUS 有权
标题翻译： D / A转换电路，A / D转换电路和电子设备
公开(公告)号：US20120212357A1
公开(公告)日：2012-08-23
申请号：US13401485
申请日：2012-02-21
申请人： Hideo HANEDA , Takemi YONEZAWA
发明人： Hideo HANEDA , Takemi YONEZAWA
IPC分类号： H03M1/66 , H03M1/12
CPC分类号： H03M1/066 , H03M1/468 , H03M1/687 , H03M1/804 , H03M1/806
摘要： A D/A conversion circuit includes a first D/A converting section which is connected with an output node, a first serial capacitor which is disposed between the output node and a first node, a second D/A converting section which is connected with the first node, and a control circuit. The first D/A converting section includes a first capacitor array section and a first switch array section. The second D/A converting section includes a second capacitor array section and a second switch array section. The control circuit performs a switch control for dynamically changing allocation of the capacitors to the respective bits of input digital data for the first switch array section of the first D/A converting section.
摘要翻译： AD / A转换电路包括与输出节点连接的第一D / A转换部分，布置在输出节点和第一节点之间的第一串行电容器，与第一D / A转换部分连接的第二D / A转换部分节点和控制电路。第一D / A转换部分包括第一电容器阵列部分和第一开关阵列部分。第二D / A转换部分包括第二电容器阵列部分和第二开关阵列部分。控制电路执行用于动态地改变电容器的分配到第一D / A转换部分的第一开关阵列部分的输入数字数据的各个位的开关控制。

108. 发明申请

US20120146830A1 ANALOG DIGITAL CONVERTER 有权
标题翻译：模拟数字转换器
公开(公告)号：US20120146830A1
公开(公告)日：2012-06-14
申请号：US13243267
申请日：2011-09-23
申请人： Young-deuk JEON , Young Kyun CHO , Jaewon NAM , Jong-Kee KWON
发明人： Young-deuk JEON , Young Kyun CHO , Jaewon NAM , Jong-Kee KWON
IPC分类号： H03M1/12
CPC分类号： H03M1/164 , H03M1/468
摘要： Provided is an analog digital converter (ADC). The ADC includes: a capacitor array generating a level voltage; a comparator outputting a compare signal by comparing the level voltage; and a logic circuit determining digital bits of an analog signal based on the compare signal, wherein the logic circuit determines at least one digital bit among digital bits of the analog signal while a sampling operation of the analog signal is performed in the capacitor array.
摘要翻译：提供了一种模拟数字转换器（ADC）。 ADC包括：产生电平电压的电容器阵列; 比较器，通过比较电平电压输出比较信号; 以及逻辑电路，其基于所述比较信号确定模拟信号的数字位，其中所述逻辑电路在所述电容器阵列中执行所述模拟信号的采样操作时，确定所述模拟信号的数字位中的至少一个数字位。

109. 发明申请

US20120112948A1 COMPACT SAR ADC 有权
公开(公告)号：US20120112948A1
公开(公告)日：2012-05-10
申请号：US13247001
申请日：2011-09-28
申请人： Stéphane Le Tual , Mounir Boulemnakher , Pratap Narayan Singh
发明人： Stéphane Le Tual , Mounir Boulemnakher , Pratap Narayan Singh
IPC分类号： H03M1/12
CPC分类号： H03M1/468
摘要： A method of successive approximation analog to digital conversion including: during a sample phase, coupling an input signal to a plurality of pairs of capacitors; and during a conversion phase, coupling a first capacitor of each pair to a first supply voltage, and a second capacitor of each pair to a second supply voltage.
摘要翻译：一种逐次逼近模数转换的方法，包括：在采样阶段期间，将输入信号耦合到多对电容器; 并且在转换阶段期间，将每对的第一电容器耦合到第一电源电压，将每对的第二电容器耦合到第二电源电压。

110. 发明授权

US08035542B2 Digital-to-analog converter and successive approximation type analog-to-digital converter including the same 有权
标题翻译：数模转换器和包括其的逐次逼近型模数转换器
公开(公告)号：US08035542B2
公开(公告)日：2011-10-11
申请号：US12726072
申请日：2010-03-17
申请人： Kiyoshi Ishikawa
发明人： Kiyoshi Ishikawa
IPC分类号： H03M1/66
CPC分类号： H03M1/468 , H03M1/804
摘要： A digital-to-analog converter generates a voltage from power supply and ground voltages, generates upper and lower limit reference voltages for a reference width which regards the generated voltage as an intermediate potential, converts a change in an analog input signal with respect to the upper and lower limit reference voltages into a digital code, and performs a control in order to achieve a sample and hold of the analog input signal.
摘要翻译：数模转换器从电源和接地电压产生电压，产生将发电电压视为中间电位的参考宽度的上限和下限参考电压，将模拟输入信号的变化相对于将上限参考电压和下限参考电压转换为数字码，并执行控制以实现模拟输入信号的采样和保持。

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