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101. 发明授权

US09311849B2 Inverter, AMOLED compensation circuit and display panel 有权
标题翻译：变频器，AMOLED补偿电路和显示面板
公开(公告)号：US09311849B2
公开(公告)日：2016-04-12
申请号：US14062726
申请日：2013-10-24
申请人： Shanghai Tianma Micro-Electronics Co., Ltd.
发明人： Dong Qian
IPC分类号： G09G3/32 , H03K19/00 , H03K3/012
CPC分类号： G09G3/3225 , H03K3/012 , H03K19/0016 , H03K19/0027
摘要： An inverter is disclosed. The disclosed inverter includes first, second, third, and fourth transistors, where each of the first, second, third, and fourth transistors is a P-type thin film transistor. The inverter also includes a first capacitor. The inverter allows for wide voltage output swing performance and low power consumption.
摘要翻译：公开了一种逆变器。所公开的逆变器包括第一，第二，第三和第四晶体管，其中第一，第二，第三和第四晶体管中的每一个是P型薄膜晶体管。逆变器还包括第一电容器。逆变器允许宽电压输出摆幅性能和低功耗。

102. 发明授权

US09300278B2 Method and apparatus for calibrating CMOS inverter 有权
标题翻译：校准CMOS反相器的方法和装置
公开(公告)号：US09300278B2
公开(公告)日：2016-03-29
申请号：US14450335
申请日：2014-08-04
申请人： Realtek Semiconductor Corp.
发明人： Chia-Liang (Leon) Lin
IPC分类号： H03K3/02 , H03K3/037 , H03K3/356
CPC分类号： H03K3/0375 , H03K3/037 , H03K3/356104 , H03K19/0027
摘要： A circuit and method for calibrating CMOS (complementary metal-oxide semiconductor) inverters are provided. In a circuit, a first tunable CMOS inverter, controlled by a control signal, receives a first voltage from a first circuit node and outputs a second voltage to a second circuit node. A second tunable CMOS inverter, controlled by the control signal, receives the second voltage from the second circuit node and outputs the first voltage to the first circuit node. A resistor couples the first circuit node to the second circuit node. A switch, controlled by a reset signal, conditionally shorts the first circuit node to the second circuit node. A finite state machine receives the first voltage and the second voltage and outputs the reset signal and the control signal, wherein the control signal is adjusted based on a difference between the first voltage and the second voltage.
摘要翻译：提供了用于校准CMOS（互补金属氧化物半导体）逆变器的电路和方法。在电路中，由控制信号控制的第一可调CMOS反相器从第一电路节点接收第一电压，并向第二电路节点输出第二电压。由控制信号控制的第二可调CMOS反相器从第二电路节点接收第二电压，并将第一电压输出到第一电路节点。电阻器将第一电路节点耦合到第二电路节点。由复位信号控制的开关有条件地将第一电路节点短路到第二电路节点。有限状态机接收第一电压和第二电压并输出复位信号和控制信号，其中基于第一电压和第二电压之间的差来调整控制信号。

103. 发明申请

US20160065187A1 MULTI-LEVEL PULSE GENERATOR CIRCUITRY 有权
标题翻译：多级脉冲发生器电路
公开(公告)号：US20160065187A1
公开(公告)日：2016-03-03
申请号：US14836413
申请日：2015-08-26
申请人： International Rectifier Corporation
发明人： Aswath Krishnan Krishnamoorthy , Anthony B. Candage
IPC分类号： H03K3/356 , H03K5/1532
CPC分类号： H03K3/013 , H03K3/35613 , H03K5/003 , H03K5/1532 , H03K19/0027 , H03K19/00361
摘要： During operation, a supply voltage and the reference voltage power a novel multi-level pulse generator circuit. The multi-level pulse generator circuit generates voltage pulses of varying magnitude from a respective output port. For example, the multi-level pulse generator circuit produces respective pulses to have magnitudes that fall inside and outside of a range defined by the supply voltage and the reference voltage. Expansion of the pulse magnitudes to be outside of the range as defined by the supply voltage and the reference voltage increases noise immunity and therefore enables a respective transmitter to transmit data at higher bandwidth. The multi-level pulse generator circuit can be fabricated using a set of multiple transistors of only a single type in which each of the multiple transistors in the set has a corresponding oxide breakdown voltage that is substantially less than the respective magnitude that falls outside of the range.
摘要翻译：在运行期间，电源电压和参考电压供电一个新颖的多电平脉冲发生器电路。多电平脉冲发生器电路从相应的输出端口产生不同幅度的电压脉冲。例如，多电平脉冲发生器电路产生各自的脉冲，其大小落在由电源电压和参考电压限定的范围内部和外部。脉冲幅度的扩大超出由电源电压和参考电压定义的范围，可以增加抗噪声能力，从而能使各个发射机以更高的带宽传输数据。多级脉冲发生器电路可以使用仅一种类型的多个晶体管的集合来制造，其中该组中的多个晶体管中的每个晶体管具有相应的氧化物击穿电压，其大大小于落在范围。

104. 发明申请

US20160011620A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING BULK BIAS CONTROL FUNCTION AND METHOD OF DRIVING THE SAME 有权
标题翻译：具有大容量偏差控制功能的半导体集成电路装置及其驱动方法
公开(公告)号：US20160011620A1
公开(公告)日：2016-01-14
申请号：US14514027
申请日：2014-10-14
申请人： SK hynix Inc.
发明人： Yeon Uk KIM
IPC分类号： G05F3/02 , H03K3/012
CPC分类号： G05F3/02 , H03K19/0013 , H03K19/0027 , H03K19/00361
摘要： A semiconductor integrated circuit device having a bulk bias control function is provided. The semiconductor integrated circuit device may be configured to output the first external voltage as a bulk voltage of a transistor in a power-up period, and to output a second external voltage having a higher level than the first external voltage as the bulk voltage of the transistor in a power-down mode.
摘要翻译：提供具有体积偏置控制功能的半导体集成电路器件。半导体集成电路器件可以被配置为在上电周期中输出作为晶体管的体电压的第一外部电压，并且输出具有比第一外部电压高的电平的第二外部电压作为晶体管处于掉电模式。

105. 发明授权

US09020456B2 Ultra-low-power radio for short-range communication 有权
标题翻译：用于短距离通信的超低功率无线电
公开(公告)号：US09020456B2
公开(公告)日：2015-04-28
申请号：US13915749
申请日：2013-06-12
申请人： The Regents of the University of Michigan
发明人： David D. Wentzloff , Nathan E. Roberts
IPC分类号： H04B1/06 , H04B7/00 , H04B1/16
CPC分类号： H04B1/1615 , H03K19/0016 , H03K19/0027 , H04W52/0225 , Y02D70/144 , Y02D70/162
摘要： A wake-up function is provided for a low power radio. The radio includes: an antenna, a rectifier, and a comparator. The rectifier is configured to receive an RF signal from the antenna and generates an output having a magnitude that decreases in the presence of the RF signal. The comparator compares the output from the rectifier to a reference signal and outputs an activation signal for another radio component. In response the activation signal, the radio component will transition from a low power consumption mode to a higher power consumption mode. In this way, the rectifier and comparator cooperatively operate to perform a wake-up function in the presence of an RF signal.
摘要翻译：为低功率无线电提供唤醒功能。收音机包括：天线，整流器和比较器。整流器被配置为从天线接收RF信号，并产生具有在存在RF信号时减小的幅度的输出。比较器将整流器的输出与参考信号进行比较，并输出另一个无线电组件的激活信号。响应于激活信号，无线电部件将从低功耗模式转换到较高功耗模式。以这种方式，整流器和比较器协作地操作以在存在RF信号的情况下执行唤醒功能。

106. 发明授权

US08816723B1 Buffer circuit 有权
标题翻译：缓冲电路
公开(公告)号：US08816723B1
公开(公告)日：2014-08-26
申请号：US13959984
申请日：2013-08-06
申请人： Kabushiki Kaisha Toshiba
发明人： Kosuke Yanagidaira
IPC分类号： H03K5/22
CPC分类号： G05F3/16 , G11C7/1084 , H03K19/0027
摘要： A buffer circuit includes a first current mirror circuit, a second current mirror circuit, a first transistor, and a second transistor. The first current mirror circuit passes a first mirror current through a second node, corresponding to a first current passed through a first node, and is activated based on a first activating signal. The second current mirror circuit is connected to the first node and the second node, passes a second mirror current through the second node, corresponding to a second current passed through the first node, and is activated based on a second activating signal. The first transistor has a gate to which a reference voltage is applied and has a drain connected to the first node. The second transistor has a gate to which an input voltage is applied and has a drain connected to the second node.
摘要翻译：缓冲电路包括第一电流镜电路，第二电流镜电路，第一晶体管和第二晶体管。第一电流镜电路将第一镜像电流通过第二节点，对应于通过第一节点的第一电流，并且基于第一激活信号被激活。第二电流镜电路连接到第一节点和第二节点，通过第二镜像电流通过第二节点，对应于通过第一节点的第二电流，并且基于第二激活信号被激活。第一晶体管具有施加参考电压的栅极，并且漏极连接到第一节点。第二晶体管具有施加输入电压的栅极，并且漏极连接到第二节点。

107. 发明申请

US20140145919A1 INVERTER, AMOLDED COMPENSATION CIRCUIT AND DISPLAY PANEL 有权
标题翻译：逆变器，补偿补偿电路和显示面板
公开(公告)号：US20140145919A1
公开(公告)日：2014-05-29
申请号：US14062726
申请日：2013-10-24
申请人： Shanghai Tianma Micro-Electronics Co., Ltd.
发明人： Dong QIAN
IPC分类号： G09G3/32 , H03K3/012
CPC分类号： G09G3/3225 , H03K3/012 , H03K19/0016 , H03K19/0027
摘要： An inverter is disclosed. The disclosed inverter includes first, second, third, and fourth transistors, where each of the first, second, third, and fourth transistors is a P-type thin film transistor. The inverter also includes a first capacitor. The inverter allows for wide voltage output swing performance and low power consumption.
摘要翻译：公开了一种逆变器。所公开的逆变器包括第一，第二，第三和第四晶体管，其中第一，第二，第三和第四晶体管中的每一个是P型薄膜晶体管。逆变器还包括第一电容器。逆变器允许宽电压输出摆幅性能和低功耗。

108. 发明申请

US20140002144A1 SEMICONDUCTOR DEVICE WITH BUFFER AND REPLICA CIRCUITS 有权
标题翻译：具有缓冲器和备用电路的半导体器件
公开(公告)号：US20140002144A1
公开(公告)日：2014-01-02
申请号：US14018784
申请日：2013-09-05
申请人： Elpida Memory, Inc.
发明人： Toru HATAKEYAMA , Toru Ishikawa
IPC分类号： H03K19/00
CPC分类号： H03K19/0027 , G11C5/06 , G11C7/1087
摘要： A semiconductor device includes a first input buffer adjusting a logic threshold voltage, a first replica circuit, a first reference voltage generating circuit, and a first comparator circuit. The first replica circuit is identical in circuit configuration to the first input buffer. The first replica circuit has an input and an output connected to the input. The first replica circuit generates the logic threshold voltage as an output voltage. The first reference voltage generating circuit generates a first reference voltage. The first comparator circuit compares the logic threshold voltage as an output voltage of the first replica circuit to the first reference voltage to generate a first threshold adjustment signal. The first comparator circuit supplies the first threshold adjustment signal to the first input buffer and the first replica circuit. The first threshold adjustment signal allows the first input buffer to adjust the logic threshold voltage.
摘要翻译：半导体器件包括调整逻辑阈值电压的第一输入缓冲器，第一复制电路，第一参考电压产生电路和第一比较器电路。第一复制电路在电路配置与第一输入缓冲器相同。第一个复制电路具有连接到输入的输入和输出。第一个复制电路产生逻辑阈值电压作为输出电压。第一参考电压产生电路产生第一参考电压。第一比较器电路将逻辑阈值电压作为第一复制电路的输出电压与第一参考电压进行比较，以产生第一阈值调整信号。第一比较器电路将第一阈值调整信号提供给第一输入缓冲器和第一复制电路。第一阈值调整信号允许第一输入缓冲器调整逻辑阈值电压。

109. 发明授权

US08502566B2 Adjustable input receiver for low power high speed interface 有权
标题翻译：可调输入接收器，用于低功率高速接口
公开(公告)号：US08502566B2
公开(公告)日：2013-08-06
申请号：US12125760
申请日：2008-05-22
申请人： Chang Ki Kwon
发明人： Chang Ki Kwon
IPC分类号： H03K5/24
CPC分类号： H03K19/0027 , H03K19/018528 , H03K19/018585
摘要： A pseudo-differential input receiver is disclosed which is configured to support a wide-range of reference voltage Vref and a wide-range frequency interface with no parallel termination are described herein. The pseudo-differential receiver implementations described herein are very efficient in terms of area, power, and performance. A wide-frequency-range Vref-adjustable input receiver is described herein. The receiver can be configured with a Vref-monitoring PMOS helper FET or an enabled stacked PMOS helper FET to enable the receiver to work at Vref=0V like a conventional CMOS receiver. The receiver can also be configured with a Vref-monitoring NMOS helper FET to enable a Vref-based input receiver to work with programmability on bias currents & trip-point at Vref=(0.5˜0.7)Vdd, depending on the ratio of output driver's impedance and parallel on/off-die termination impedance.
摘要翻译：公开了一种伪差分输入接收机，其被配置为支持宽范围的参考电压Vref，并且在此描述了没有并行终端的宽范围频率接口。这里描述的伪差分接收机实现在面积，功率和性能方面是非常有效的。本文描述了宽频范围Vref可调输入接收机。接收器可以配置有Vref监控PMOS辅助FET或启用堆叠的PMOS辅助FET，以使接收器能像以前的CMOS接收器一样工作在Vref = 0V。接收器还可以配置有Vref监控NMOS辅助FET，以使基于Vref的输入接收器能够在Vref =（0.5〜0.7）Vdd的偏置电流和跳变点上进行可编程性处理，具体取决于输出驱动器阻抗和并联开/关断开端子阻抗。

110. 发明申请

US20120068750A1 SWITCHING CIRCUITS, LATCHES AND METHODS 有权
标题翻译：切换电路，锁存器和方法
公开(公告)号：US20120068750A1
公开(公告)日：2012-03-22
申请号：US12887074
申请日：2010-09-21
申请人： John McCoy
发明人： John McCoy
IPC分类号： H03K3/00 , H03K17/30 , H03K17/16
CPC分类号： H03K3/0375 , H03K19/0027 , H03K19/01721
摘要： Switching circuits, latches and methods are provided, such as those that may respond to an input signal that transitions from a first binary level to a second binary level. One such switching circuit may have a metastable state that is closer to a first voltage corresponding to the first binary level than it is to a second voltage corresponding to the second binary level. In other embodiments, the metastable state may be dynamically adjustable so that it is at one voltage before the circuit switches and at a different voltage after the circuit switches. As a result, the switching circuit may respond relatively quickly to the input signal transitioning from the first binary level to the second binary level.
摘要翻译：提供了开关电路，锁存器和方法，例如可以响应从第一二进制电平转换到第二二进制电平的输入信号的开关电路，锁存器和方法。一个这样的开关电路可以具有比它对应于第二二进制电平的第二电压更接近对应于第一二进制电平的第一电压的亚稳态。在其他实施例中，亚稳态可以是动态可调节的，使得它在电路切换之前处于一个电压，并且在电路切换之后处于不同的电压。结果，开关电路可以相对快速地响应于从第一二进制电平转换到第二二进制电平的输入信号。

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