专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

101. 发明授权

US11984500B2 Structure and method of new power MOS and IGBT with built-in multiple VT'S 有权
公开(公告)号：US11984500B2
公开(公告)日：2024-05-14
申请号：US17527035
申请日：2021-11-15
申请人： SiEn (QingDao) Integrated Circuits Co., Ltd.
发明人： Min-Hwa Chi , Dongyang Zhou , Jinpeng Qiu , Peng Li , Conghui Liu
IPC分类号： H01L29/78 , H01L29/66 , H01L29/739 , G11C11/56 , H03K19/00
CPC分类号： H01L29/7813 , H01L29/66348 , H01L29/66734 , H01L29/7397 , G11C11/56 , H03K19/0027
摘要： The invention provides a multi-Vt vertical power device and a method of making the same. Through patterning a contact mask, a contact structure array having a shared trench gate structure may be formed, and different traversal gaps between an edge of a contact portion of a second conductivity type and an edge of a trench may be formed in the contact structure array. As such, multi-Vt vertical states may be implemented for storing information. The present invention allows making a multi-Vt vertical power device having different Vt's to be capable to store information without additional process steps. Therefore, with respect to the present invention, the process is simple, cost is low, and application field is wide; number of Vt varies to store multi-bit digital information or analog information in the power device; the built-in multi-Vt power MOSFET and IGBT are adapted not only for the high power applications but also for information storage.

102. 发明公开

US20230170903A1 DIGITAL BUFFER DEVICE WITH SELF-CALIBRATION 审中-公开
公开(公告)号：US20230170903A1
公开(公告)日：2023-06-01
申请号：US17535725
申请日：2021-11-26
申请人： ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.
发明人： SHU-HAN NIEN
IPC分类号： H03K19/003 , H03K19/00
CPC分类号： H03K19/00384 , H03K19/0027 , G11C7/1084
摘要： A digital buffer device with self-calibration includes a first buffer circuit, detection circuit, and calibration circuit. The first buffer circuit has a buffer input terminal for receiving an input signal and a buffer output terminal as output of the digital buffer device. The detection circuit includes at least one second buffer circuit for receiving at least one reference signal and generating at least one detection signal to indicate circuit characteristic variations of the at least one second buffer circuit. The at least one second buffer circuit is of a same type of buffer as the first buffer circuit. The calibration circuit has a calibration input terminal for receiving the input signal, and a calibration output terminal coupled to the buffer output terminal. The calibration circuit is for calibrating the first buffer circuit to generate an output signal according to the input signal and the at least one detection signal.

103. 发明申请

US20180278810A1 IMAGE SENSOR PRECHARGE BOOST 审中-公开
公开(公告)号：US20180278810A1
公开(公告)日：2018-09-27
申请号：US15469812
申请日：2017-03-27
申请人： OMNIVISION TECHNOLOGIES, INC.
发明人： Eric A. G. Webster
IPC分类号： H04N3/14 , H04N5/355 , H03K19/00
CPC分类号： H04N3/1568 , H03K19/0027 , H04N3/1506 , H04N3/1518 , H04N3/1525 , H04N5/3559 , H04N5/3597
摘要： Image sensors with precharge boost are disclosed herein. An example image sensor may include pixels that each include a photodiode to receive image light and produce image charge in response, a floating diffusion to receive the image charge, a transfer gate to couple the photodiode to the floating diffusion in response to a transfer control signal, a reset gate to couple a reset voltage to the floating diffusion in response to a reset control signal, and a boost capacitor coupled between the floating diffusion and a boost voltage source, wherein, during a precharge operation, the boost voltage is provided to the boost capacitor for a portion of time the transfer gate is enabled and while the reset gate is disabled.

104. 发明授权

US09628053B2 Multi-level pulse generator circuitry 有权
公开(公告)号：US09628053B2
公开(公告)日：2017-04-18
申请号：US14836413
申请日：2015-08-26
申请人： International Rectifier Corporation
发明人： Aswath Krishnan Krishnamoorthy , Anthony B. Candage
IPC分类号： H03K3/013 , H03K5/153 , H03K5/1532 , H03K3/356 , H03K5/003 , H03K19/00 , H03K19/003
CPC分类号： H03K3/013 , H03K3/35613 , H03K5/003 , H03K5/1532 , H03K19/0027 , H03K19/00361
摘要： During operation, a supply voltage and the reference voltage power a novel multi-level pulse generator circuit. The multi-level pulse generator circuit generates voltage pulses of varying magnitude from a respective output port. For example, the multi-level pulse generator circuit produces respective pulses to have magnitudes that fall inside and outside of a range defined by the supply voltage and the reference voltage. Expansion of the pulse magnitudes to be outside of the range as defined by the supply voltage and the reference voltage increases noise immunity and therefore enables a respective transmitter to transmit data at higher bandwidth. The multi-level pulse generator circuit can be fabricated using a set of multiple transistors of only a single type in which each of the multiple transistors in the set has a corresponding oxide breakdown voltage that is substantially less than the respective magnitude that falls outside of the range.

105. 发明申请

US20160269027A1 Output Buffer with Offset Cancellation Structure and Offset Cancellation Method Using the Same 有权
标题翻译：具有偏移消除结构的输出缓冲器和使用其的偏移消除方法
公开(公告)号：US20160269027A1
公开(公告)日：2016-09-15
申请号：US14642779
申请日：2015-03-10
申请人： Sitronix Technology Corp.
发明人： Ming-Wei Hsu , Chern-Lin Chen
IPC分类号： H03K19/00 , H03F1/02 , H03F3/45 , G09G3/36
CPC分类号： H03K19/0027 , G09G3/3688 , G09G2310/0291 , H03F3/3022 , H03F3/3023 , H03F3/45183 , H03F3/45192 , H03F3/45246 , H03F3/45475 , H03F3/45744 , H03F3/45968 , H03F2203/45212
摘要： An output buffer with an offset cancellation structure for an LCD source driver includes an operational amplifier, for driving an output signal of the output buffer according to a data signal from a data input terminal of the output buffer; a reference voltage generator, for generating a reference voltage and inputting the reference voltage to the operational amplifier; and a sampling capacitor, coupled between a second input terminal of the operational amplifier and the data input terminal of the output buffer in a first phase, and coupled between the second input terminal of the operational amplifier and an output terminal of the operational amplifier in a second phase, wherein the second input terminal of the operational amplifier is further coupled to the output terminal of the operational amplifier in the first phase. The output signal outputs the data signal where the offset voltage is cancelled in the second phase.
摘要翻译：具有用于LCD源驱动器的偏移消除结构的输出缓冲器包括运算放大器，用于根据来自输出缓冲器的数据输入端的数据信号来驱动输出缓冲器的输出信号; 参考电压发生器，用于产生参考电压并将所述参考电压输入到所述运算放大器; 以及采样电容器，其以第一相耦合在所述运算放大器的第二输入端和所述输出缓冲器的数据输入端之间，并且耦合在所述运算放大器的第二输入端和所述运算放大器的输出端之间第二相，其中运算放大器的第二输入端在第一阶段进一步耦合到运算放大器的输出端。输出信号输出在第二阶段取消偏移电压的数据信号。

106. 发明授权

US09417647B2 Semiconductor integrated circuit device having bulk bias control function and method of driving the same 有权
标题翻译：具有体积偏置控制功能的半导体集成电路器件及其驱动方法
公开(公告)号：US09417647B2
公开(公告)日：2016-08-16
申请号：US14514027
申请日：2014-10-14
申请人： SK hynix Inc.
发明人： Yeon Uk Kim
IPC分类号： G05F3/02 , H03K19/00 , H03K19/003
CPC分类号： G05F3/02 , H03K19/0013 , H03K19/0027 , H03K19/00361
摘要： A semiconductor integrated circuit device having a bulk bias control function is provided. The semiconductor integrated circuit device may be configured to output the first external voltage as a bulk voltage of a transistor in a power-up period, and to output a second external voltage having a higher level than the first external voltage as the bulk voltage of the transistor in a power-down mode.
摘要翻译：提供具有体积偏置控制功能的半导体集成电路器件。半导体集成电路器件可以被配置为在上电周期中输出作为晶体管的体电压的第一外部电压，并且输出具有比第一外部电压高的电平的第二外部电压作为晶体管处于掉电模式。

107. 发明授权

US09311849B2 Inverter, AMOLED compensation circuit and display panel 有权
标题翻译：变频器，AMOLED补偿电路和显示面板
公开(公告)号：US09311849B2
公开(公告)日：2016-04-12
申请号：US14062726
申请日：2013-10-24
申请人： Shanghai Tianma Micro-Electronics Co., Ltd.
发明人： Dong Qian
IPC分类号： G09G3/32 , H03K19/00 , H03K3/012
CPC分类号： G09G3/3225 , H03K3/012 , H03K19/0016 , H03K19/0027
摘要： An inverter is disclosed. The disclosed inverter includes first, second, third, and fourth transistors, where each of the first, second, third, and fourth transistors is a P-type thin film transistor. The inverter also includes a first capacitor. The inverter allows for wide voltage output swing performance and low power consumption.
摘要翻译：公开了一种逆变器。所公开的逆变器包括第一，第二，第三和第四晶体管，其中第一，第二，第三和第四晶体管中的每一个是P型薄膜晶体管。逆变器还包括第一电容器。逆变器允许宽电压输出摆幅性能和低功耗。

108. 发明授权

US09300278B2 Method and apparatus for calibrating CMOS inverter 有权
标题翻译：校准CMOS反相器的方法和装置
公开(公告)号：US09300278B2
公开(公告)日：2016-03-29
申请号：US14450335
申请日：2014-08-04
申请人： Realtek Semiconductor Corp.
发明人： Chia-Liang (Leon) Lin
IPC分类号： H03K3/02 , H03K3/037 , H03K3/356
CPC分类号： H03K3/0375 , H03K3/037 , H03K3/356104 , H03K19/0027
摘要： A circuit and method for calibrating CMOS (complementary metal-oxide semiconductor) inverters are provided. In a circuit, a first tunable CMOS inverter, controlled by a control signal, receives a first voltage from a first circuit node and outputs a second voltage to a second circuit node. A second tunable CMOS inverter, controlled by the control signal, receives the second voltage from the second circuit node and outputs the first voltage to the first circuit node. A resistor couples the first circuit node to the second circuit node. A switch, controlled by a reset signal, conditionally shorts the first circuit node to the second circuit node. A finite state machine receives the first voltage and the second voltage and outputs the reset signal and the control signal, wherein the control signal is adjusted based on a difference between the first voltage and the second voltage.
摘要翻译：提供了用于校准CMOS（互补金属氧化物半导体）逆变器的电路和方法。在电路中，由控制信号控制的第一可调CMOS反相器从第一电路节点接收第一电压，并向第二电路节点输出第二电压。由控制信号控制的第二可调CMOS反相器从第二电路节点接收第二电压，并将第一电压输出到第一电路节点。电阻器将第一电路节点耦合到第二电路节点。由复位信号控制的开关有条件地将第一电路节点短路到第二电路节点。有限状态机接收第一电压和第二电压并输出复位信号和控制信号，其中基于第一电压和第二电压之间的差来调整控制信号。

109. 发明申请

US20160065187A1 MULTI-LEVEL PULSE GENERATOR CIRCUITRY 有权
标题翻译：多级脉冲发生器电路
公开(公告)号：US20160065187A1
公开(公告)日：2016-03-03
申请号：US14836413
申请日：2015-08-26
申请人： International Rectifier Corporation
发明人： Aswath Krishnan Krishnamoorthy , Anthony B. Candage
IPC分类号： H03K3/356 , H03K5/1532
CPC分类号： H03K3/013 , H03K3/35613 , H03K5/003 , H03K5/1532 , H03K19/0027 , H03K19/00361
摘要： During operation, a supply voltage and the reference voltage power a novel multi-level pulse generator circuit. The multi-level pulse generator circuit generates voltage pulses of varying magnitude from a respective output port. For example, the multi-level pulse generator circuit produces respective pulses to have magnitudes that fall inside and outside of a range defined by the supply voltage and the reference voltage. Expansion of the pulse magnitudes to be outside of the range as defined by the supply voltage and the reference voltage increases noise immunity and therefore enables a respective transmitter to transmit data at higher bandwidth. The multi-level pulse generator circuit can be fabricated using a set of multiple transistors of only a single type in which each of the multiple transistors in the set has a corresponding oxide breakdown voltage that is substantially less than the respective magnitude that falls outside of the range.
摘要翻译：在运行期间，电源电压和参考电压供电一个新颖的多电平脉冲发生器电路。多电平脉冲发生器电路从相应的输出端口产生不同幅度的电压脉冲。例如，多电平脉冲发生器电路产生各自的脉冲，其大小落在由电源电压和参考电压限定的范围内部和外部。脉冲幅度的扩大超出由电源电压和参考电压定义的范围，可以增加抗噪声能力，从而能使各个发射机以更高的带宽传输数据。多级脉冲发生器电路可以使用仅一种类型的多个晶体管的集合来制造，其中该组中的多个晶体管中的每个晶体管具有相应的氧化物击穿电压，其大大小于落在范围。

110. 发明申请

US20160011620A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING BULK BIAS CONTROL FUNCTION AND METHOD OF DRIVING THE SAME 有权
标题翻译：具有大容量偏差控制功能的半导体集成电路装置及其驱动方法
公开(公告)号：US20160011620A1
公开(公告)日：2016-01-14
申请号：US14514027
申请日：2014-10-14
申请人： SK hynix Inc.
发明人： Yeon Uk KIM
IPC分类号： G05F3/02 , H03K3/012
CPC分类号： G05F3/02 , H03K19/0013 , H03K19/0027 , H03K19/00361
摘要： A semiconductor integrated circuit device having a bulk bias control function is provided. The semiconductor integrated circuit device may be configured to output the first external voltage as a bulk voltage of a transistor in a power-up period, and to output a second external voltage having a higher level than the first external voltage as the bulk voltage of the transistor in a power-down mode.
摘要翻译：提供具有体积偏置控制功能的半导体集成电路器件。半导体集成电路器件可以被配置为在上电周期中输出作为晶体管的体电压的第一外部电压，并且输出具有比第一外部电压高的电平的第二外部电压作为晶体管处于掉电模式。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式