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101. 发明授权

US4004280A Calculator data storage system 失效
标题翻译：计算器数据存储系统
公开(公告)号：US4004280A
公开(公告)日：1977-01-18
申请号：US593594
申请日：1975-07-07
申请人： Jerry L. Vandierendonck
发明人： Jerry L. Vandierendonck
IPC分类号： G06F9/30 , G06F13/42 , G06F15/78 , G06F13/00
CPC分类号： G06F9/30141 , G06F13/4243 , G06F15/7864 , G06F9/30138
摘要： Disclosed is an expandable calculator system of the type implemented on semiconductor chips providing additional data storage registers for increasing data storage capacity of the basic system. A basic calculator system comprising two semiconductor chips is provided with additional semiconductor chips each providing a plurality of separately addressable registers for storing data, to thereby increase the data storage capacity of the two-chip system. First and second control signals synchronize the internal timing of the external register chips and also enable communication to the external chips. The data system has 10 registers on each of the additional semiconductor chips which are addressed by means responsive to instructions communicated via the data transmission path.
摘要翻译：公开了一种在半导体芯片上实现的可扩展计算器系统，其提供用于增加基本系统的数据存储容量的附加数据存储寄存器。包括两个半导体芯片的基本计算器系统设置有附加的半导体芯片，每个半导体芯片提供多个用于存储数据的单独可寻址的寄存器，从而增加双芯片系统的数据存储容量。第一和第二控制信号同步外部寄存器芯片的内部定时，并且还能够与外部芯片通信。数据系统在每个附加半导体芯片上具有10个寄存器，这些寄存器通过响应于经由数据传输路径传送的指令的方式寻址。

102. 发明授权

US3017094A Order control arrangements for electronic digital computers 失效
标题翻译：电子数字电脑的订单控制安排
公开(公告)号：US3017094A
公开(公告)日：1962-01-16
申请号：US56083156
申请日：1956-01-23
申请人： IBM
发明人： CHRISTOPHER STRACHEY , BRUCE GILLIES DONALD
IPC分类号： G06F9/30 , G06F9/355
CPC分类号： G06F9/355 , G06F9/30 , G06F9/30141

103. 发明申请

US20190035452A1 System, Apparatus And Method For Segmenting A Memory Array 审中-公开
公开(公告)号：US20190035452A1
公开(公告)日：2019-01-31
申请号：US16054207
申请日：2018-08-03
申请人： Intel Corporation
发明人： Bhushan M. Borole , Iqbal R. Rajwani , Anupama A. Thaploo , Sunil Nekkanti , Altug Koker , Abhisek R. Appu
IPC分类号： G11C11/4094 , G06F3/06 , G11C11/4093 , G06F13/40 , G06F9/38 , G11C11/4074
CPC分类号： G11C11/4094 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G06F9/30123 , G06F9/30141 , G06F9/3851 , G06F9/3867 , G06F9/3887 , G06F12/0868 , G06F12/0897 , G06F12/1027 , G06F12/109 , G06F13/4068 , G11C11/4074 , G11C11/4093 , G11C11/419 , Y02D10/14 , Y02D10/151
摘要： In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.

104. 发明申请

US20190004564A1 METHOD FOR CYCLE ACCURATE DATA TRANSFER IN A SKEWED SYNCHRONOUS CLOCK DOMAIN 审中-公开
公开(公告)号：US20190004564A1
公开(公告)日：2019-01-03
申请号：US15573917
申请日：2016-06-14
申请人： GYAN PRAKASH , NIDHIR KUMAR
发明人： GYAN PRAKASH , NIDHIR KUMAR
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F1/04 , G06F5/06 , G06F5/10 , G06F9/30141 , G06F9/3869 , G06F2205/123 , G11C7/10 , G11C7/1093 , G11C7/22 , H03K19/20
摘要： A method and system for cycle accurate data transfer between skewed source synchronous clocks is envisaged. The procedure starts through reset. On reset, both the write and read address registers are set to point to location 0. Source clock is stopped to disable active clock edges to both write and read address registers during the reset procedure. The source clock is subsequently started to deliver active edges w both write and read address registers. On every active source clock edge, data is pushed into the data register based on the location pointed by write address resister. On every skewed active clock edge, data is read from the data register based on the address pointed by read address register. Due to the delayed nature of clock reaching the read address register, write address register increments first and stores data into the data register.

105. 发明申请

US20180336456A1 SPECIAL PURPOSE NEURAL NETWORK TRAINING CHIP 审中-公开
公开(公告)号：US20180336456A1
公开(公告)日：2018-11-22
申请号：US15983056
申请日：2018-05-17
申请人： Google LLC
发明人： Thomas Norrie , Olivier Temam , Andrew Everett Phelps , Norman Paul Jouppi
IPC分类号： G06N3/063 , G06F17/16 , G06N3/08
CPC分类号： G06F9/3887 , G06F9/3001 , G06F9/30032 , G06F9/30036 , G06F9/30141 , G06F9/3885 , G06F15/76 , G06N3/00
摘要： Methods, systems, and apparatus including a special purpose hardware chip for training neural networks are described. The special-purpose hardware chip may include a scalar processor configured to control computational operation of the special-purpose hardware chip. The chip may also include a vector processor configured to have a 2-dimensional array of vector processing units which all execute the same instruction in a single instruction, multiple-data manner and communicate with each other through load and store instructions of the vector processor. The chip may additionally include a matrix multiply unit that is coupled to the vector processor configured to multiply at least one two-dimensional matrix with a second one-dimensional vector or two-dimensional matrix in order to obtain a multiplication result.

106. 发明申请

US20180329711A1 BANKING REGISTER RENAMING TO REDUCE POWER 审中-公开
公开(公告)号：US20180329711A1
公开(公告)日：2018-11-15
申请号：US15657076
申请日：2017-07-21
申请人： Samsung Electronics Co., Ltd.
发明人： Ankit GHIYA
IPC分类号： G06F9/38 , G06F9/30 , G06F1/32
CPC分类号： G06F9/384 , G06F1/3206 , G06F1/3275 , G06F1/3296 , G06F9/30105 , G06F9/30141 , G06F9/3836
摘要： According to one general aspect, an apparatus may include a register circuit and an instruction scheduler circuit. The register circuit may include a plurality of physical registers that are partitioned into at least a common portion that is associated with a predefined plurality of instructions, and a shared portion, and a plurality of write ports, wherein each portion is associated with at least one respective write port. The instruction scheduler circuit configured to determine an instruction, and rename an architectural register associated with the instruction to a physical register. Wherein the portion including the physical register is selected based, at least in part, upon a characteristic of the current instruction.

107. 发明申请

US20180247186A1 NEURAL NETWORK PROCESSING WITH CHAINED INSTRUCTIONS 审中-公开
公开(公告)号：US20180247186A1
公开(公告)日：2018-08-30
申请号：US15637495
申请日：2017-06-29
申请人： Microsoft Technology Licensing, LLC
发明人： Jeremy Fowers , Eric S. Chung , Douglas C. Burger
IPC分类号： G06N3/063 , G06F17/16
CPC分类号： G06F17/16 , G06F9/265 , G06F9/30036 , G06F9/30141 , G06F9/3836 , G06F9/3867 , G06F9/3885 , G06F9/3891 , G06N3/02 , G06N3/04 , G06N3/0445 , G06N3/0454 , G06N3/0481 , G06N3/063 , G06N3/08 , H03K19/17796
摘要： Hardware and methods for neural network processing are provided. A method in a hardware node including a pipeline having a matrix vector unit (MVU), a first multifunction unit connected to receive an input from the matrix vector unit, a second multifunction unit connected to receive an output from the first multifunction unit, and a third multifunction unit connected to receive an output from the second multifunction unit is provided. The method includes performing using the MVU a first type of instruction that can only be performed by the MVU to generate a first result. The method further includes performing a second type of instruction that can only be performed by one of the multifunction units and generating a second result and without storing the any of the two results in a global register, passing the second result to the second multifunction and the third multifunction unit.

108. 发明申请

US20180181405A1 METHOD AND APPARATUS TO CREATE REGISTER WINDOWS FOR PARALLEL ITERATIONS TO ACHIEVE HIGH PERFORMANCE IN HW-SW CODESIGNED LOOP ACCELERATOR 审中-公开
公开(公告)号：US20180181405A1
公开(公告)日：2018-06-28
申请号：US15390194
申请日：2016-12-23
申请人： Intel Corporation
发明人： Jayesh IYER , Sergey P. SCHERBININ , Alexander Y. OSTANEVICH , Dmitry M. MASLENNIKOV , Denis G. MOTIN , Alexander V. ERMOLOVICH , Andrey CHUDNOVETS , Sergey A. ROZHKOV , Boris A. BABAYAN
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3885 , G06F8/445 , G06F8/4452 , G06F8/452 , G06F9/3001 , G06F9/30058 , G06F9/30065 , G06F9/3009 , G06F9/3012 , G06F9/30123 , G06F9/30127 , G06F9/30138 , G06F9/30141 , G06F9/30181 , G06F9/325 , G06F9/381 , G06F9/384 , G06F9/3851
摘要： An apparatus includes a register file and a binary translator to create a plurality of strands and a plurality of iteration windows, where each iteration window of the plurality of iteration windows is allocated a set of continuous registers of the register file. The apparatus further includes a buffer to store strand documentation for a strand from the plurality of strands, where the strand documentation for the strand is to include an indication of a current register base for the strand. The apparatus further includes an execution circuit to execute an instruction to update the current register base for the strand in the strand documentation for the strand based on a fixed step value and an iteration window size.

109. 发明授权

US09910824B2 Vector processor configured to operate on variable length vectors using instructions to combine and split vectors 有权
公开(公告)号：US09910824B2
公开(公告)日：2018-03-06
申请号：US14727076
申请日：2015-06-01
申请人： Optimum Semiconductor Technologies, Inc.
发明人： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
IPC分类号： G06F9/30 , G06F9/38 , G06F15/80 , G06F15/78 , G06F17/14
CPC分类号： G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
摘要： A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more instructions that separate a vector or combine two vectors. The computer processor may be implemented as a monolithic integrated circuit.

110. 发明申请

US20170329741A1 Graphic Processor Unit with Improved Energy Efficiency 审中-公开
公开(公告)号：US20170329741A1
公开(公告)日：2017-11-16
申请号：US15152810
申请日：2016-05-12
申请人： Wisconsin Alumni Research Foundation
发明人： Nam Sung Kim , Zhenhong Liu
IPC分类号： G06F15/78 , G06F9/30 , G06F9/38
CPC分类号： G06F15/7839 , G06F1/3203 , G06F1/3243 , G06F1/3275 , G06F1/3287 , G06F9/30021 , G06F9/30058 , G06F9/30141 , G06F9/3836 , G06F9/3887
摘要： A GPU architecture employs a crossbar switch to preferentially store operand vectors in a compressed form allowing reduction in the number of memory circuits that must be activated during an operand fetch and to allow existing execution units to be used for scalar execution. Scalar execution can be performed during branch divergence.

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