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101. 发明申请

US20140258692A1 DATA PROCESSOR 有权
标题翻译：数据处理器
公开(公告)号：US20140258692A1
公开(公告)日：2014-09-11
申请号：US14284342
申请日：2014-05-21
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Fumio ARAKAWA
IPC分类号： G06F9/30
CPC分类号： G06F9/30185 , G06F9/3001 , G06F9/30029 , G06F9/30058 , G06F9/30094 , G06F9/3016 , G06F9/30181 , G06F9/3865
摘要： A RISC data processor in which the number of flags generated by each instruction is increased so that a decrease of flag-generating instructions exceeds an increase of flag-using instructions in quantity, thereby achieving the decrease in instructions. An instruction for generating flags according to operands' data sizes is defined, and an instruction set handled by the RISC data processor includes an instruction capable of executing an operation on operands in more than one data size. An identical operation process is conducted on the small-size operand and on low-order bits of the large-size operand, and flags are generated capable of coping with the respective data sizes regardless of the data size of each operand subjected to the operation. Thus, a reduction in instruction code space of the RISC data processor can be achieved.
摘要翻译：一个RISC数据处理器，其中由每个指令产生的标志数量增加，使得标志产生指令的减少超过了使用量的指令的增加，从而实现了指令的减少。定义用于根据操作数的数据大小生成标志的指令，并且由RISC数据处理器处理的指令集包括能够对多于一个数据大小的操作数执行操作的指令。对大尺寸操作数的小尺寸操作数和低位进行相同的操作处理，并且生成能够应对各个数据大小的标志，而与经受操作的每个操作数的数据大小无关。因此，可以实现RISC数据处理器的指令代码空间的减少。

102. 发明授权

US08806183B1 Blank bit and processor instructions employing the blank bit 有权
标题翻译：使用空白位的空白位和处理器指令
公开(公告)号：US08806183B1
公开(公告)日：2014-08-12
申请号：US11345803
申请日：2006-02-01
申请人： Gyle D. Yearsley
发明人： Gyle D. Yearsley
IPC分类号： G06F9/32
CPC分类号： G06F9/3001 , G06F9/30007 , G06F9/30018 , G06F9/30021 , G06F9/30043 , G06F9/30058 , G06F9/30094
摘要： Reading a value into a register, checking to see if the value is a NULL, and then jumping out of a loop if the value is a NULL is a common task that processors perform. To speed performance of such a task, a novel “blank bit” is added to the flag register of a processor. When a first instruction (arithmetic, logic or load) is executed, the instruction operands are checked to see if any is a NULL character value. Information on the result of the check is stored in the blank bit. Execution of a second instruction uses the information stored in the blank bit to determine whether or not a second operation (for example, a jump) will be performed. By using the first and second instructions in a loop, the number of instructions executed to check for NULLs at the end of strings and arrays is reduced.
摘要翻译：将值读入寄存器，检查值是否为NULL，然后如果值为NULL，则跳出循环是处理器执行的常见任务。为了加快这种任务的性能，将一个新颖的“空白位”添加到处理器的标志寄存器。当执行第一条指令（算术，逻辑或负载）时，将检查指令操作数，看看是否有NULL字符值。有关检查结果的信息存储在空白位。执行第二指令使用存储在空白位中的信息来确定是否将执行第二操作（例如，跳转）。通过在循环中使用第一个和第二个指令，减少了在字符串和数组结尾处执行以检查NULL的指令数量。

103. 发明申请

US20140173262A1 Energy-Focused Compiler-Assisted Branch Prediction 有权
标题翻译：能量聚焦编译器辅助分支预测
公开(公告)号：US20140173262A1
公开(公告)日：2014-06-19
申请号：US14097879
申请日：2013-12-05
申请人： BlueRISC Inc.
发明人： Saurabh Chheda , Kristopher Carver , Raksit Ashok
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/3846 , G06F9/3848
摘要： A processing system to reduce energy consumption and improve performance in a processor, controlled by compiler inserted information ahead of a selected branch instruction, to statically expose and control how the prediction should be completed and which mechanism should be used to achieve energy and performance efficiency.
摘要翻译：一种处理系统，用于降低处理器的能耗并提高编译器在选定分支指令之前插入的信息的性能，以静态暴露和控制预测应如何完成以及应采用哪种机制来实现能源和性能效率。

104. 发明申请

US20140173261A1 COMPUTER PROCESSOR WITH INSTRUCTION FOR EXECUTION BASED ON AVAILABLE INSTRUCTION SETS 有权
公开(公告)号：US20140173261A1
公开(公告)日：2014-06-19
申请号：US14100058
申请日：2013-12-09
申请人： International Business Machines Corporation
发明人： Jose E. Garza , Stephen J. Hobson
IPC分类号： G06F9/30
CPC分类号： G06F9/38 , G06F9/30058 , G06F9/466 , G06F11/1474 , G06F11/2236
摘要： A system and method for testing whether a computer processor is capable of executing a requested instruction set. The system includes a computer processor configured to receive an encoded conditional branch instruction in a form of machine code executable directly by the computer processor, and implement the encoded conditional branch instruction unconditionally, based on underlying hardware architecture of the computer processor. The Method for testing whether a computer processor is capable of executing a requested instruction set, the method including, receiving an encoded conditional branch instruction in a form of machine code executable directly by the computer processor, and implementing the encoded conditional branch instruction unconditionally, based on underlying hardware architecture of the computer processor.

105. 发明申请

US20140164740A1 Branch-Free Condition Evaluation 有权
标题翻译：无分支状况评估
公开(公告)号：US20140164740A1
公开(公告)日：2014-06-12
申请号：US13710826
申请日：2012-12-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30058 , G06F9/30021 , G06F9/384
摘要： A compare instruction of an instruction set architecture (ISA), when executed tests one or more operands for an instruction defined condition. The result of the test is stored as an operand, with leading zeros, in a general register of the ISA. The general register is identified (explicitly or implicitly) by the compare instruction. Thus, the result of the test can be manipulated by standard register operations of the computer system. In a superscalar processor, no special “condition code” renaming is required, as the standard register renaming takes care of out-of-order processing of the conditions.
摘要翻译：指令集体系结构（ISA）的比较指令在执行时，会针对指令定义的条件测试一个或多个操作数。测试结果作为操作数存储在ISA的通用寄存器中，带有前导零。通用寄存器被比较指令识别（明确地或隐含地）。因此，测试的结果可以通过计算机系统的标准寄存器操作来操纵。在超标量处理器中，不需要特殊的“条件代码”重命名，因为标准寄存器重命名处理条件的无序处理。

106. 发明申请

US20140122836A1 CONFIDENCE-DRIVEN SELECTIVE PREDICATION OF PROCESSOR INSTRUCTIONS 有权
标题翻译：信心指导加工者说明书的选择性预测
公开(公告)号：US20140122836A1
公开(公告)日：2014-05-01
申请号：US13666407
申请日：2012-11-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORA
发明人： Michael Karl Gschwind
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/30058 , G06F9/30072 , G06F9/3017 , G06F9/3802 , G06F9/3844
摘要： An apparatus includes a network interface, memory, and a processor. The processor is coupled with the network interface and memory. The processor is configured to determine that an instruction instance is a branch instruction instance. Responsive to a determination that an instruction instance is a branch instruction instance, the processor is configured to obtain a branch prediction for the branch instruction instance and a confidence value of the branch prediction. The processor is further configured to determine that the confidence for the branch prediction is low based on the confidence value, and responsive to such a determination, generate predicated instruction instances based on the branch instruction instance.
摘要翻译：一种装置包括网络接口，存储器和处理器。处理器与网络接口和存储器耦合。处理器被配置为确定指令实例是分支指令实例。响应于指示实例是分支指令实例的确定，处理器被配置为获得分支指令实例的分支预测和分支预测的置信度值。处理器还被配置为基于置信度值来确定分支预测的置信度，并且响应于这样的确定，基于分支指令实例生成预测指令实例。

107. 发明授权

US08666063B2 Method and apparatus for minimizing differential power attacks on processors 有权
标题翻译：用于最小化处理器的不同功率攻击的方法和装置
公开(公告)号：US08666063B2
公开(公告)日：2014-03-04
申请号：US12837268
申请日：2010-07-15
申请人： Farhad Pezeshki , Robert John Lambert
发明人： Farhad Pezeshki , Robert John Lambert
IPC分类号： H04L9/00
CPC分类号： H04L9/3247 , G06F7/725 , G06F9/30058 , G06F12/1408 , G06F21/52 , G06F21/75 , G06F21/755 , G06F2207/7223 , G06F2207/7242 , G06K19/073 , G06K19/07363 , H04L9/003 , H04L2209/04 , Y02D10/13
摘要： A method of masking a cryptographic operation using a secret value, comprising the steps of dividing the secret value into a plurality of parts; combining with each part a random value to derive a new part such that the new parts when combined are equivalent to the original secret value; and utilizing each of the individual parts in the operation.
摘要翻译：一种使用秘密值掩蔽密码操作的方法，包括以下步骤：将秘密值分割成多个部分; 与每个部分组合一个随机值以导出新的部分，使得当组合的新部分等同于原始秘密值时; 并且在操作中使用每个单独的部件。

108. 发明申请

US20140059332A1 BRANCH TARGET BUFFER FOR EMULATION ENVIRONMENTS 有权
标题翻译：分支目标缓冲区用于模拟环境
公开(公告)号：US20140059332A1
公开(公告)日：2014-02-27
申请号：US14068044
申请日：2013-10-31
申请人： International Business Machines Corporation
发明人： Carlos CAVANNA , Reid COPELAND , Chad MC INTYRE , Ali SHEIKH
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/3848 , G06F9/455 , G06F12/0875 , G06F2212/452
摘要： Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.
摘要翻译：分支指令在正在执行程序的仿真环境中进行管理。填充多形体内联高速缓存中的多个时隙。多个条目填充在驻留在程序正在执行的仿真环境中的分支目标缓冲器中。当遇到与程序相关联的间接分支指令时，从间接分支指令识别与指令相关联的目标地址。将多形态内联高速缓存的每个时隙中的至少一个地址与与间接分支指令相关联的目标地址进行比较。如果多形态内联高速缓存的时隙中的任何地址都不匹配与间接分支指令相关联的目标地址，则搜索分支目标缓冲区以识别与目标地址相关联的分支目标缓冲器中的一个条目间接分支指令。

109. 发明申请

US20140025930A1 MULTI-CORE PROCESSOR SHARING LI CACHE AND METHOD OF OPERATING SAME 审中-公开
标题翻译：多核处理器共享缓存和操作方法
公开(公告)号：US20140025930A1
公开(公告)日：2014-01-23
申请号：US14037543
申请日：2013-09-26
申请人： Samsung Electronics Co., Ltd.
发明人： HOI JIN LEE , NAK HEE SEONG , JAE HONG PARK , KYOUNG MOOK LIM
IPC分类号： G06F9/30
CPC分类号： G06F9/30058 , G06F12/084 , G06F12/0848
摘要： A multi-core processor includes first processor core including a first instruction fetch unit and out-of-order execution data units, a second processor core including a second instruction fetch unit and in-order execution data units, and a shared-level 1 cache including a level 1-instruction cache shared between the first instruction fetch unit and the second instruction fetch unit and a level 1-data cache shared between the out-of-order execution data units and the in-order execution data.
摘要翻译：多核处理器包括第一处理器核心，其包括第一指令提取单元和无序执行数据单元，第二处理器核心，包括第二指令提取单元和按顺序执行数据单元，以及共享级别1缓存包括在第一指令获取单元和第二指令获取单元之间共享的1级指令高速缓存以及无序执行数据单元与顺序执行数据之间共享的1级数据高速缓存。

110. 发明申请

US20130339697A1 BRANCH PREDICTION PRELOADING 有权
标题翻译：分行预测推广
公开(公告)号：US20130339697A1
公开(公告)日：2013-12-19
申请号：US13784888
申请日：2013-03-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： James J. Bonanno , Marcel Mitran , Brian R. Prasky , Joran Siu , Timothy J. Slegel , Alexander Vasilevskiy
IPC分类号： G06F9/30
CPC分类号： G06F9/30058 , G06F9/3806 , G06F9/3844
摘要： Embodiments relate to branch prediction preloading. A method for branch prediction preloading includes fetching a plurality of instructions in an instruction stream, and decoding a branch prediction preload instruction in the instruction stream. The method also includes determining, by a processing circuit, an address of a predicted branch instruction based on the branch prediction preload instruction, and determining, by the processing circuit, a predicted target address of the predicted branch instruction based on the branch prediction preload instruction. The method further includes identifying a mask field in the branch prediction preload instruction, and determining, by the processing circuit, a branch instruction length of the predicted branch instruction based on the mask field. Based on executing the branch prediction preload instruction, a branch target buffer is preloaded with the address of the predicted branch instruction, the branch instruction length, and the predicted target address associated with the predicted branch instruction.
摘要翻译：实施例涉及分支预测预加载。一种用于分支预测预加载的方法包括在指令流中取出多个指令，并对指令流中的分支预测预加载指令进行解码。该方法还包括由处理电路根据分支预测预加载指令确定预测分支指令的地址，并且由处理电路根据分支预测预加载指令确定预测分支指令的预测目标地址。该方法还包括识别分支预测预加载指令中的掩码字段，并且由处理电路根据掩码字段确定预测转移指令的分支指令长度。基于执行分支预测预加载指令，分支目标缓冲器预先加载预测分支指令的地址，分支指令长度以及与预测分支指令相关联的预测目标地址。

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