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101. 发明授权

US4037211A Address extending control unit 失效
标题翻译：地址扩展控制单元
公开(公告)号：US4037211A
公开(公告)日：1977-07-19
申请号：US641812
申请日：1975-12-18
申请人： Hiroaki Ikuta , Yoshikazu Naruke , Yoshio Nagasawa , Masanori Yakushi
发明人： Hiroaki Ikuta , Yoshikazu Naruke , Yoshio Nagasawa , Masanori Yakushi
IPC分类号： G06F9/34 , G06F12/02 , G06F12/06 , G11C8/00
CPC分类号： G06F12/0623
摘要： An address extending control circuit is disclosed which is provided with a memory having a memory capacity larger than that assignable with the content of an address register. The memory area of the memory is divided into a common block and a plurality of segment blocks of variable capacity. In a certain processing, the common block and any one of the segment blocks are utilized in pairs, thereby to obtain an extended address. To this end, an address extending address register capable of selecting a predetermined segment block of the memory is provided in addition to the address register. When the value in the address register is detected to be larger than a predetermined value, the content of the address extending address register corresponding thereto is appended to the content of the address register to increase the number of bits and a combination of the common block with one segment block of the memory is selected, with which an address in the selected segment block is accessed. Thus, address extending can be achieved with a simple construction.
摘要翻译：公开了一种地址扩展控制电路，其具有存储器容量大于可由地址寄存器的内容分配的存储器容量的存储器。存储器的存储区被分成公共块和可变容量的多个段块。在某个处理中，公共块和任何一个段块成对使用，从而获得扩展地址。为此，除了地址寄存器之外，还提供了能够选择存储器的预定段块的地址扩展地址寄存器。当检测到地址寄存器中的值大于预定值时，将与之对应的地址扩展地址寄存器的内容附加到地址寄存器的内容，以增加位数，并将公共块的组合与选择存储器的一个段块，通过该存储器访问所选择的段块中的地址。因此，可以用简单的结构实现地址延伸。

102. 发明授权

US3786436A Memory expansion arrangement in a central processor 失效
标题翻译：中央处理器的内存扩展安排
公开(公告)号：US3786436A
公开(公告)日：1974-01-15
申请号：US3786436D
申请日：1973-03-14
申请人： GTE AUTOMATIC ELECTRIC LAB INC
发明人： ZELINSKI P , JONES L
IPC分类号： G06F9/355 , G06F12/06 , G06F9/20
CPC分类号： G06F9/342 , G06F12/0623
摘要： A page register in the central processor comprises 3N bistable devices, N each for an instruction field, a branch field, and a data field, to extend addresses by N bits beyond the capacity of the operand portion of the format of instructions. A ''''load page register'''' instruction uses the operand to designate load the branch field and/or the data field, or transfer the instruction field to the data field; and also supplies the values for loading the branch and/or data field. A ''''last page reference'''' register is also provided to which the instruction and data fields are transferred from the page register during execution of each instruction, while the address in a program counter is transferred to a ''''last program count'''' register, to be stored in memory when a ''''branch and store program'''' linkage instruction is executed.
摘要翻译：中央处理器中的页寄存器包括3N双稳态器件，N个用于指令字段，分支字段和数据字段，以将地址扩展超过指令格式的操作数部分的容量的N位。 “加载页寄存器”指令使用操作数来指定加载分支字段和/或数据字段，或将指令字段传送到数据字段; 并提供加载分支和/或数据字段的值。还提供了一个“最后一页参考”寄存器，在每个指令的执行期间指令和数据字段从页寄存器传送到该寄存器，而程序计数器中的地址被传送到“最后一个程序计数”寄存器，以被存储在执行“分支和存储程序”链接指令时在内存中。

103. 发明授权

US3761885A Computer system comprising a storage configuration with access prior to ultimate address calculation 失效
标题翻译：包含存储配置的计算机系统在进行最终地址计算之前进行访问
公开(公告)号：US3761885A
公开(公告)日：1973-09-25
申请号：US3761885D
申请日：1972-02-16
申请人： PHILIPS CORP
发明人： DUDOK VAN HEEL J
IPC分类号： G06F12/06 , G11C7/00
CPC分类号： G06F12/0623
摘要： In order to allow a request for access to a given store in a computer system having a storage configuration comprising a number of stores to be made before an ultimate address has been calculated from a number of address components, an unused address space (void) is defined between each store of the configuration and possibly also above the store of the highest order. A result of an address calculation which is situated in a void causes a cancellation of the relevant previously made request for access. It will never be necessary to change a request for access to a given store into a request for access to another store.
摘要翻译：为了允许访问具有存储配置的计算机系统中的给定存储器的请求，该存储配置包括在从多个地址分量计算最终地址之前要进行的多个存储器的存储配置，未使用的地址空间（void）在配置的每个存储之间定义，并且可能还高于最高订单的存储。位于空白处的地址计算的结果导致取消相关的先前提出的访问请求。永远不需要将访问给定商店的请求更改为访问另一个商店的请求。

104. 发明授权

US3238510A Memory organization for data processors 失效
标题翻译：数据处理器的内存组织
公开(公告)号：US3238510A
公开(公告)日：1966-03-01
申请号：US16335561
申请日：1961-12-29
申请人： IBM
发明人： ERGOTT JR HAROLD L
IPC分类号： G06F12/06 , G06F13/00
CPC分类号： G06F13/00 , G06F12/0623

105. 发明公开

US20230205687A1 CONTROLLER AND OPERATING METHOD THEREOF 审中-公开
公开(公告)号：US20230205687A1
公开(公告)日：2023-06-29
申请号：US17741798
申请日：2022-05-11
申请人： SK hynix Inc.
发明人： Jeen PARK
IPC分类号： G06F12/02 , G06F12/06 , G06F13/16
CPC分类号： G06F12/0238 , G06F12/0623 , G06F12/0653 , G06F13/1668 , G06F2212/7201
摘要： The embodiments of the disclosed technology relate to a controller and operating method thereof. Based on some embodiments of the disclosed technology, the controller may include i) a first memory configured to store map data including a plurality of map data entries, ii) a second memory configured to store map search data indicating a first map data entry, which corresponds to a first logical address, among the plurality of map data entries, and iii) a core configured to search for information on a physical address mapped to a second logical address from the map data, based on whether the map search data is stored in the second memory.

106. 发明申请

US20190235938A1 ENHANCED ADDRESS SPACE LAYOUT RANDOMIZATION 审中-公开
公开(公告)号：US20190235938A1
公开(公告)日：2019-08-01
申请号：US16259736
申请日：2019-01-28
申请人： Intel Corporation
发明人： TOMER STARK , RON GABOR , JOSEPH NUZMAN
IPC分类号： G06F11/07 , G06F12/06 , G06F12/14
CPC分类号： G06F11/073 , G06F11/0727 , G06F12/0623 , G06F12/14 , G06F2212/1052 , G06F2212/657
摘要： One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.

107. 发明申请

US20180129428A1 METHOD AND APPARATUS FOR WEAR-LEVELLING NON-VOLATILE MEMORY 审中-公开
公开(公告)号：US20180129428A1
公开(公告)日：2018-05-10
申请号：US15848774
申请日：2017-12-20
申请人： SanDisk Technologies LLC
发明人： Chetan Agrawal , Dinesh Agarwal , Vijay Sivasankaran
IPC分类号： G06F3/06
CPC分类号： G06F3/0616 , G06F3/0628 , G06F3/064 , G06F3/0652 , G06F3/0679 , G06F3/0683 , G06F3/0688 , G06F12/0246 , G06F12/0253 , G06F12/0623 , G11C16/3495
摘要： Apparatus and method for performing wear leveling are disclosed. An ordered list of references to each of a set of memory blocks is stored. A set of memory blocks in the ordered list is sequentially allocating. The allocated set of memory blocks in the ordered list are erased in the sequence in which they were allocated.

108. 发明申请

US20180024753A1 INTERNALLY PRECONDITIONING SOLID STATE DRIVES FOR VARIOUS WORKLOADS 有权
公开(公告)号：US20180024753A1
公开(公告)日：2018-01-25
申请号：US15216541
申请日：2016-07-21
申请人： HGST Netherlands B.V.
发明人： Timothy Glen Hallett , Anton John Neu , Phillip Peterson
IPC分类号： G06F3/06 , G06F12/06
CPC分类号： G06F3/0613 , G06F3/0632 , G06F3/0679 , G06F3/0685 , G06F12/0223 , G06F12/0246 , G06F12/06 , G06F12/0623 , G06F12/0692 , G06F2212/1016 , G06F2212/2022 , G06F2212/7201 , G06F2212/7206 , G06F2212/7208 , G06F2212/7211 , G11C29/028 , G11C29/40 , G11C29/44 , G11C29/52 , G11C2029/4002 , G11C2029/4402
摘要： Systems and methods for internally preconditioning SSDs for various workloads are disclosed. One such method involves (1) receiving preconditioning parameters including an invalidity distribution across ribbons, a transfer size of workloads, and a randomness of workloads, (2) generating workload data including a percentage of random data and a percentage of non-random data, where the percentages are based on the randomness of workloads parameter, (3) determining preselected physical block addresses (PBAs) of a ribbon using the invalidity distribution parameter, (4) writing a portion of the workload data to each of the preselected PBAs of the ribbon using a preselected transfer size until the ribbon is full, where the transfer size is based on the transfer size of workloads parameter, (5) marking all PBAs of the ribbon that were not preselected using the invalidity distribution parameter as being invalid, and (6) repeating (2) to (5) until a preselected end condition is met.

109. 发明授权

US09870319B1 Multibank queuing system 有权
公开(公告)号：US09870319B1
公开(公告)日：2018-01-16
申请号：US15090369
申请日：2016-04-04
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Sharon Ulman , Roi Sherman , Dror Bromberg , Carmi Arad
IPC分类号： H04L12/28 , H04L12/56 , G06F12/06 , G06F7/58 , G06F13/16 , H04L12/879
CPC分类号： G06F12/0623 , G06F7/582 , G06F12/0246 , G06F13/1647 , G06F13/1694 , G06F2212/2532 , G06F2212/261 , H04L49/90 , H04L49/901
摘要： Data items to be stored in a queue are received, where the queue is distributed among a plurality of memory banks. The data items are distributed among the plurality of memory banks, including selecting memory banks in which to store the data items based on pseudorandom numbers generated for the data items, where the pseudorandom numbers are generated using a first pseudorandom number generator initialized with a first seed. Subsequently the data items are retrieved from the plurality of memory banks, including selecting memory banks from which to retrieve the data items based on the pseudorandom numbers regenerated for the data items, where the pseudorandom numbers are regenerated using a second pseudorandom number generator initialized with the first seed.

110. 发明授权

US09870173B2 Apparatus and method for optimized n-write/1-read port memory design 有权
公开(公告)号：US09870173B2
公开(公告)日：2018-01-16
申请号：US15047987
申请日：2016-02-19
申请人： CAVIUM, INC.
发明人： Saurin Patel , Weihuang Wang
IPC分类号： G06F13/00 , G06F3/06 , G06F12/0802 , G06F13/42 , G06F12/127 , G06F12/06 , G06F12/02
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/067 , G06F3/0683 , G06F12/0223 , G06F12/06 , G06F12/0623 , G06F12/0802 , G06F12/0846 , G06F12/0857 , G06F12/127 , G06F13/4256 , G06F13/4273 , G06F13/4291 , G06F2212/1048 , H04L49/00
摘要： An optimized design of n-write/1-read port memory comprises a memory unit including a plurality of memory banks each having one write port and one read port configured to write data to and read data from the memory banks, respectively. The memory further comprises a plurality of write interfaces configured to carry concurrent write requests to the memory unit for a write operation, wherein the first write request is always presented by its write interface directly to a crossbar, wherein the rest of the write requests are each fed through a set of temporary memory modules connected in a sequence before being presented to the crossbar. The crossbar is configured to accept the first write request directly and fetch the rest of the write requests from one of the memory modules in the set and route each of the write requests to one of the memory banks in the memory unit.

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