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101. 发明授权

US07452778B2 Semiconductor nano-wire devices and methods of fabrication 有权
标题翻译：半导体纳米线器件及其制造方法
公开(公告)号：US07452778B2
公开(公告)日：2008-11-18
申请号：US11104348
申请日：2005-04-12
申请人： Hung-Wei Chen , Yee-Chia Yeo , Di-Hong Lee , Fu-Liang Yang , Chenming Hu
发明人： Hung-Wei Chen , Yee-Chia Yeo , Di-Hong Lee , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336
CPC分类号： H01L29/42384 , B82Y10/00 , H01L21/324 , H01L29/0673 , H01L29/42392 , H01L29/66795 , H01L29/7854 , H01L29/78645 , H01L29/78696
摘要： Nano-wires, preferably of less than 20 nm diameter, can be formed with minimized risk of narrowing and breaking that results from silicon atom migration during an annealing process step. This is accomplished by masking portion of the active layer where silicon atomer would otherwise agglomerate with a material such as silicon dioxide, silicon nitride, or other dielectric that eliminates or substantially reduces the silicon atom migration. Nano-wires, nanotubes, nano-rods, and other features can be formed and can optionally be incorporated into devices, such as by use as a channel region in a transistor device.
摘要翻译：可以形成直径小于20nm的纳米线，其最小化是在退火工艺步骤期间硅原子迁移导致的变窄和断裂的风险。这是通过掩蔽有源层的一部分来实现的，其中硅一方面将以诸如二氧化硅，氮化硅或其它电介质的材料聚集，其消除或基本上减少硅原子迁移。可以形成纳米线，纳米管，纳米棒和其它特征，并且可以可选地并入器件中，例如用作晶体管器件中的沟道区。

102. 发明授权

US07262086B2 Contacts to semiconductor fin devices 有权
标题翻译：与半导体鳍片器件接触
公开(公告)号：US07262086B2
公开(公告)日：2007-08-28
申请号：US11478916
申请日：2006-06-30
申请人： Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/339
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66795 , H01L2029/7858 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a contact to a semiconductor fin which can be carried out by first providing a semiconductor fin that has a top surface, two sidewall surfaces and at least one end surface; forming an etch stop layer overlying the fin; forming a passivation layer overlying the etch stop layer; forming a contact hole in the passivation layer exposing the etch stop layer; removing the etch stop layer in the contact hole; and filling the contact hole with an electrically conductive material.
摘要翻译：一种用于形成与半导体鳍片的接触的方法，其可以通过首先提供具有顶表面，两个侧壁表面和至少一个端面的半导体鳍片来实现; 形成覆盖鳍片的蚀刻停止层; 形成覆盖所述蚀刻停止层的钝化层; 在所述钝化层中形成暴露所述蚀刻停止层的接触孔; 去除接触孔中的蚀刻停止层; 并用导电材料填充接触孔。

103. 发明申请

US20060244066A1 Contacts to semiconductor fin devices 有权
公开(公告)号：US20060244066A1
公开(公告)日：2006-11-02
申请号：US11478916
申请日：2006-06-30
申请人： Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66795 , H01L2029/7858 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a contact to a semiconductor fin which can be carried out by first providing a semiconductor fin that has a top surface, two sidewall surfaces and at least one end surface; forming an etch stop layer overlying the fin; forming a passivation layer overlying the etch stop layer; forming a contact hole in the passivation layer exposing the etch stop layer; removing the etch stop layer in the contact hole; and filling the contact hole with an electrically conductive material.

104. 发明申请

US20060226487A1 Resistor with reduced leakage 审中-公开
标题翻译：电阻泄漏减少
公开(公告)号：US20060226487A1
公开(公告)日：2006-10-12
申请号：US11451045
申请日：2006-06-12
申请人： Yee-Chia Yeo , Chenming Hu
发明人： Yee-Chia Yeo , Chenming Hu
IPC分类号： H01L23/62
CPC分类号： H01L27/1203 , H01L28/20
摘要： A resistor 100 is formed in a semiconductor layer 106, e.g., a silicon layer on an SOI substrate. A body region 108 is formed in a portion of the semiconductor layer 106 and is doped to a first conductivity type (e.g., n-type or p-type). A first contact region 110, which is also doped to the first conductivity type, is formed in the semiconductor layer 106 adjacent the body region 108. A second contact region 112 is also formed in the semiconductor layer 106 and is spaced from the first contact region 110 by the body region 108. A dielectric layer 116 overlies the body region and is formed from a material with a relative permittivity greater than about 8. An electrode 114 overlies the dielectric 116.
摘要翻译：电阻器100形成在半导体层106中，例如SOI衬底上的硅层。体区108形成在半导体层106的一部分中并被掺杂到第一导电类型（例如，n型或p型）。第一接触区域110也被掺杂到第一导电类型，形成在邻近主体区域108的半导体层106中。第二接触区域112也形成在半导体层106中并且与第一接触区域电介质层116覆盖在主体区域上，并且由相对介电常数大于约8的材料形成。电极114覆盖电介质116。

105. 发明授权

US07074656B2 Doping of semiconductor fin devices 有权
标题翻译：掺杂半导体鳍片器件
公开(公告)号：US07074656B2
公开(公告)日：2006-07-11
申请号：US10425156
申请日：2003-04-29
申请人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/66803
摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
摘要翻译：半导体结构包括覆盖绝缘体层的多个半导体鳍片，覆盖所述半导体鳍片的一部分的栅极电介质和覆盖栅极电介质的栅电极。每个半导体翅片具有顶表面，第一侧壁表面和第二侧壁表面。掺杂离子相对于半导体鳍片的顶表面的法线以第一角度（例如，大于约7°）注入，以掺杂第一侧壁表面和顶表面。相对于半导体鳍片的顶表面的法线注入另外的掺杂剂离子以掺杂第二侧壁表面和顶表面。

106. 发明申请

US20060124965A1 Capacitor that includes high permittivity capacitor dielectric 有权
标题翻译：包括高介电常数电容器电容器的电容器
公开(公告)号：US20060124965A1
公开(公告)日：2006-06-15
申请号：US11331703
申请日：2006-01-13
申请人： Yee-Chia Yeo , Chenming Hu
发明人： Yee-Chia Yeo , Chenming Hu
IPC分类号： H01L31/109
CPC分类号： H01L27/0805 , H01L21/84 , H01L27/1203 , H01L28/55 , H01L28/65 , H01L29/66181 , H01L29/94 , Y10S257/905 , Y10S257/908
摘要： A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.
摘要翻译：在包括硅表面层的半导体衬底上形成去耦电容器。在半导体表面层的一部分中形成基本平坦的底部电极。电容器电介质覆盖在底部电极上。电容器电介质由具有相对介电常数（优选大于约5）的高介电常数电介质形成。电容器还包括覆盖在电容器电介质上的基本平坦的顶部电极。在优选的应用中，顶部电极连接到第一参考电压线，底部电极连接到第二参考电压线。

107. 发明申请

US20050275024A1 SOI chip with recess-resistant buried insulator and method of manufacturing the same 有权
标题翻译：具有耐凹陷绝缘体的SOI芯片及其制造方法
公开(公告)号：US20050275024A1
公开(公告)日：2005-12-15
申请号：US11207681
申请日：2005-08-19
申请人： Yee-Chia Yeo , Chenming Hu
发明人： Yee-Chia Yeo , Chenming Hu
IPC分类号： H01L21/20 , H01L21/31 , H01L21/762 , H01L21/84 , H01L27/01 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/76254 , H01L21/84
摘要： A semiconductor-on-insulator structure includes a substrate and a buried insulator stack overlying the substrate. The buried insulator stack includes a first dielectric layer and a recess-resistant layer overlying the first dielectric layer. A second dielectric layer can overlie the recess-resistant layer. A semiconductor layer overlying the buried insulator stack. Active devices, such as transistors and diodes, can be formed in the semiconductor layer.
摘要翻译：绝缘体上半导体结构包括衬底和覆盖衬底的掩埋绝缘体堆叠。掩埋绝缘体堆叠包括覆盖第一介电层的第一介电层和凹陷层。第二电介质层可以覆盖在耐凹陷层上。覆盖埋层绝缘体叠层的半导体层。可以在半导体层中形成有源器件，例如晶体管和二极管。

108. 发明申请

US20050248906A1 Capacitor that includes high permittivity capacitor dielectric 有权
标题翻译：包括高介电常数电容器电容器的电容器
公开(公告)号：US20050248906A1
公开(公告)日：2005-11-10
申请号：US11167694
申请日：2005-06-27
申请人： Yee-Chia Yeo , Chenming Hu
发明人： Yee-Chia Yeo , Chenming Hu
IPC分类号： H01G4/228 , H01L21/00 , H01L21/02 , H01L21/334 , H01L21/762 , H01L21/8239 , H01L21/84 , H01L27/00 , H01L27/105 , H01L27/108 , H01L27/12 , H01L29/92 , H01L29/94
CPC分类号： H01L27/0805 , H01L21/84 , H01L27/1203 , H01L28/55 , H01L28/65 , H01L29/66181 , H01L29/94 , Y10S257/905 , Y10S257/908
摘要： A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.
摘要翻译：在包括硅表面层的半导体衬底上形成去耦电容器。在半导体表面层的一部分中形成基本平坦的底部电极。电容器电介质覆盖在底部电极上。电容器电介质由具有相对介电常数（优选大于约5）的高介电常数电介质形成。电容器还包括覆盖在电容器电介质上的基本平坦的顶部电极。在优选的应用中，顶部电极连接到第一参考电压线，底部电极连接到第二参考电压线。

109. 发明授权

US06955952B2 Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement 有权
标题翻译：应变平衡结构具有拉伸应变硅通道和压缩应变硅 - 锗通道，用于CMOS性能提升
公开(公告)号：US06955952B2
公开(公告)日：2005-10-18
申请号：US10383709
申请日：2003-03-07
申请人： Yee-Chia Yeo , Chun-Chieh Lin , Fu-Liang Yang , Mong-Song Liang , Chenming Hu
发明人： Yee-Chia Yeo , Chun-Chieh Lin , Fu-Liang Yang , Mong-Song Liang , Chenming Hu
IPC分类号： H01L21/00 , H01L21/84 , H01L27/12 , H01L31/109
CPC分类号： H01L29/1054 , H01L21/84 , H01L27/1203
摘要： A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile stain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.
摘要翻译：已经开发了通过应变诱导带结构修改来实现NMOS和PMOS元件的迁移率增强的CMOS器件的制造方法。 NMOS元件形成为具有双轴应变下的硅沟道区，同时形成在双轴压缩应变下具有SiGe沟道区的PMOS元件。允许形成覆盖SiGe层的较厚硅层的新颖工艺顺序允许NMOS沟道区存在于双轴拉伸污染增强电子迁移率的硅层中。相同的新工艺序列导致存在较薄的硅层，覆盖PMOS区域中相同的SiGe层，允许PMOS沟道区存在于双轴压缩应变SiGe层中，导致空穴迁移率增强。

110. 发明授权

US06940705B2 Capacitor with enhanced performance and method of manufacture 有权
标题翻译：具有增强性能和制造方法的电容器
公开(公告)号：US06940705B2
公开(公告)日：2005-09-06
申请号：US10627218
申请日：2003-07-25
申请人： Yee-Chia Yeo , Chenming Hu
发明人： Yee-Chia Yeo , Chenming Hu
IPC分类号： H01L21/02 , H01L27/08 , H01L29/94 , H01G4/35
CPC分类号： H01L28/40 , H01L27/0805 , H01L29/94 , H01L2924/0002 , Y10T29/435 , H01L2924/00
摘要： A decoupling capacitor is formed in a semiconductor substrate that includes a strained silicon layer. A substantially flat bottom electrode is formed in a portion of the strained silicon layer and a capacitor dielectric overlying the bottom electrode. A substantially flat top electrode overlies said capacitor dielectric. The top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.
摘要翻译：在包括应变硅层的半导体衬底中形成去耦电容器。基本平坦的底部电极形成在应变硅层的一部分和覆盖底部电极的电容器电介质上。基本平坦的顶部电极覆盖所述电容器电介质。顶部电极连接到第一参考电压线，底部电极连接到第二参考电压线。

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