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101. 发明申请

US20090286344A1 Sensor And Method For Making The Same 失效
标题翻译：传感器及其制作方法
公开(公告)号：US20090286344A1
公开(公告)日：2009-11-19
申请号：US12509603
申请日：2009-07-27
申请人： Theodore I Kamins , Philip J. Kuekes , Carrie L. Donley , Jason J. Blackstock
发明人： Theodore I Kamins , Philip J. Kuekes , Carrie L. Donley , Jason J. Blackstock
IPC分类号： H01L21/04
CPC分类号： B82Y15/00 , G01K7/186 , G01K2211/00 , G01N25/482 , Y10S977/762 , Y10S977/765
摘要： A method of making a sensor comprises substantially laterally growing at least one nanowire having at least two segments between two electrodes, whereby a junction or connection is formed between the at least two segments; and establishing a sensing material adjacent to the junction or connection, and adjacent to at least a portion of each of the at least two segments, wherein the sensing material has at least two states.
摘要翻译：制造传感器的方法包括在两个电极之间基本上横向生长至少一个具有至少两个区段的纳米线，由此在所述至少两个区段之间形成结或连接; 以及建立与所述连接或连接相邻并且与所述至少两个段中的每一个的至少一部分相邻的感测材料，其中所述感测材料具有至少两个状态。

102. 发明授权

US07592679B1 Sensor and method for making the same 有权
标题翻译：传感器和制作方法
公开(公告)号：US07592679B1
公开(公告)日：2009-09-22
申请号：US11583648
申请日：2006-10-19
申请人： Theodore I. Kamins , Philip J. Kuekes , Carrie L. Donley , Jason J. Blackstock
发明人： Theodore I. Kamins , Philip J. Kuekes , Carrie L. Donley , Jason J. Blackstock
IPC分类号： H01L29/78
CPC分类号： B82Y15/00 , G01K7/186 , G01K2211/00 , G01N25/482 , Y10S977/762 , Y10S977/765
摘要： A sensor includes at least two electrodes, and at least one nanowire extending substantially laterally between the electrodes. The at least one nanowire has at least two segments with a junction or connection formed therebetween. A sensing material changeable between at least two states is positioned adjacent to the junction or connection, and adjacent to at least a portion of each of the segments.
摘要翻译：传感器包括至少两个电极和至少一个在电极之间大体上横向延伸的纳米线。至少一个纳米线具有至少两个在其间形成有连接或连接的部分。可在至少两个状态之间改变的传感材料位于邻接于接合处或连接处并且与每个段的至少一部分相邻。

103. 发明授权

US07582975B1 Nanowire device and method of making the same 有权
标题翻译：纳米线装置及其制作方法
公开(公告)号：US07582975B1
公开(公告)日：2009-09-01
申请号：US11741218
申请日：2007-04-27
申请人： Theodore I. Kamins , Philip J. Kuekes , Carrie L. Donley , Jason J. Blackstock
发明人： Theodore I. Kamins , Philip J. Kuekes , Carrie L. Donley , Jason J. Blackstock
IPC分类号： H01L29/40
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y15/00 , B82Y20/00 , G01K7/186 , G01K2211/00 , H01L21/02381 , H01L21/02532 , H01L21/02546 , H01L21/02601 , H01L21/02603 , H01L21/02639 , H01L21/02645 , H01L21/02653 , H01L29/0673 , H01L29/0676 , Y10S977/762 , Y10S977/765
摘要： A nanowire device includes a nanowire formed between two surfaces, and a gap formed at a predetermined location in the nanowire.
摘要翻译：纳米线器件包括形成在两个表面之间的纳米线和形成在纳米线中的预定位置处的间隙。

104. 发明授权

US07545999B2 Photonic configuration 有权
标题翻译：光子配置
公开(公告)号：US07545999B2
公开(公告)日：2009-06-09
申请号：US11264206
申请日：2005-11-01
申请人： Philip J. Kuekes , Theodore I. Kamins
发明人： Philip J. Kuekes , Theodore I. Kamins
IPC分类号： G02B6/12 , G02B6/42
CPC分类号： G02B6/43 , B82Y20/00 , G02B6/1225
摘要： An apparatus comprising an integrated circuit having a plurality of devices each having device characteristics, and a waveguide structure coupled to the integrated circuit, wherein photons provided to the waveguide structure are directed to one or more devices of the plurality of devices and can alter the device characteristics of the device or devices.
摘要翻译：一种包括集成电路的装置，其具有各自具有器件特性的多个器件，以及耦合到所述集成电路的波导结构，其中提供给所述波导结构的光子被引导到所述多个器件中的一个或多个器件，并且可以改变所述器件设备或设备的特性。

105. 发明授权

US07525833B2 Nanoscale shift register and signal demultiplexing using microscale/nanoscale shift registers 有权
标题翻译：使用微米/纳米级移位寄存器的纳米级移位寄存器和信号解复用
公开(公告)号：US07525833B2
公开(公告)日：2009-04-28
申请号：US11255722
申请日：2005-10-21
申请人： Gregory S. Snider , Philip J. Kuekes
发明人： Gregory S. Snider , Philip J. Kuekes
IPC分类号： G11C11/00
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0023 , G11C19/00 , G11C2213/17 , G11C2213/77 , G11C2213/81
摘要： One embodiment of the present invention is a nanoscale shift register that can be used, in certain nanoscale and mixed-scale logic circuits, to distribute an input signal to individual nanowires of the logic circuit. In a described embodiment, the nanoscale shift register includes two series of nanoscale latches, each series controlled by common latch-control signals. Internal latches of each series of latches are alternatively interconnected with a previous latch of the other series and a next latch of the other series by two series of gates, each controlled by a gate signal line.
摘要翻译：本发明的一个实施例是纳米级移位寄存器，其可以在某些纳米尺度和混合尺度的逻辑电路中用于将输入信号分配到逻辑电路的各个纳米线。在所描述的实施例中，纳米尺度移位寄存器包括两个系列的纳米尺度锁存器，每个串联由公共锁存控制信号控制。每个锁存器系列的内部锁存器交替地与另一个串联的先前锁存器和另一个串联的下一个锁存器通过两个串联的栅极互连，每个栅极由栅极信号线控制。

106. 发明申请

US20080238478A1 FPGA architecture at conventonal and submicron scales 有权
标题翻译： FPGA架构在conventonal和亚微米尺度
公开(公告)号：US20080238478A1
公开(公告)日：2008-10-02
申请号：US12156877
申请日：2008-06-04
申请人： Gregory S. Snider , Philip J. Kuekes
发明人： Gregory S. Snider , Philip J. Kuekes
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , B82Y10/00 , B82Y30/00 , G11C8/10 , G11C13/0007 , G11C13/0014 , G11C2213/15 , G11C2213/34 , G11C2213/51 , G11C2213/77 , G11C2213/81 , H03K19/17728 , H03K19/1778
摘要： Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable impedance devices operably coupled to the input signals, and the LUT output signals. Each programmable impedance device in the array includes a first electrode operably coupled to one of the input signal, a second electrode disposed to form a junction wherein the second electrode at least partially overlaps the first electrode, and a programmable material disposed between the first electrode and the second electrode. The programmable material operably couples the first electrode and the second electrode such that each programmable impedance device exhibits a non-volatile programmable impedance. The array may be configured as a one-dimensional or two-dimensional array.
摘要翻译：公开了可重构逻辑器件和编程器件的方法。逻辑器件包括查找表（LUT）和配置用于对LUT输出信号进行采样的至少一个存储元件。 LUT包括多个输入信号，可操作地耦合到输入信号的可编程阻抗装置的阵列和LUT输出信号。阵列中的每个可编程阻抗器件包括可操作地耦合到输入信号中的一个的第一电极，设置成形成其中第二电极至少部分地与第一电极重叠的结的第二电极和设置在第一电极和第二电极。可编程材料可操作地耦合第一电极和第二电极，使得每个可编程阻抗装置呈现非易失性可编程阻抗。该阵列可以被配置为一维或二维阵列。

107. 发明申请

US20080179756A1 Semiconductor structures including conductive vias and methods of making semiconductor structures 有权
标题翻译：包括导电通孔的半导体结构和制造半导体结构的方法
公开(公告)号：US20080179756A1
公开(公告)日：2008-07-31
申请号：US11700034
申请日：2007-01-31
申请人： Theodore I. Kamins , Philip J. Kuekes
发明人： Theodore I. Kamins , Philip J. Kuekes
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76898
摘要： Semiconductor structures are disclosed including a substrate comprising a semiconductor material and having opposed first and second surfaces, and at least one conductive via extending from the first surface to the second surface. The conductive vias can extend at angles relative to the first surface, such as acute angles or 90°. The conductive vias can include segments that extend at different angles. Methods of forming conductive vias in semiconductor structures are provided. In the methods, a thermal gradient is applied in combination with an electric field to form conductive vias.
摘要翻译：公开了半导体结构，其包括包括半导体材料并且具有相对的第一和第二表面的衬底以及从第一表面延伸到第二表面的至少一个导电通孔。导电孔可以相对于第一表面的角度延伸，例如锐角或90°。导电通孔可以包括以不同角度延伸的段。提供了在半导体结构中形成导电通孔的方法。在该方法中，结合电场施加热梯度以形成导电通孔。

108. 发明申请

US20080116490A1 SENSING METHOD AND NANOSENSING DEVICE FOR PERFORMING THE SAME 失效
标题翻译：感测方法和用于执行其的纳米器件
公开(公告)号：US20080116490A1
公开(公告)日：2008-05-22
申请号：US11583262
申请日：2006-10-19
申请人： Duncan R. Stewart , William M. Tong , R. Stanley Williams , Philip J. Kuekes , Sean Xiao-an Zhang , Kevin F. Peters , Kenneth J. Ward
发明人： Duncan R. Stewart , William M. Tong , R. Stanley Williams , Philip J. Kuekes , Sean Xiao-an Zhang , Kevin F. Peters , Kenneth J. Ward
IPC分类号： H01L27/10 , H01L29/73
CPC分类号： G01N27/128 , Y10S977/762 , Y10S977/957
摘要： A sensing method includes exposing a nano-transducer having a controlled surface to a sample including at least one species. Adsorption of the species on the nano-transducer is transduced to a measurable signal as a function of time. Desorption of the species from the nano-transducer is also transduced to a measurable signal as a function of time. A residence time of the at least one species adsorbed on the nano-transducer is extracted from the measurable signals. The adsorption and desorption each define an individual measurable event.
摘要翻译：感测方法包括将具有受控表面的纳米换能器暴露于包括至少一种的样品。物种在纳米转换器上的吸附作为时间的函数被转导到可测量的信号。物种从纳米转换器的解吸也被转换为可测量的信号作为时间的函数。从可测量信号中提取吸附在纳米换能器上的至少一种物质的停留时间。吸附和解吸各自定义一个单独的可测量事件。

109. 发明授权

US07256435B1 Multilevel imprint lithography 有权
标题翻译：多层压印光刻
公开(公告)号：US07256435B1
公开(公告)日：2007-08-14
申请号：US10453329
申请日：2003-06-02
申请人： Pavel Kornilovich , Yong Chen , Duncan Stewart , R. Stanley Williams , Philip J. Kuekes , Mehmet Fatih Yanik
发明人： Pavel Kornilovich , Yong Chen , Duncan Stewart , R. Stanley Williams , Philip J. Kuekes , Mehmet Fatih Yanik
IPC分类号： H01L27/10
CPC分类号： H01L21/76838 , B81C99/009 , B81C2201/0153 , B82Y10/00 , B82Y40/00 , G03F7/0002
摘要： A mold with a protruding pattern is provided that is pressed into a thin polymer film via an imprinting process. Controlled connections between nanowires and microwires and other lithographically-made elements of electronic circuitry are provided. An imprint stamp is configured to form arrays of approximately parallel nanowires which have (1) micro dimensions in the X direction, (2) nano dimensions and nano spacing in the Y direction, and three or more distinct heights in the Z direction. The stamp thus formed can be used to connect specific individual nanowires to specific microscopic regions of microscopic wires or pads. The protruding pattern in the mold creates recesses in the thin polymer film, so the polymer layer acquires the reverse of the pattern on the mold. After the mold is removed, the film is processed such that the polymer pattern can be transferred on a metal/semiconductor pattern on the substrate.
摘要翻译：提供具有突出图案的模具，其通过压印过程被压入薄聚合物膜。提供了纳米线和微丝之间的控制连接以及电子电路的其它光刻元件。打印印记被配置成形成大致平行的纳米线的阵列，其具有（1）X方向上的微尺寸，（2）在Y方向上的纳米尺寸和纳米间距，以及Z方向上的三个或更多个不同的高度。如此形成的印章可以用于将特定的单个纳米线连接到微细线或垫的特定微观区域。模具中的突出图案在薄聚合物膜中产生凹陷，因此聚合物层获得模具上图案的相反。在除去模具之后，处理膜，使得聚合物图案可以在基底上的金属/半导体图案上转印。

110. 发明授权

US07227379B1 Nanoscale latch-array processing engines 有权
标题翻译：纳米级闩锁阵列处理引擎
公开(公告)号：US07227379B1
公开(公告)日：2007-06-05
申请号：US11192197
申请日：2005-07-27
申请人： Gregory S. Snider , Philip J. Kuekes , Duncan R. Stewart
发明人： Gregory S. Snider , Philip J. Kuekes , Duncan R. Stewart
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： B82Y10/00 , G06N99/007 , H01L27/101
摘要： One embodiment of the present invention is an array of nanoscale latches interconnected by a nanowire bus to form a latch array. Each nanoscale latch in the nanoscale-latch array serves as a nanoscale register, and is driven by a nanoscale control line. Primitive operations for the latch array can be defined as sequences of one or more inputs to one or more of the nanowire data bus and nanoscale control lines. In various latch-array embodiments of the present invention, information can be transferred from one nanoscale latch to another nanoscale latch in a controlled fashion, and sequences of information-transfer operations can be devised to implement arbitrary Boolean logic operations and operators, including NOT, AND, OR, XOR, NOR, NAND, and other such Boolean logic operators and operations, as well as input and output functions. Nanoscale-latch arrays can be combined and interconnected in an almost limitless number of different ways to construct arbitrarily complex, sequential, parallel, or both parallel and sequential computing engines that represent additional embodiments of the present invention.
摘要翻译：本发明的一个实施例是通过纳米线总线互连以形成锁存阵列的纳米级锁存器的阵列。纳米尺度锁存阵列中的每个纳米级锁存器用作纳米尺度寄存器，并由纳米尺度控制线驱动。锁存阵列的原始操作可以被定义为一个或多个输入到纳米线数据总线和纳米尺度控制线中的一个或多个的序列。在本发明的各种锁存阵列实施例中，可以以受控的方式将信息从一个纳米级锁存器传送到另一个纳米级锁存器，并且可以设计信息传输操作的序列以实现任意的布尔逻辑运算，并且运算符包括NOT， AND，OR，XOR，NOR，NAND和其他这样的布尔逻辑运算符和操作，以及输入和输出功能。纳秒级锁存器阵列可以以几乎无限数量的不同方式组合和互连，以构造代表本发明附加实施例的任意复杂，顺序，并行或并行和顺序的计算引擎。

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