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101. 发明申请

US20080079085A1 SEMICONDUCTOR DEVICE COMPRISING ISOLATION TRENCHES INDUCING DIFFERENT TYPES OF STRAIN 有权
标题翻译：包含分离条件的半导体器件诱导不同类型的应变
公开(公告)号：US20080079085A1
公开(公告)日：2008-04-03
申请号：US11734320
申请日：2007-04-12
申请人： Christoph Schwan , Joe Bloomquist , Peter Javorka , Manfred Horstmann , Sven Beyer , Markus Forsberg , Frank Wirbeleit , Karla Romero
发明人： Christoph Schwan , Joe Bloomquist , Peter Javorka , Manfred Horstmann , Sven Beyer , Markus Forsberg , Frank Wirbeleit , Karla Romero
IPC分类号： H01L21/762 , H01L23/58 , H01L29/78
CPC分类号： H01L21/823878 , H01L21/76229 , H01L21/823807 , H01L29/7833 , H01L29/7843 , H01L29/7846
摘要： By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately provided in the respective isolation trenches in order to correspondingly adapt the charge carrier mobility of respective channel regions.
摘要翻译：通过基于分离的工艺顺序形成不同类型的固有应力的隔离沟槽，可以调节相邻有源半导体区域的应变特性以获得整体器件性能。例如，可以在相应的隔离沟槽中适当地提供包括压缩和拉伸应力的高应力电介质填充材料，以便相应地适应各个沟道区的电荷载流子迁移率。

102. 发明授权

US07329571B2 Technique for providing multiple stress sources in NMOS and PMOS transistors 有权
标题翻译：在NMOS和PMOS晶体管中提供多个应力源的技术
公开(公告)号：US07329571B2
公开(公告)日：2008-02-12
申请号：US11466802
申请日：2006-08-24
申请人： Jan Hoentschel , Andy Wei , Manfred Horstmann , Thorsten Kammler
发明人： Jan Hoentschel , Andy Wei , Manfred Horstmann , Thorsten Kammler
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/44
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823864 , H01L27/1203 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/7843 , H01L29/7848 , H01L29/78618 , H01L29/78684
摘要： By combining a plurality of stress inducing mechanisms in each of different types of transistors, a significant performance gain may be obtained, thereby providing enhanced flexibility in adjusting product specific characteristics. For this purpose, sidewall spacers with high tensile stress may be commonly formed on PMOS and NMOS transistors, wherein a deleterious effect on the PMOS transistor may be compensated for by a corresponding compressively stressed contact etch stop layer, while the NMOS transistor comprises a contact etch stop layer with tensile stress. Furthermore, the PMOS transistor comprises an embedded strained semiconductor layer for efficiently creating compressive strain in the channel region.
摘要翻译：通过在不同类型的晶体管中组合多个应力诱导机构，可以获得显着的性能增益，从而在调整产品特定特性方面提供增强的灵活性。为此，可以在PMOS和NMOS晶体管上通常形成具有高拉伸应力的侧壁间隔物，其中可以通过相应的压缩应力接触蚀刻停止层补偿对PMOS晶体管的有害影响，而NMOS晶体管包括接触蚀刻停止层拉伸应力。此外，PMOS晶体管包括用于在沟道区域中有效地产生压缩应变的嵌入式应变半导体层。

103. 发明申请

US20080026552A1 METHOD OF ENHANCING LITHOGRAPHY CAPABILITIES DURING GATE FORMATION IN SEMICONDUCTORS HAVING A PRONOUNCED SURFACE TOPOGRAPHY 有权
标题翻译：在具有预定表面形貌的半导体中增加栅格形成过程中的刻蚀能力的方法
公开(公告)号：US20080026552A1
公开(公告)日：2008-01-31
申请号：US11773631
申请日：2007-07-05
申请人： Martin Gerhardt , Martin Trentzsch , Markus Forsberg , Manfred Horstmann
发明人： Martin Gerhardt , Martin Trentzsch , Markus Forsberg , Manfred Horstmann
IPC分类号： H01L21/4763
CPC分类号： H01L21/28123 , H01L29/66772
摘要： In a mesa isolation configuration for forming a transistor on a semiconductor island, an additional planarization step is performed to enhance the uniformity of the gate patterning process. In some illustrative embodiments, the gate electrode material may be planarized, for instance, on the basis of CMP, to compensate for the highly non-uniform surface topography, when the gate electrode material is formed above the non-filled isolation trenches. Consequently, significant advantages of the mesa isolation strategy may be combined with a high degree of scalability due to the enhancement of the critical gate patterning process.
摘要翻译：在用于在半导体岛上形成晶体管的台面隔离结构中，执行附加的平面化步骤以增强栅极图案化工艺的均匀性。在一些说明性实施例中，当栅电极材料形成在未填充的隔离沟槽上方时，栅电极材料可以例如基于CMP平坦化，以补偿高度不均匀的表面形貌。因此，由于关键栅极图案化工艺的增强，台面隔离策略的显着优点可能与高度的可扩展性相结合。

104. 发明申请

US20070252205A1 SOI TRANSISTOR HAVING A REDUCED BODY POTENTIAL AND A METHOD OF FORMING THE SAME 有权
标题翻译：具有减少身体潜力的SOI晶体管及其形成方法
公开(公告)号：US20070252205A1
公开(公告)日：2007-11-01
申请号：US11609995
申请日：2006-12-13
申请人： Jan Hoentschel , Andy Wei , Joe Bloomquist , Manfred Horstmann
发明人： Jan Hoentschel , Andy Wei , Joe Bloomquist , Manfred Horstmann
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L29/78609 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78621
摘要： By introducing a atomic species, such as carbon, fluorine and the like, into the drain and source regions, as well as in the body region, the junction leakage of SOI transistors may be significantly increased, thereby providing an enhanced leakage path for accumulated minority charge carriers. Consequently, fluctuations of the body potential may be significantly reduced, thereby improving the overall performance of advanced SOI devices. In particular embodiments, the mechanism may be selectively applied to threshold voltage sensitive device areas, such as static RAM areas.
摘要翻译：通过将诸如碳，氟等的原子物质引入漏极和源极区域以及在体区域中，可以显着增加SOI晶体管的结漏电，从而为累积的少数族群提供增强的泄漏路径电荷载体。因此，体电位的波动可能会显着降低，从而提高先进的SOI器件的整体性能。在特定实施例中，可以将机构选择性地应用于阈值电压敏感设备区域，例如静态RAM区域。

105. 发明申请

US20070096195A1 TECHNIQUE FOR PROVIDING MULTIPLE STRESS SOURCES IN NMOS AND PMOS TRANSISTORS 有权
标题翻译：在NMOS和PMOS晶体管中提供多个应力源的技术
公开(公告)号：US20070096195A1
公开(公告)日：2007-05-03
申请号：US11466802
申请日：2006-08-24
申请人： Jan Hoentschel , Andy Wei , Manfred Horstmann , Thorsten Kammler
发明人： Jan Hoentschel , Andy Wei , Manfred Horstmann , Thorsten Kammler
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823864 , H01L27/1203 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/7843 , H01L29/7848 , H01L29/78618 , H01L29/78684
摘要： By combining a plurality of stress inducing mechanisms in each of different types of transistors, a significant performance gain may be obtained, thereby providing enhanced flexibility in adjusting product specific characteristics. For this purpose, sidewall spacers with high tensile stress may be commonly formed on PMOS and NMOS transistors, wherein a deleterious effect on the PMOS transistor may be compensated for by a corresponding compressively stressed contact etch stop layer, while the NMOS transistor comprises a contact etch stop layer with tensile stress. Furthermore, the PMOS transistor comprises an embedded strained semiconductor layer for efficiently creating compressive strain in the channel region.
摘要翻译：通过在不同类型的晶体管中组合多个应力诱导机构，可以获得显着的性能增益，从而在调整产品特定特性方面提供增强的灵活性。为此，可以在PMOS和NMOS晶体管上通常形成具有高拉伸应力的侧壁间隔物，其中可以通过相应的压缩应力接触蚀刻停止层补偿对PMOS晶体管的有害影响，而NMOS晶体管包括接触蚀刻停止层拉伸应力。此外，PMOS晶体管包括用于在沟道区域中有效地产生压缩应变的嵌入式应变半导体层。

106. 发明授权

US07064074B2 Technique for forming contacts for buried doped regions in a semiconductor device 有权
标题翻译：在半导体器件中形成掩埋掺杂区的接触的技术
公开(公告)号：US07064074B2
公开(公告)日：2006-06-20
申请号：US10624712
申请日：2003-07-22
申请人： Ralf van Bentum , Manfred Horstmann
发明人： Ralf van Bentum , Manfred Horstmann
IPC分类号： H01L21/302
CPC分类号： H01L21/76229 , H01L21/74
摘要： A semiconductor device comprises an isolation trench and a contact trench that may contact a buried conductive region. The contact trench comprises insulating sidewall spacers that are formed during the filling of the isolation trench with an insulating material and the subsequent anisotropic etching of the excess material. Thereafter, the contact trench is filled with a conductive material. Thus, the formation of a contact for a buried region may be carried out simultaneously with the formation of a trench isolation structure, thereby minimizing the number of process steps required.
摘要翻译：半导体器件包括隔离沟槽和可接触埋入导电区域的接触沟槽。接触沟槽包括绝缘侧壁间隔物，其在用隔离材料填充隔离沟槽期间形成，并且随后对多余材料进行各向异性蚀刻。此后，用导电材料填充接触沟槽。因此，可以与形成沟槽隔离结构同时进行掩埋区域的接触的形成，从而最小化所需的工艺步骤的数量。

107. 发明授权

US06555892B2 Semiconductor device with reduced line-to-line capacitance and cross talk noise 有权
公开(公告)号：US06555892B2
公开(公告)日：2003-04-29
申请号：US09812372
申请日：2001-03-20
申请人： Manfred Horstmann , Karsten Wieczorek , Frederick N. Hause
发明人： Manfred Horstmann , Karsten Wieczorek , Frederick N. Hause
IPC分类号： H01L2900
CPC分类号： H01L29/6659 , H01L21/28247 , H01L21/76801 , H01L23/5329 , H01L29/41725 , H01L29/41775 , H01L29/4983 , H01L2924/0002 , H01L2924/00
摘要： A transistor device is disclosed, having an insulating material disposed between the gate electrode and the drain and source lines, wherein the dielectric constant of the insulating material is 3.5 or less. Accordingly, the capacitance between the gate electrode and the drain and source lines can be reduced, thereby improving signal performance of the field effect transistor with decreased cross talk noise.

108. 发明授权

US06541863B1 Semiconductor device having a reduced signal processing time and a method of fabricating the same 有权
标题翻译：具有减小的信号处理时间的半导体器件及其制造方法
公开(公告)号：US06541863B1
公开(公告)日：2003-04-01
申请号：US09475572
申请日：2000-01-05
申请人： Manfred Horstmann , Karsten Wieczorek , Gert Burbach
发明人： Manfred Horstmann , Karsten Wieczorek , Gert Burbach
IPC分类号： H01L2348
CPC分类号： H01L23/5222 , H01L21/76807 , H01L21/7682 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor device comprising an insulating layer which is partly formed of porous material, and a method for fabricating the device. A stray capacitance of adjacent wiring lines is significantly reduced by reducing the amount of material, i.e., by using porous material in the insulating layer of a metallization layer. In one embodiment, the porous layer may be fabricated separately on a further substrate and is subsequently transferred to the product wafer while the further substrate and the product wafer are appropriately aligned to each other. In this way, fabrication of complete metallization layers having a reduced dielectric constant in advance or concurrently with the product wafer carrying the MOS structure is possible. Due to the reduced capacitance of the wiring lines of the metallization layer, signal performance and/or power consumption of an integrated circuit is improved.
摘要翻译：提供了一种包括部分由多孔材料形成的绝缘层的半导体器件及其制造方法。通过减少材料的量，即通过在金属化层的绝缘层中使用多孔材料，相当布线的杂散电容显着降低。在一个实施例中，多孔层可以分开制造在另一个衬底上，随后转移到产品晶片，同时另外的衬底和产品晶片彼此适当地对准。以这种方式，可以预先制造具有降低的介电常数的完整金属化层或与携带MOS结构的产品晶片同时进行。由于金属化层的布线的电容降低，提高了集成电路的信号性能和/或功耗。

109. 发明授权

US06274894B1 Low-bandgap source and drain formation for short-channel MOS transistors 有权
标题翻译：短沟道MOS晶体管的低带隙源极和漏极形成
公开(公告)号：US06274894B1
公开(公告)日：2001-08-14
申请号：US09375920
申请日：1999-08-17
申请人： Karsten Wieczorek , Manfred Horstmann , Frederick N. Hause
发明人： Karsten Wieczorek , Manfred Horstmann , Frederick N. Hause
IPC分类号： H01L31072
CPC分类号： H01L29/0847 , H01L29/1083 , H01L29/165 , H01L29/41766 , H01L29/66477 , H01L29/66628 , H01L29/66636
摘要： A transistor having source and drain regions which include lower-bandgap portions and a method for making the same are provided. A gate conductor is formed over a gate dielectric on a semiconductor substrate. The gate conductor is covered on all sides with oxide or another dielectric for protection during subsequent processing. Anisotropic etching is used to form shallow trenches in the substrate on either side of the gate conductor. The trenches are bounded by the dielectric-coated gate conductor and by dielectric isolation regions, or by an adjacent gate conductor in the case of non-isolated transistors. A selective epitaxy technique may then be used to grow a layer within each trench of a material having a bandgap lower than that of the semiconductor substrate. The lower-bandgap material is preferably grown only on the exposed semiconductor surfaces in the trenches, and not on the surrounding dielectric regions. The lower-bandgap material may be an undoped layer used as a buffer for interdiffusion of dopants between the channel and source/drain regions of the transistor. The lower-bandgap material may also be a heavily doped layer with the same carrier type as the semiconductor substrate, used as a halo region to reduce punchthrough and threshold voltage lowering effects. The buffer and halo functions may also be combined using multilayer source/drain structures. The portion of the trench above such buffer and/or halo layers is filled with a semiconductor material doped with the opposite carrier type than that of the substrate to form lightly-doped-drain portions of the transistor source and drain.
摘要翻译：提供具有包括低带隙部分的源极和漏极区域的晶体管及其制造方法。在半导体衬底上的栅极电介质上形成栅极导体。栅极导体在所有侧面都被氧化物或另一个电介质覆盖，用于在后续处理过程中进行保护。各向异性蚀刻用于在栅极导体两侧的衬底中形成浅沟槽。在非隔离晶体管的情况下，沟槽由电介质涂覆的栅极导体和介电隔离区域或相邻栅极导体限制。然后可以使用选择性外延技术来在具有比半导体衬底的带隙低的带隙的材料的每个沟槽内生长层。较低带隙材料优选仅在沟槽中的暴露的半导体表面上生长，而不是在周围的电介质区域上生长。低带隙材料可以是用作缓冲器的未掺杂层，用于在晶体管的沟道和源极/漏极区之间的掺杂剂的相互扩散。较低带隙材料也可以是具有与半导体衬底相同载流子类型的重掺杂层，用作卤素区域以减少穿通和阈值电压降低效应。缓冲区和晕圈功能也可以使用多层源/漏结构组合。在这种缓冲区和/或晕圈之上的沟槽部分填充掺杂有与衬底相反的载体类型的半导体材料，以形成晶体管源极和漏极的轻掺杂漏极部分。

110. 发明授权

US06255182B1 Method of forming a gate structure of a transistor by means of scalable spacer technology 失效
标题翻译：通过可扩展间隔技术形成晶体管栅极结构的方法
公开(公告)号：US06255182B1
公开(公告)日：2001-07-03
申请号：US09503634
申请日：2000-02-14
申请人： Karsten Wieczorek , Manfred Horstmann , Frederick N. Hause
发明人： Karsten Wieczorek , Manfred Horstmann , Frederick N. Hause
IPC分类号： H01L21336
CPC分类号： H01L21/28132 , H01L29/665 , H01L29/6659
摘要： A method is described which can be used to form gate structures of very small dimensions in a semiconductor device. The method may be used to avoid employment of highly-sophisticated and cost-intensive DUV photolithography. In one illustrative embodiment, the method comprises forming a gate electrode layer, forming a first mask layer above the gate electrode layer, and forming a sidewall spacer adjacent the sidewalls of the first mask layer. Thereafter, the method comprises forming a second mask layer above a portion of the sidewall spacer and the first mask layer, removing portions of the sidewall spacer to define a hard mask comprised of a portion of the sidewall spacer, and patterning the gate electrode layer using the hard mask to define a gate electrode of the device.
摘要翻译：描述了可用于在半导体器件中形成非常小尺寸的栅极结构的方法。该方法可以用于避免使用高度复杂和成本高的DUV光刻。在一个说明性实施例中，该方法包括形成栅极电极层，在栅极电极层上形成第一掩模层，以及形成邻近第一掩模层的侧壁的侧壁间隔物。此后，该方法包括在侧壁间隔物和第一掩模层的一部分上方形成第二掩模层，去除侧壁间隔物的部分以限定由侧壁间隔物的一部分组成的硬掩模，并且使用硬掩模来定义器件的栅电极。

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