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101. 发明授权

US06326658B1 Semiconductor device including an interface layer containing chlorine 失效
标题翻译：包括含有氯的界面层的半导体装置
公开(公告)号：US06326658B1
公开(公告)日：2001-12-04
申请号：US09404594
申请日：1999-09-24
申请人： Yoshitaka Tsunashima , Katsuya Okumura , Masayuki Tanaka , Shigehiko Saida , Hirofumi Inoue , Takeshi Hamamoto
发明人： Yoshitaka Tsunashima , Katsuya Okumura , Masayuki Tanaka , Shigehiko Saida , Hirofumi Inoue , Takeshi Hamamoto
IPC分类号： H01L27108
CPC分类号： H01L27/10867
摘要： A buried strap is formed after forming an SiC layer on the side surface of a trench in order to suppress the epitaxial growth of Si from the side surface (single crystal Si) of the trench to the buried strap (polycrystalline Si) without causing an increase in the contact resistance in the post process accompanied by high temperature after formation of the buried strap.
摘要翻译：在沟槽侧面上形成SiC层之后形成掩埋带，以抑制从沟槽的侧表面（单晶Si）到掩埋带（多晶Si）的Si的外延生长而不会增加在后处理中的接触电阻伴随着形成埋藏带的高温。

102. 发明授权

US06323272B1 Polyamide resin composition 有权
标题翻译：聚酰胺树脂组合物
公开(公告)号：US06323272B1
公开(公告)日：2001-11-27
申请号：US09637658
申请日：2000-08-11
申请人： Kenji Tamura , Hirofumi Inoue , Junichi Nakamura , Masayuki Noguchi , Tsuguo Ebata
发明人： Kenji Tamura , Hirofumi Inoue , Junichi Nakamura , Masayuki Noguchi , Tsuguo Ebata
IPC分类号： C08K906
CPC分类号： C08L77/00 , C08K9/04 , C08L23/0869 , C08L77/02 , C08L77/06 , C08L23/00
摘要： The invention provides polyamide resin compositions with good mechanical properties and dimensional stability during water absorption. Polyamide resin composition, comprising 100 parts by weight of resin contents composed of (A) 60 to 98% by weight of polyamide resin, (B) 40 to 2% by weight of polyolefine resin having dicarboxylic acid anhydride groups, as well as (C) 0.3 to 30 parts by weight of triazine-containing layered silicate with intercalated triazine compound derivatives with at least one positive charge.
摘要翻译：本发明提供了具有良好机械性能和吸水时尺寸稳定性的聚酰胺树脂组合物。聚酰胺树脂组合物包含100重量份由（A）60-98重量％的聚酰胺树脂组成的树脂含量，（B）40至2重量％的具有二羧酸酐基团的聚烯烃树脂以及（C ）0.3〜30重量份具有至少一个正电荷的插层三嗪化合物衍生物的含三嗪层状硅酸盐。

103. 发明授权

US06274663B1 Compound resin composition 失效
标题翻译：复合树脂组合物
公开(公告)号：US06274663B1
公开(公告)日：2001-08-14
申请号：US09331638
申请日：1999-06-23
申请人： Teruo Hosokawa , Hirofumi Inoue
发明人： Teruo Hosokawa , Hirofumi Inoue
IPC分类号： C08K300
CPC分类号： C08K9/04 , C08K2201/008
摘要： A compound resin composition in which an intercalated compound, in which an onium salt of an aminoalcohol derivative is inserted into the layers of a swellable stratified compound and the interlayer distance is 10˜25 Å as measured by x-ray diffraction, is finely dispersed in a heat curable resin, wherein the proportion is the intercalated compound with respect to the compound resin composition is in the range of 0.5˜60% by weight. This compound resin composition has excellent bending elastic modulus and thermal resistance, and is therefore suitably employed in a number of fields such as the automotive components, home appliance parts, aircraft parts, and construction materials fields, among others.
摘要翻译：将其中将氨基醇衍生物的鎓盐插入可膨胀的分层化合物的层中的插层化合物和通过x射线衍射测量的层间距离为10〜25的复合树脂组合物被细分散在相对于化合物树脂组合物，所述嵌入化合物的比例为0.5〜60重量％的热固性树脂。该复合树脂组合物具有优异的弯曲弹性模量和耐热性，因此适用于汽车部件，家电部件，飞机部件，建筑材料领域等多个领域。

104. 发明授权

US6074903A Method for forming electrical isolation for semiconductor devices 失效
标题翻译：用于形成半导体器件的电隔离的方法
公开(公告)号：US6074903A
公开(公告)日：2000-06-13
申请号：US98203
申请日：1998-06-16
申请人： Rajesh Rengarajan , Hirofumi Inoue , Radhika Srinivasan , Jochen Beintner
发明人： Rajesh Rengarajan , Hirofumi Inoue , Radhika Srinivasan , Jochen Beintner
IPC分类号： H01L21/76 , H01L21/762 , H01L27/08 , H01L21/8238
CPC分类号： H01L21/76237
摘要： A method for forming a electrically isolated semiconductor devices in a silicon body. A trench is formed in a selected region of the body. A barrier material is deposited over sidewalls of the trench. Portions of the barrier material are removed from a first sidewall portion of the trench to expose such first sidewall portion of the trench while leaving portions of such barrier material on a second sidewall portion of the trench to form a barrier layer thereon. A dielectric material is deposited in the trench, a portion of dielectric material being deposited on the exposed first sidewall portion of the trench and another portion of such deposited dielectric material being deposited on the barrier material. The dielectric material is annealed in an oxidizing environment to densify such deposited dielectric material, the barrier layer inhibiting oxidation of the said second sidewall portion of the trench. A plurality of the semiconductor devices is formed in the silicon body with such devices being electrically isolated by the dielectric material in the trench.
摘要翻译：一种用于在硅体中形成电绝缘的半导体器件的方法。在身体的选定区域中形成沟槽。阻挡材料沉积在沟槽的侧壁上。阻挡材料的一部分从沟槽的第一侧壁部分被去除以暴露沟槽的这种第一侧壁部分，同时将这种阻挡材料的一部分留在沟槽的第二侧壁部分上以在其上形成阻挡层。电介质材料沉积在沟槽中，介电材料的一部分沉积在暴露的沟槽的第一侧壁部分上，另一部分沉积的介电材料沉积在阻挡材料上。电介质材料在氧化环境中退火以致密化这种淀积的介电材料，阻挡层阻止沟槽的所述第二侧壁部分的氧化。在硅体中形成多个半导体器件，这些器件通过沟槽中的电介质材料电隔离。

105. 发明授权

US4381856A Method of repairing blast furnace wall lining 失效
标题翻译：高炉墙衬修复方法
公开(公告)号：US4381856A
公开(公告)日：1983-05-03
申请号：US396861
申请日：1982-07-09
申请人： Akihiko Inoue , Hirofumi Inoue , Tsuyoshi Nakamura , Seiji Tobino , Masamitsu Baba
发明人： Akihiko Inoue , Hirofumi Inoue , Tsuyoshi Nakamura , Seiji Tobino , Masamitsu Baba
IPC分类号： C21B7/06 , F27D1/16
CPC分类号： C21B7/06
摘要： In repairing lining damage in a blast furnace, the furnace is blown down after lowering the burden inside to below the damaged part. Then a plurality of openings and a refractories filling aperture are provided through the furnace wall in the damaged part. A preliminarily prepared panel is lowered down through an opening in the furnace top to a position opposite to the damaged part. One end of a string-like member whose other end is fastened to the panel is drawn outside the furnace through one of the openings. The whole length of the string-like member is protectively covered by a single or double support tube and stretched therethrough. Monolithic refractories are forced in through the refractories filling aperture into a clearance between the damaged part and panel either during blowing down or after blowing in.
摘要翻译：在高炉修复衬里损坏时，将其内部的负担降低到受损部件的下方，将炉子吹走。然后通过损坏部分的炉壁设置多个开口和耐火材料填充孔。预先准备好的面板通过炉顶中的开口向下降到与损坏部分相对的位置。另一端固定在面板上的线状构件的一端通过其中一个开口被拉出炉外。弦状构件的整个长度由单个或双重支撑管保护性地覆盖并且被拉伸穿过。通过耐火材料填充孔将单片耐火材料压入损坏的部件和面板之间的空隙中，或者在吹下或吹入之后。

106. 发明授权

US08391082B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08391082B2
公开(公告)日：2013-03-05
申请号：US13099540
申请日：2011-05-03
申请人： Hiroyuki Nagashima , Hirofumi Inoue
发明人： Hiroyuki Nagashima , Hirofumi Inoue
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C7/1006 , G11C7/1051 , G11C7/1075 , G11C7/22 , G11C8/16 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0061 , G11C13/0097 , G11C2013/0076 , G11C2013/0078 , G11C2013/0092 , G11C2213/31 , G11C2213/72 , G11C2216/24
摘要： A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, each memory cell containing an electrically erasable programmable variable resistive element of which resistance is stored in a non-volatile manner as data; and a plurality of write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the plurality of write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the plurality of write/erase circuits erases data from memory cells inside a corresponding MAT at the same time.
摘要翻译：一种非易失性半导体存储器件，包括一个单元阵列，该单元阵列包括矩阵排列的多个MAT（单元阵列），每个MAT包含多条第一线，与该多条第一线交叉的多条第二线，以及多条存储单元两行之间的第一和第二行的交点，每个存储单元包含以电阻作为数据以非易失性方式存储的电可擦除可编程可变电阻元件; 以及多个写入/擦除电路，连接到MAT，并根据输入数据对MAT内的存储单元执行数据写入或擦除。多个写/擦除电路的一部分将数据写入相应MAT内的存储单元，而多个写/擦除电路的另一部分同时从相应MAT内的存储单元擦除数据。

107. 发明授权

US08391048B2 Non-volatile semiconductor memory device including memory cells with a variable resistor 有权
标题翻译：包括具有可变电阻器的存储单元的非易失性半导体存储器件
公开(公告)号：US08391048B2
公开(公告)日：2013-03-05
申请号：US12846198
申请日：2010-07-29
申请人： Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue , Hiroshi Kanno
发明人： Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue , Hiroshi Kanno
IPC分类号： G11C11/00
CPC分类号： G11C13/0061 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C13/0097 , G11C2013/0092
摘要： A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.
摘要翻译：根据本发明的实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一布线; 多个第二布线穿过多个第一布线; 以及分别布置在第一布线和第二布线的交点处的多个电可重写存储器单元，并且每个由可变电阻器形成，其以非易失性方式存储电阻值作为数据。根据本发明的实施例的一个方面的非易失性半导体存储器件还包括一个控制器，用于选择给定的一个存储单元，产生用于擦除数据的擦除脉冲，并将擦除脉冲提供给选择的存储单元。擦除脉冲具有根据到所选存储单元的访问路径长度指数地增加或减少的脉冲宽度。

108. 发明授权

US08318602B2 Nonvolatile semiconductor storage apparatus and method for manufacturing the same 有权
标题翻译：非易失性半导体存储装置及其制造方法
公开(公告)号：US08318602B2
公开(公告)日：2012-11-27
申请号：US13085622
申请日：2011-04-13
申请人： Masaru Kito , Hirofumi Inoue
发明人： Masaru Kito , Hirofumi Inoue
IPC分类号： H01L21/768
CPC分类号： H01L27/105 , G11C16/10 , H01L27/0207 , H01L27/0688 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582
摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage apparatus including: a substrate; a columnar semiconductor disposed perpendicular to the substrate; a charge storage laminated film disposed around the columnar semiconductor; a first conductor layer that is in contact with the charge storage laminated film and that has a first end portion having a first end face; a second conductor layer that is in contact with the charge storage laminated film, that is separated from the first conductor layer and that has a second end portion having a second end face; a first contact plug disposed on the first end face; and a second contact plug disposed on the second end face.
摘要翻译：根据本发明的一个方面，提供了一种非易失性半导体存储装置，包括：基板; 垂直于衬底设置的柱状半导体; 设置在所述柱状半导体周围的电荷存储层叠膜; 与所述电荷存储叠层膜接触并具有第一端部的第一导体层，所述第一端部具有第一端面; 与电荷存储叠层膜接触的第二导体层，其与第一导体层分离并且具有具有第二端面的第二端部; 设置在所述第一端面上的第一接触插塞; 以及设置在所述第二端面上的第二接触插塞。

109. 发明授权

US08183602B2 Nonvolatile semiconductor memory device including via-holes continuously formed through plural cell array layers 有权
标题翻译：包括通过多个单元阵列层连续形成的通孔的非易失性半导体存储器件
公开(公告)号：US08183602B2
公开(公告)日：2012-05-22
申请号：US12275682
申请日：2008-11-21
申请人： Hideyuki Tabata , Eiji Ito , Hirofumi Inoue
发明人： Hideyuki Tabata , Eiji Ito , Hirofumi Inoue
IPC分类号： H01L23/52
CPC分类号： H01L27/2481 , G11C13/00 , G11C13/0009 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/147 , H01L45/1675 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines indifferent cell array layers.
摘要翻译：非易失性半导体存储器件包括半导体衬底; 形成在所述半导体衬底上的单元阵列块，并且包括多个堆叠的单元阵列层，每个堆叠的单元阵列层具有多个第一线，与所述多条第一线交叉的多个第二线，以及在所述第一和第二线的两个交点处连接的存储单元线条以及在单元阵列层的堆叠方向上延伸的多个通孔，以将每个单元阵列层中的第一或第二线分别连接到半导体基板。通孔连续地形成在多个单元阵列层中，并且具有相同的下端位置和上端位置的多个通孔连接到第一或第二线不同的单元阵列层。

110. 发明申请

US20120012807A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120012807A1
公开(公告)日：2012-01-19
申请号：US13182095
申请日：2011-07-13
申请人： Takeshi YAMAGUCHI , Hirofumi Inoue , Reika Ichihara , Takayuki Tsukamoto , Takashi Shigeoka , Katsuyuki Sekine , Shinya Aoki
发明人： Takeshi YAMAGUCHI , Hirofumi Inoue , Reika Ichihara , Takayuki Tsukamoto , Takashi Shigeoka , Katsuyuki Sekine , Shinya Aoki
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , H01L27/2409 , H01L45/08 , H01L45/1233
摘要： A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.
摘要翻译：实施例中的半导体存储器件包括存储单元，每个存储单元设置在第一线和第二线之间，并且具有串联连接的可变电阻元件和开关元件。可变电阻元件包括可变电阻层，其被配置为在低电阻状态和高电阻状态之间改变其电阻值。可变电阻层由过渡金属氧化物构成。构成过渡金属氧化物的过渡金属和氧的比例沿着从第一线指向第二线的第一方向在1:1和1:2之间变化。

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