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101. 发明授权

US08652887B2 Multi-layer structures and process for fabricating semiconductor devices 有权
标题翻译：用于制造半导体器件的多层结构和工艺
公开(公告)号：US08652887B2
公开(公告)日：2014-02-18
申请号：US13416813
申请日：2012-03-09
申请人： Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
发明人： Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/76254 , H01L21/02238 , H01L21/32 , H01L21/84 , H01L27/1203
摘要： The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing.
摘要翻译：本发明涉及一种提供绝缘体上硅（SOI）堆叠的方法，其包括衬底层，衬底层上的第一氧化物层和第一氧化物层（BOX层）上的硅层。该方法包括提供SOI堆叠的至少一个第一区域，其中通过热氧化硅层的一部分并提供SOI堆叠的至少一个第二区域来减薄硅层，其中第一氧化物层（BOX层）被稀释通过退火。

102. 发明申请

US20120250444A1 PSEUDO-INVERTER CIRCUIT ON SeOI 有权
标题翻译： PSOUD上的PSEUDO-INVERTER电路
公开(公告)号：US20120250444A1
公开(公告)日：2012-10-04
申请号：US13495632
申请日：2012-06-13
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： G11C8/08 , G05F3/02
CPC分类号： G11C8/08 , G11C11/4085 , G11C2211/4016
摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
摘要翻译：在绝缘体上半导体衬底上制成的电路。该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

103. 发明申请

US20120231606A1 MULTI-LAYER STRUCTURES AND PROCESS FOR FABRICATING SEMICONDUCTOR DEVICES 有权
标题翻译：用于制造半导体器件的多层结构和工艺
公开(公告)号：US20120231606A1
公开(公告)日：2012-09-13
申请号：US13416813
申请日：2012-03-09
申请人： Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
发明人： Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
IPC分类号： H01L21/762
CPC分类号： H01L21/76254 , H01L21/02238 , H01L21/32 , H01L21/84 , H01L27/1203
摘要： The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing.
摘要翻译：本发明涉及一种提供绝缘体上硅（SOI）堆叠的方法，其包括衬底层，衬底层上的第一氧化物层和第一氧化物层（BOX层）上的硅层。该方法包括提供SOI堆叠的至少一个第一区域，其中通过热氧化硅层的一部分并提供SOI堆叠的至少一个第二区域来减薄硅层，其中第一氧化物层（BOX层）被稀释通过退火。

104. 发明申请

US20110260233A1 DEVICE COMPRISING A FIELD-EFFECT TRANSISTOR IN A SILICON-ON-INSULATOR 有权
标题翻译：包含绝缘体上的场效应晶体管的器件
公开(公告)号：US20110260233A1
公开(公告)日：2011-10-27
申请号：US12886421
申请日：2010-09-20
申请人： Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
发明人： Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
IPC分类号： H01L29/788 , H01L21/336 , H01L29/78
CPC分类号： H01L21/823462 , H01L21/823481 , H01L21/84 , H01L27/0705 , H01L27/1203 , H01L27/1207 , H01L29/7881
摘要： The present invention relates to a semiconductor device that has a semiconductor-on-insulator (SeOI) structure, which includes a substrate, an insulating layer such as an oxide layer on the substrate and a semiconductor layer on the insulating layer with a field-effect-transistor (FET) formed in the SeOI structure from the substrate and deposited layers, wherein the FET has a channel region in the substrate, a gate dielectric layer that is made from at least a part of the oxide layer of the SeOI structure; and a gate electrode that is formed at least partially from a part of the semiconductor layer of the SeOI structure. The invention further relates to a method of forming one or more field-effect-transistors or metal-oxide-semiconductor transistors from a semiconductor-on-insulator structure that involves patterning and etching the SeOI structure, forming shallow trench isolations, depositing insulating, metal or semiconductor layers, and removing mask and/or pattern layers.
摘要翻译：本发明涉及一种具有绝缘体上半导体（SeOI）结构的半导体器件，其包括衬底，绝缘层如衬底上的氧化物层和具有场效应的绝缘层上的半导体层 - 晶体管（FET），其从所述衬底和沉积层形成在所述SeOI结构中，其中所述FET在所述衬底中具有沟道区;栅极介电层，其由所述SeOI结构的所述氧化物层的至少一部分制成; 以及至少部分地由SeOI结构的半导体层的一部分形成的栅电极。本发明还涉及从绝缘体上半导体结构形成一个或多个场效应晶体管或金属氧化物半导体晶体管的方法，该方法包括图案化和蚀刻SeOI结构，形成浅沟槽隔离，沉积绝缘金属或半导体层，以及去除掩模和/或图案层。

105. 发明授权

US08035163B2 Low-cost double-structure substrates and methods for their manufacture 有权
标题翻译：低成本双层结构基材及其制造方法
公开(公告)号：US08035163B2
公开(公告)日：2011-10-11
申请号：US12470253
申请日：2009-05-21
申请人： Bich-Yen Nguyen , Carlos Mazure
发明人： Bich-Yen Nguyen , Carlos Mazure
IPC分类号： H01L29/66 , H01L21/30 , H01L21/46
CPC分类号： H01L21/76254 , H01L21/76256
摘要： In preferred embodiments, the invention provides substrates that include a support, a first insulating layer arranged on the support, a non-mono-crystalline semi-conducting layer arranged on the first insulating layer, a second insulating layer arranged on the non-mono-crystalline semi-conducting layer; and top layer disposed on the second insulating layer. Additionally, a first gate electrode can be formed on the top layer and a second gate electrode can be formed in the non-mono-crystalline semi-conducting layer. The invention also provides methods for manufacture of such substrates.
摘要翻译：在优选实施例中，本发明提供了包括支撑件，布置在支撑件上的第一绝缘层，布置在第一绝缘层上的非单晶半导体层的衬底，布置在非单晶半导体层上的第二绝缘层，结晶半导体层; 以及设置在第二绝缘层上的顶层。此外，可以在顶层上形成第一栅电极，并且可以在非单晶半导体层中形成第二栅电极。本发明还提供了制造这种基材的方法。

106. 发明申请

US20110233675A1 SRAM-TYPE MEMORY CELL 有权
标题翻译： SRAM型存储单元
公开(公告)号：US20110233675A1
公开(公告)日：2011-09-29
申请号：US13039167
申请日：2011-03-02
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/84 , H01L27/1203
摘要： An SRAM-type memory cell that includes a semiconductor on insulator substrate having a thin film of semiconductor material separated from a base substrate by an insulating layer; and six transistors such as two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters. Each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential. The first and second potentials can be modulated according to the type of cell control operation.
摘要翻译：一种SRAM型存储单元，包括绝缘体上半导体衬底，其具有通过绝缘层从基底衬底分离的半导体材料薄膜; 以及六个晶体管，例如两个存取晶体管，两个导通晶体管和两个电荷晶体管，其布置成与导通晶体管形成两个反向耦合的反相器。每个晶体管具有形成在通道下方的基底衬底中的后控制栅极，并且能够被偏置以便调制晶体管的阈值电压，第一背栅极线将存取晶体管的背控制栅极连接到第一电位和第二背栅极线，其将导通晶体管和电荷晶体管的背控制栅极连接到第二电位。第一和第二电位可以根据电池控制操作的类型进行调制。

107. 发明申请

US20110037150A1 SUBSTRATE COMPRISING DIFFERENT TYPES OF SURFACES AND METHOD FOR OBTAINING SUCH SUBSTRATES 审中-公开
标题翻译：包含不同类型表面的基板和用于获得这些基板的方法
公开(公告)号：US20110037150A1
公开(公告)日：2011-02-17
申请号：US12989474
申请日：2009-05-18
申请人： Bich-Yen Nguyen
发明人： Bich-Yen Nguyen
IPC分类号： H01L29/04 , G03F7/20 , H01L21/30
CPC分类号： H01L21/76254 , H01L21/76256
摘要： A support having a larger density of crystalline defects, an insulating layer disposed on a first region of a front face of the support, and a superficial layer disposed on the insulating layer. An additional layer can be disposed at least on a second region of the front face of the support has a thickness sufficient to bury crystalline defects of the support. A substrate can also include an epitaxial layer arranged at least over the first region of the front face of the support, between the support and the insulation layer. Also, a method of making the substrate by forming a masking layer on the first region of the superficial layer and removing the superficial layer and the insulating layer in the second region uncovered by the masking layer. The additional layer is formed in the second region and then planarized.
摘要翻译：具有较大结晶缺陷密度的支撑体，设置在支撑体正面的第一区域上的绝缘层和设置在绝缘层上的表面层。可以至少在支撑体的前表面的第二区域上设置附加层，其厚度足以埋设支撑体的结晶缺陷。衬底还可以包括布置在支撑体的前表面的至少第一区域之间，在支撑体和绝缘层之间的外延层。此外，通过在表层的第一区域上形成掩模层并除去由掩模层未覆盖的第二区域中的表层和绝缘层来制造衬底的方法。附加层形成在第二区域中，然后平坦化。

108. 发明授权

US07838345B2 Electronic device including semiconductor fins and a process for forming the electronic device 有权
标题翻译：包括半导体散热片的电子设备和用于形成电子设备的方法
公开(公告)号：US07838345B2
公开(公告)日：2010-11-23
申请号：US11416436
申请日：2006-05-02
申请人： Zhonghai Shi , Bich-Yen Nguyen , Héctor Sánchez
发明人： Zhonghai Shi , Bich-Yen Nguyen , Héctor Sánchez
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L29/66795
摘要： An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and contacting each of the first semiconductor fin and the second semiconductor fin along only a portion of length of each of the first semiconductor fin and the second semiconductor fin, respectively. In another aspect, a process for forming an electronic device can include forming a first semiconductor fin and a second semiconductor fin from a semiconductor layer, each of the first semiconductor fin and the second semiconductor fin spaced-apart from the other. The process can also include forming a bridge that contacts the first semiconductor fin and second semiconductor fin. The process can further include forming a conductive member, including a gate electrode, lying between the first semiconductor fin and second semiconductor fin.
摘要翻译：电子设备可以包括与另一个间隔开的第一半导体鳍片和第二半导体鳍片。电子设备还可以分别包括位于第一半导体鳍片和第二半导体鳍片之间并且分别仅与第一半导体鳍片和第二半导体鳍片的每一个的长度的一部分接触的桥接器。在另一方面，一种用于形成电子器件的方法可以包括从半导体层形成第一半导体鳍片和第二半导体鳍片，每个第一半导体鳍片和第二半导体鳍片彼此间隔开。该工艺还可以包括形成接触第一半导体鳍片和第二半导体鳍片的桥。该方法还可以包括形成位于第一半导体鳍片和第二半导体鳍片之间的包括栅电极的导电构件。

109. 发明申请

US20100059817A1 POWER MOSFET WITH A GATE STRUCTURE OF DIFFERENT MATERIAL 有权
标题翻译：具有不同材料门结构的功率MOSFET
公开(公告)号：US20100059817A1
公开(公告)日：2010-03-11
申请号：US12205438
申请日：2008-09-05
申请人： DANIEL PHAM , Bich-Yen Nguyen
发明人： DANIEL PHAM , Bich-Yen Nguyen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/28105 , H01L29/42372
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.
摘要翻译：半导体器件包括第一导电类型和第一掺杂浓度的半导体层。用作第一导电类型的漏极的第一半导体区域具有比半导体层更低的掺杂浓度，并且在半导体层之上。栅极电介质在第一半导体区域之上。栅极电介质上的栅极电极在中心部分的相对侧上具有含金属的中心部分和第一和第二硅部分。用作第二导电类型的沟道的第二半导体区域具有在第一硅部分下面的第一部分和栅极电介质。用作第一导电类型的源的第三半导体区域与第二半导体区域的第一部分横向相邻。置换硅的含金属中心部分将源极增加到漏极击穿电压。

110. 发明申请

US20090321873A1 LOW-COST SUBSTRATES HAVING HIGH-RESISTIVITY PROPERTIES AND METHODS FOR THEIR MANUFACTURE 有权
标题翻译：具有高电阻特性的低成本基板及其制造方法
公开(公告)号：US20090321873A1
公开(公告)日：2009-12-31
申请号：US12470152
申请日：2009-05-21
申请人： Bich-Yen Nguyen , Carlos Mazure
发明人： Bich-Yen Nguyen , Carlos Mazure
IPC分类号： H01L27/12 , H01L21/20
CPC分类号： H01L21/76251
摘要： In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates.
摘要翻译：在一个实施例中，本发明提供了被构造成使得在其顶层中制造的器件具有与在标准高电阻率衬底中制造的相同器件相似的性质的衬底。本发明的基板包括具有标准电阻率的支撑体，布置在支撑基板上的具有高电阻率，优选地大于约1000欧姆 - 厘米的半导体层，设置在高电阻率层上的绝缘层，以及顶层布置在绝缘层上。本发明还提供了制造这种基底的方法。

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