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101. 发明授权

US08946942B2 Robust semiconductor power devices with design to protect transistor cells with slower switching speed 有权
公开(公告)号：US08946942B2
公开(公告)日：2015-02-03
申请号：US12074327
申请日：2008-03-03
申请人： Sik K. Lui , Anup Bhalla
发明人： Sik K. Lui , Anup Bhalla
IPC分类号： H01H47/00 , H03K17/16 , H01L29/06 , H01L29/08 , H01L29/78
CPC分类号： H01H49/00 , H01L29/0696 , H01L29/0856 , H01L29/086 , H01L29/7803 , H01L29/7813 , H01L2924/0002 , H03K17/04123 , H03K17/08122 , H03K17/122 , H03K17/164 , H03K17/687 , Y10T29/49105 , Y10T307/747 , Y10T307/76 , H01L2924/00
摘要： This invention discloses a power switch that includes a fast-switch semiconductor power device and a slow-switch semiconductor power device controllable to turn on and off a current transmitting therethrough. The slow-switch semiconductor power device further includes a ballasting resistor for increasing a device robustness of the slow switch semiconductor power device. In an exemplary embodiment, the fast-switch semiconductor power device includes a fast switch metal oxide semiconductor field effect transistor (MOSFET) and the slow-switch semiconductor power device includes a slow switch MOSFET wherein the slow switch MOSFET further includes a source ballasting resistor.

102. 发明申请

US20140332882A1 TRENCH JUNCTION BARRIER CONTROLLED SCHOTTKY 有权
标题翻译： TRENCH JUNCTION BARRIER控制的肖特
公开(公告)号：US20140332882A1
公开(公告)日：2014-11-13
申请号：US13892312
申请日：2013-05-13
申请人： SiK K. Lui , Anup Bhalla
发明人： SiK K. Lui , Anup Bhalla
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7839 , H01L29/0619 , H01L29/0623 , H01L29/66143 , H01L29/66712 , H01L29/7806 , H01L29/7813 , H01L29/872
摘要： A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.
摘要翻译：一种用于制造肖特基二极管的方法，包括以下步骤：1）提供具有与第一导电类型相反的第二导电类型的掺杂剂的区域，以在所述第一导电类型的半导体衬底中形成顶部掺杂区域; 2）通过顶部掺杂区域提供沟槽至预定深度并提供第二导电类型的掺杂剂以形成第二导电类型的底部掺杂区域; 以及3）将至少从顶部掺杂区域的底部延伸到底部掺杂区域的顶部的沟槽的侧壁上的肖特基势垒金属层衬里。

103. 发明申请

US20110204440A1 Shielded gate trench (SGT) mosfet devices and manufacturing processes 有权
标题翻译：屏蔽栅沟槽（SGT）mosfet器件和制造工艺
公开(公告)号：US20110204440A1
公开(公告)日：2011-08-25
申请号：US13066947
申请日：2011-04-28
申请人： Anup Bhalla , Sik K. Lui
发明人： Anup Bhalla , Sik K. Lui
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/407 , H01L29/66734 , H01L29/7811
摘要： This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench. The semiconductor power device further includes an insulation protective layer disposed on top of the semiconductor power device having a plurality of source openings on top of the source region and the source connecting trench provided for electrically connecting to the source metal and at least a gate opening provided for electrically connecting the gate pad to the trenched gate.
摘要翻译：本发明公开了一种半导体功率器件，其包括由在半导体衬底中开口的沟槽围绕的多个功率晶体管单元。构成活性单元的单元中的至少一个具有与沟槽栅极相邻设置的源极区域，该沟槽栅极电连接到栅极焊盘并围绕电池。沟槽栅极还具有填充有栅极材料的底部屏蔽电极，栅极材料设置在沟槽栅极下方并与沟槽栅极绝缘。构成由沟槽围绕的源极接触单元中的至少一个具有用作源极连接沟槽的部分的单元填充有栅极材料，用于电连接底部屏蔽电极和直接设置在源极连接沟槽顶部的源极金属源连接沟槽。半导体功率器件还包括设置在半导体功率器件的顶部上的绝缘保护层，其具有在源极区域的顶部上的多个源极开口和设置用于电连接到源极金属的源极连接沟槽和至少提供的栅极开口用于将栅极焊盘电连接到沟槽栅极。

104. 发明申请

US20110042724A1 Trenched mosfets with part of the device formed on a (110) crystal plane 审中-公开
标题翻译：在110平面上形成有部分器件的沟槽式mosfet
公开(公告)号：US20110042724A1
公开(公告)日：2011-02-24
申请号：US11634031
申请日：2009-04-20
申请人： Anup Bhalla , Sik K. Lui , Sung-Shan Tai
发明人： Anup Bhalla , Sik K. Lui , Sung-Shan Tai
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L24/33 , H01L29/045 , H01L29/4236 , H01L29/66734 , H01L29/7811 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00
摘要： This invention discloses an improved MOSFET devices manufactured with a trenched gate by forming the sidewalls of the trench on a (110) crystal orientation of a semiconductor substrate. The trench is covering with a dielectric oxide layer along the sidewalls and the bottom surface or the termination of the trench formed along different crystal orientations of the semiconductor substrate. Special manufacturing processes such as oxide annealing process, special mask or SOG processes are implemented to overcome the limitations of the non-uniform dielectric layer growth.
摘要翻译：本发明公开了通过在半导体衬底的（110）晶体取向上形成沟槽的侧壁而制造的具有沟槽栅极的改进的MOSFET器件。沟槽沿着沿着半导体衬底的不同晶体取向形成的沟槽的侧壁和底表面或沟槽的终端覆盖电介质氧化物层。实施诸如氧化物退火工艺，特殊掩模或SOG工艺的特殊制造工艺以克服非均匀介电层生长的限制。

105. 发明申请

US20100258897A1 Trench junction barrier controlled Schottky 有权
标题翻译：沟槽接口屏障控制肖特基
公开(公告)号：US20100258897A1
公开(公告)日：2010-10-14
申请号：US12802790
申请日：2010-06-14
申请人： Sik K. Lui , Anup Bhalla
发明人： Sik K. Lui , Anup Bhalla
IPC分类号： H01L29/872 , H01L21/329
CPC分类号： H01L29/66727 , H01L29/0623 , H01L29/1095 , H01L29/407 , H01L29/66143 , H01L29/66734 , H01L29/7811 , H01L29/782 , H01L29/8725
摘要： A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.
摘要翻译：一种用于制造肖特基二极管的方法，包括以下步骤：1）提供具有与第一导电类型相反的第二导电类型的掺杂剂的区域，以在所述第一导电类型的半导体衬底中形成顶部掺杂区域; 2）通过顶部掺杂区域提供沟槽至预定深度并提供第二导电类型的掺杂剂以形成第二导电类型的底部掺杂区域; 以及3）将至少从顶部掺杂区域的底部延伸到底部掺杂区域的顶部的沟槽的侧壁上的肖特基势垒金属层衬里。

106. 发明授权

US07764105B2 MOSFET for synchronous rectification 有权
标题翻译： MOSFET用于同步整流
公开(公告)号：US07764105B2
公开(公告)日：2010-07-27
申请号：US12154948
申请日：2008-05-27
申请人： Anup Bhalla , Sik K. Lui
发明人： Anup Bhalla , Sik K. Lui
IPC分类号： H03K5/08
CPC分类号： H01L27/088 , H01L27/0629 , H01L29/7803 , H01L29/7813 , H01L2223/6644 , H01L2224/16145 , H01L2224/45144 , H01L2224/48247 , H03K17/165 , H01L2924/00
摘要： This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of the MOSFET device. The inadvertent turning on of the MOSFET may occur when a large voltage transient occurs at the drain of the MOSFET device. By connecting the gate of the shunt FET to the drain of the MOSFET device, a low impedance path is provided at the right point of time during the circuit operation to shunt the current without requiring any external circuitry.
摘要翻译：本发明公开了一种新的MOSFET器件。 MOSFET器件具有通过将低阻抗的并联FET连接到MOSFET器件而实现的改进的操作特性。并联FET分流瞬态电流。分流FET用于防止MOSFET器件无意中导通。当在MOSFET器件的漏极处发生大的电压瞬变时，可能会发生MOSFET的无意开启。通过将分流FET的栅极连接到MOSFET器件的漏极，在电路操作期间在正确的时间点提供低阻抗路径，以分流电流而不需要任何外部电路。

107. 发明授权

US07737522B2 Trench junction barrier controlled Schottky device with top and bottom doped regions for enhancing forward current in a vertical direction 有权
标题翻译：具有顶部和底部掺杂区域的沟槽结势垒控制肖特基器件，用于在垂直方向上增强正向电流
公开(公告)号：US07737522B2
公开(公告)日：2010-06-15
申请号：US11541189
申请日：2006-09-30
申请人： Sik K Lui , Anup Bhalla
发明人： Sik K Lui , Anup Bhalla
IPC分类号： H01L29/47 , H01L29/872
CPC分类号： H01L29/66727 , H01L29/0623 , H01L29/1095 , H01L29/407 , H01L29/66143 , H01L29/66734 , H01L29/7811 , H01L29/782 , H01L29/8725
摘要： A Schottky diode includes at least a trenched opened in a semiconductor substrate doped with a dopant of a first conductivity type wherein the trench is filled with a Schottky junction barrier metal. The Schottky diode further includes one or more dopant region of a second conductivity type surrounding sidewalls of the trench distributed along the depth of the trench for shielding a reverse leakage current through the sidewalls of the trench. The Schottky diode further includes a bottom-doped region of the second conductivity type surrounding a bottom surface of the trench and a top-doped region of the second conductivity type surrounding a top portion of the sidewalls of the trench. In a preferred embodiment, the first conductivity type is a N-type conductivity type and the middle-depth dopant region comprising a P-dopant region.
摘要翻译：肖特基二极管包括在掺杂有第一导电类型的掺杂剂的半导体衬底中开放的至少沟槽，其中沟槽填充有肖特基结阻挡金属。所述肖特基二极管还包括一个或多个第二导电类型的掺杂区，该沟道围绕所述沟槽的深度分布，用于屏蔽穿过沟槽的侧壁的反向漏电流。肖特基二极管还包括围绕沟槽的底表面的第二导电类型的底部掺杂区域和围绕沟槽的侧壁的顶部的第二导电类型的顶部掺杂区域。在优选实施例中，第一导电类型是N型导电类型，并且中间深度掺杂区包含P掺杂区域。

108. 发明授权

US07671662B2 Thermally stable semiconductor power device 有权
标题翻译：热稳定的半导体功率器件
公开(公告)号：US07671662B2
公开(公告)日：2010-03-02
申请号：US12290270
申请日：2008-10-28
申请人： Sik K Lui , Anup Bhalla , Sanjay Havanur
发明人： Sik K Lui , Anup Bhalla , Sanjay Havanur
IPC分类号： H01L35/00
CPC分类号： H01L29/7813 , H01L27/0255 , H01L29/0696 , H01L29/7803 , H01L29/7804 , H03K17/08122 , H03K2017/0806
摘要： A semiconductor power device includes a circuit to provide a gate signal wherein the gate signal has a negative temperature coefficient of gate driving voltage for decreasing a gate driving voltage with an increase temperature whereby the semiconductor power device has a net Ids temperature coefficient that is less than or equal to zero. In an exemplary embodiment, the gate voltage driver includes a diode that has a negative forward voltage temperature coefficient connected between a gate and a source of the semiconductor power device. In another embodiment, the gate voltage is integrated with the semiconductor power device manufactured as part of an integrated circuit with the semiconductor power device.
摘要翻译：半导体功率器件包括提供栅极信号的电路，其中栅极信号具有负温度系数的栅极驱动电压，用于随温度升高而降低栅极驱动电压，由此半导体功率器件的净Ids温度系数小于或等于零。在示例性实施例中，栅极电压驱动器包括具有连接在半导体功率器件的栅极和源极之间的正向正向电压温度系数的二极管。在另一个实施例中，栅极电压与作为与半导体功率器件的集成电路的一部分制造的半导体功率器件集成。

109. 发明授权

US07633140B2 Inverted J-lead for power devices 有权
标题翻译：功率器件的倒置J型引线
公开(公告)号：US07633140B2
公开(公告)日：2009-12-15
申请号：US10732181
申请日：2003-12-09
申请人： Leeshawn Luo , Anup Bhalla , Sik K. Lui , Yueh-Se Ho , Mike F. Chang , Xiao Tiang Zhang
发明人： Leeshawn Luo , Anup Bhalla , Sik K. Lui , Yueh-Se Ho , Mike F. Chang , Xiao Tiang Zhang
IPC分类号： H01L23/495
CPC分类号： H01L24/48 , H01L23/49555 , H01L23/49562 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L24/49 , H01L24/73 , H01L2224/05552 , H01L2224/05553 , H01L2224/05599 , H01L2224/0603 , H01L2224/32245 , H01L2224/371 , H01L2224/37599 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48472 , H01L2224/49111 , H01L2224/49171 , H01L2224/73221 , H01L2224/73265 , H01L2224/84801 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/0106 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package includes a lead frame having a plurality of leads and a lead frame pad, the lead frame pad including a die coupled thereto, at least one of the plurality of leads having an external portion sloped upwards relative to a bottom surface of the package, metal connectors connecting the die to the plurality of leads, and a resin body encapsulating the die, metal connectors and at least a portion of the lead frame.
摘要翻译：半导体封装包括具有多个引线和引线框架焊盘的引线框架，所述引线框架焊盘包括耦合到其上的管芯，所述多个引线中的至少一个引线具有相对于所述封装的底表面向上倾斜的外部部分将模具连接到多个引线的金属连接器以及封装模具，金属连接器和引线框架的至少一部分的树脂体。

110. 发明授权

US07535021B2 Calibration technique for measuring gate resistance of power MOS gate device at water level 有权
标题翻译：功率MOS栅极器件水位栅极电阻的校准技术
公开(公告)号：US07535021B2
公开(公告)日：2009-05-19
申请号：US11265363
申请日：2005-11-01
申请人： Anup Bhalla , Sik K. Lui , Daniel Ng
发明人： Anup Bhalla , Sik K. Lui , Daniel Ng
IPC分类号： H01L23/58
CPC分类号： H04L63/102 , G01R31/2625 , G01R31/2884 , G01R35/005 , H01L22/14 , H01L2924/0002 , H04L63/08 , H01L2924/00
摘要： This invention discloses a method for calibrating a gate resistance measurement of a semiconductor power device that includes a step of forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of semiconductor power chips and measuring a resistance and a capacitance of the RC network to prepare for carrying out a wafer-level measurement calibration of the semiconductor power device. The method further includes a step of connecting a probe card to a set of contact pads on the semiconductor wafer for carrying out the wafer-level measurement calibration followed by performing a gate resistance Rg measurement for the semiconductor power chips.
摘要翻译：本发明公开了一种用于校准半导体功率器件的栅极电阻测量的方法，包括在与多个半导体功率芯片相邻的半导体晶片上的测试区域上形成RC网络的步骤，并测量电阻和电容 RC网络，准备进行半导体功率器件的晶圆级测量校准。该方法还包括将探针卡连接到半导体晶片上的一组接触焊盘，以执行晶片级测量校准，然后对半导体功率芯片执行栅极电阻Rg测量。

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