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101. 发明申请

US20070170507A1 STRUCTURE AND METHOD FOR MANUFACTURING PLANAR STRAINED Si/SiGe SUBSTRATE WITH MULTIPLE ORIENTATIONS AND DIFFERENT STRESS LEVELS 审中-公开
标题翻译：用于制造具有多个方位和不同应力水平的平面应变Si / SiGe衬底的结构和方法
公开(公告)号：US20070170507A1
公开(公告)日：2007-07-26
申请号：US11693377
申请日：2007-03-29
申请人： Huilong Zhu , Bruce Doris , Philip Oldiges , Meikei Ieong , Min Yang , Huajie Chen
发明人： Huilong Zhu , Bruce Doris , Philip Oldiges , Meikei Ieong , Min Yang , Huajie Chen
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/84 , H01L27/1207 , Y10S438/938
摘要： The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation material; forming a second concentration of the lattice modifying material atop the second orientation material; intermixing the first concentration of lattice modifying material with the first orientation material to produce a first lattice dimension surface and the second concentration of lattice modifying material the second orientation material to produce a second lattice dimension surface; and forming a first strained semiconducting layer atop the first lattice dimension surface and a second strained semiconducting layer atop the second lattice dimension surface.
摘要翻译：本发明提供一种形成半导体衬底的方法，包括以下步骤：提供具有包括第一取向材料的第一器件区域和具有第二取向材料的第二器件区域的初始结构; 在所述第一取向材料的顶部上形成晶格改性材料的第一浓度; 在所述第二取向材料的顶部上形成所述晶格改性材料的第二浓度; 将所述晶格修饰材料的第一浓度与所述第一取向材料混合以产生第一晶格尺寸表面，并且所述第二浓度的晶格修饰材料形成所述第二取向材料以产生第二晶格尺寸表面; 以及在所述第一晶格尺寸表面上方形成第一应变半导体层和在所述第二晶格尺寸表面顶部形成第二应变半导体层。

102. 发明授权

US07135724B2 Structure and method for making strained channel field effect transistor using sacrificial spacer 有权
标题翻译：使用牺牲隔离层制造应变通道场效应晶体管的结构和方法
公开(公告)号：US07135724B2
公开(公告)日：2006-11-14
申请号：US10711637
申请日：2004-09-29
申请人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner A. Rausch , Tsutomu Sato , Henry K. Utomo
发明人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner A. Rausch , Tsutomu Sato , Henry K. Utomo
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/28052 , H01L21/28079 , H01L21/7624 , H01L29/1045 , H01L29/165 , H01L29/4933 , H01L29/495 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.
摘要翻译：提供场效应晶体管（“FET”），其包括覆盖衬底的单晶半导体区域的栅极堆叠，设置在所述栅极堆叠的侧壁上的一对第一间隔区，以及基本上由单个晶体半导体合金，其设置在栅叠层的相对侧上。每个半导体合金区域与栅极叠层隔开第一距离。 FET的源极区域和漏极区域至少部分地设置在半导体合金区域的相应半导体合金区域中，使得源极区域和漏极区域之间的距离与栅极叠层间隔开第二距离，第一间隔物，第二距离与第一距离不同。

103. 发明申请

US20060172495A1 STRUCTURE AND METHOD FOR MANUFACTURING PLANAR STRAINED Si/SiGe SUBSTRATE WITH MULTIPLE ORIENTATIONS AND DIFFERENT STRESS LEVELS 失效
标题翻译：用于制造具有多个方位和不同应力水平的平面应变Si / SiGe衬底的结构和方法
公开(公告)号：US20060172495A1
公开(公告)日：2006-08-03
申请号：US10905978
申请日：2005-01-28
申请人： Huilong Zhu , Bruce Doris , Philip Oldiges , Meikel Ioeng , Min Yang , Huajie Chen
发明人： Huilong Zhu , Bruce Doris , Philip Oldiges , Meikel Ioeng , Min Yang , Huajie Chen
IPC分类号： H01L21/8234
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/84 , H01L27/1207 , Y10S438/938
摘要： The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation material; forming a second concentration of the lattice modifying material atop the second orientation material; intermixing the first concentration of lattice modifying material with the first orientation material to produce a first lattice dimension surface and the second concentration of lattice modifying material the second orientation material to produce a second lattice dimension surface; and forming a first strained semiconducting layer atop the first lattice dimension surface and a second strained semiconducting layer atop the second lattice dimension surface.
摘要翻译：本发明提供一种形成半导体衬底的方法，包括以下步骤：提供具有包括第一取向材料的第一器件区域和具有第二取向材料的第二器件区域的初始结构; 在所述第一取向材料的顶部上形成晶格改性材料的第一浓度; 在所述第二取向材料的顶部上形成所述晶格改性材料的第二浓度; 将所述晶格修饰材料的第一浓度与所述第一取向材料混合以产生第一晶格尺寸表面，并且所述第二浓度的晶格修饰材料形成所述第二取向材料以产生第二晶格尺寸表面; 以及在所述第一晶格尺寸表面上方形成第一应变半导体层和在所述第二晶格尺寸表面顶部形成第二应变半导体层。

104. 发明申请

US20060157706A1 Structure and method for manufacturing strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels 失效
标题翻译：用于制造具有杂化晶体取向和不同应力水平的应变硅绝缘体上基板的结构和方法
公开(公告)号：US20060157706A1
公开(公告)日：2006-07-20
申请号：US11037622
申请日：2005-01-18
申请人： Huilong Zhu , Bruce Doris , Huajie Chen , Patricia Mooney , Stephen Bedell
发明人： Huilong Zhu , Bruce Doris , Huajie Chen , Patricia Mooney , Stephen Bedell
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L21/84
摘要： The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.
摘要翻译：本发明提供了具有多个结晶取向的应变Si直接绝缘体（SSDOI）基板及其形成方法。广义上，但是具体来说，本发明的SSDOI基板包括基板; 衬底顶部的绝缘层; 以及位于顶部并与绝缘层直接接触的半导体层，所述半导体层包括第一应变Si区和第二应变Si区; 其中所述第一应变Si区具有不同于所述第二应变Si区的晶体取向，并且所述第一应变Si区具有与所述第二应变Si区相同或不同的晶体取向。第一应变Si区域的应变水平与第二应变Si区域的应变水平不同。

105. 发明申请

US20060151837A1 IN SITU DOPED EMBEDDED SIGE EXTENSION AND SOURCE/DRAIN FOR ENHANCED PFET PERFORMANCE 有权
标题翻译：采用SITU DEDED嵌入式信号扩展和源/漏极增强PFET性能
公开(公告)号：US20060151837A1
公开(公告)日：2006-07-13
申请号：US10905598
申请日：2005-01-12
申请人： Huajie Chen , Dureseti Chidambarrao , Siddhartha Panda , Sang-Hyun Oh , Henry Utomo , Werner Rausch
发明人： Huajie Chen , Dureseti Chidambarrao , Siddhartha Panda , Sang-Hyun Oh , Henry Utomo , Werner Rausch
IPC分类号： H01L29/94
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.
摘要翻译：公开了一种集成电路结构以及在衬底上具有衬底和P型和N型晶体管的结构的方法。 N型晶体管延伸和源极/漏极区域包括注入到衬底中的掺杂剂。 P型晶体管延伸和源极/漏极区域部分地包括应变外延硅锗，其中应变硅锗包括两层，顶层比底层更靠近栅极堆叠。应变硅锗被原位掺杂并在沟道区域上产生纵向应力。

106. 发明授权

US07071103B2 Chemical treatment to retard diffusion in a semiconductor overlayer 失效
标题翻译：化学处理以延缓半导体覆层中的扩散
公开(公告)号：US07071103B2
公开(公告)日：2006-07-04
申请号：US10710737
申请日：2004-07-30
申请人： Kevin K. Chan , Huajie Chen , Michael A. Gribelyuk , Judson R. Holt , Woo-Hyeong Lee , Ryan M. Mitchell , Renee T. Mo , Dan M. Mocuta , Werner A. Rausch , Paul A. Ronsheim , Henry K. Utomo
发明人： Kevin K. Chan , Huajie Chen , Michael A. Gribelyuk , Judson R. Holt , Woo-Hyeong Lee , Ryan M. Mitchell , Renee T. Mo , Dan M. Mocuta , Werner A. Rausch , Paul A. Ronsheim , Henry K. Utomo
IPC分类号： H01L21/44
CPC分类号： H01L21/28044 , H01L21/324
摘要： The present invention provides a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa. In the method of the present invention, diffusion of dopants from the first semiconductor into the overlayer or vice versa is retarded by forming a monolayer comprising carbon and oxygen between the two layers. The monolayer is formed in the present invention utilizing a chemical pretreatment process in which a solution including iodine and an alcohol such as methanol is employed.
摘要翻译：本发明提供了一种用于延迟掺杂剂从第一材料层（通常为半导体）扩散到覆盖层或反之亦然的方法。在本发明的方法中，通过在两层之间形成包含碳和氧的单层来延缓掺杂剂从第一半导体扩散到覆层中或反之亦然。使用化学预处理方法在本发明中形成单层，其中使用包括碘和醇如甲醇的溶液。

107. 发明授权

US06989058B2 Use of thin SOI to inhibit relaxation of SiGe layers 有权
标题翻译：使用薄SOI抑制SiGe层的弛豫
公开(公告)号：US06989058B2
公开(公告)日：2006-01-24
申请号：US10654232
申请日：2003-09-03
申请人： Stephen W. Bedell , Huajie Chen , Keith E. Fogel , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Keith E. Fogel , Devendra K. Sadana
IPC分类号： C30B25/02
CPC分类号： H01L21/7624 , C30B29/52 , C30B31/02 , H01L21/02381 , H01L21/02532 , H01L21/02694 , Y10T428/24917
摘要： High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.
摘要翻译：在具有大约等于或小于等于或等于SOI层的SOI层的SOI衬底上形成高质量的亚稳态SiGe合金，与形成在较厚SOI衬底上的相同SiGe层相比，SiGe层可以保持基本上完全变形，并随后在高温下退火和/或氧化温度。因此，本发明提供了一种通过在薄的，清洁的和高质量的SOI衬底上生长它们来“挫败”亚稳应变的SiGe层的方法。

108. 发明授权

US06958286B2 Method of preventing surface roughening during hydrogen prebake of SiGe substrates 失效
公开(公告)号：US06958286B2
公开(公告)日：2005-10-25
申请号：US10751208
申请日：2004-01-02
申请人： Huajie Chen , Dan M. Mocuta , Richard J. Murphy , Stephan W. Bedell , Devendra K. Sadana
发明人： Huajie Chen , Dan M. Mocuta , Richard J. Murphy , Stephan W. Bedell , Devendra K. Sadana
IPC分类号： C30B25/02 , C30B29/06 , C30B29/52 , H01L21/20 , H01L21/205 , H01L21/28 , H01L21/306 , H01L21/3205 , H01L21/36 , H01L21/44
CPC分类号： H01L21/02046 , C30B25/02 , C30B29/06 , C30B29/52 , H01L21/02052 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02658 , H01L21/02661 , Y10S438/933
摘要： The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves a first amount of oxygen (typically 1×1013−1×1015/cm2 of oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The invention then performs a hydrogen pre-bake process which heats the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface sufficiently to remove additional oxygen from the surface and leave a second amount of oxygen, less than the first amount, on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The heating process leaves an amount of at least 5×1012/cm2 of oxygen (typically, between approximately 1×1013/cm2 and approximately 5×1013/cm2 of oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. By leaving a small amount of oxygen on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface, the heating processes avoid changing the roughness of the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. Then the process of epitaxially growing the epitaxial silicon-containing layer on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface is performed.

109. 发明申请

US20050158931A1 Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions 失效
标题翻译：制造应变半导体晶体管的方法，其具有位于源极和漏极区域之下的晶格失配的半导体区域
公开(公告)号：US20050158931A1
公开(公告)日：2005-07-21
申请号：US11081271
申请日：2005-03-16
申请人： Huajie Chen , Dureseti Chidambarrao , Oleg Gluschenkov , An Steegen , Haining Yang
发明人： Huajie Chen , Dureseti Chidambarrao , Oleg Gluschenkov , An Steegen , Haining Yang
IPC分类号： H01L21/20 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L21/337
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02636 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L27/1203 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.
摘要翻译：提供集成电路的p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。第一应变施加到PFET的沟道区，而不是NFET通过位于仅仅PFET而不是NFET的源极和漏极区域中的晶格不匹配的半导体层，例如硅锗。提供制造PFET和NFET的工艺。在区域中蚀刻沟槽以成为PFET的源极和漏极区域，并且将晶格失配的硅锗层外延生长以向与其相邻的PFET的沟道区域施加应变。可以在硅锗层上生长一层硅层，并从硅层形成硅化物以提供低电阻源极和漏极区域。

110. 发明申请

US20050148162A1 Method of preventing surface roughening during hydrogen pre-bake of SiGe substrates using chlorine containing gases 审中-公开
标题翻译：在使用含氯气体的SiGe衬底的氢预烘烤期间防止表面粗糙化的方法
公开(公告)号：US20050148162A1
公开(公告)日：2005-07-07
申请号：US10751207
申请日：2004-01-02
申请人： Huajie Chen , Dan Mocuta , Richard Murphy , Stephen Bedell , Devendra Sadana
发明人： Huajie Chen , Dan Mocuta , Richard Murphy , Stephen Bedell , Devendra Sadana
IPC分类号： C30B25/02 , C30B29/52 , H01L21/20 , H01L21/205 , H01L21/306 , H01L21/36 , H01L21/44
CPC分类号： H01L21/02046 , C30B25/02 , C30B29/52 , H01L21/02052 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02658 , H01L21/02661
摘要： The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves only a sub-monolayer of oxygen (typically 1×1013-1×1015/cm2 of oxygen) at the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The invention then performs a hydrogen pre-bake process in a chlorine containing environment which heats the silicon germanium, strained silicon, or thin silicon-on-insulator surface sufficiently to remove the remaining oxygen from the surface. By introducing a small amount of chlorine containing gases, the heating processes avoid changing the roughness of the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. Then the process of epitaxially growing the epitaxial silicon-containing layer on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface is performed.
摘要翻译：本发明在硅锗，图案化的应变硅或图案化的绝缘体上硅表面上形成外延含硅层，并避免产生外延含硅层生长的粗糙表面。为了避免产生粗糙表面，本发明首先对硅锗，图案化应变硅或图案化的绝缘体上硅表面进行氢氟酸蚀刻工艺。该蚀刻工艺从表面除去大部分氧化物，并且仅留下氧气的亚单层（通常为1×10 13/1×10 15 / cm 2以上）的氧），图案化的应变硅或图案化的绝缘体上硅表面。然后，本发明在含氯环境中进行氢预烘烤过程，其中充分加热硅锗，应变硅或薄的绝缘体上硅表面以从表面除去剩余的氧。通过引入少量的含氯气体，加热过程避免改变硅锗，图案化的应变硅或图案化的绝缘体上硅表面的粗糙度。然后进行外延生长硅锗，图案化应变硅或图案化硅绝缘体表面上的外延硅含量层的工艺。

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