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101. 发明授权

US08163640B2 Metal gate compatible electrical fuse 失效
标题翻译：金属门兼容电保险丝
公开(公告)号：US08163640B2
公开(公告)日：2012-04-24
申请号：US11874385
申请日：2007-10-18
申请人： Xiangdong Chen , Deok-kee Kim , Chandrasekharan Kothandaraman
发明人： Xiangdong Chen , Deok-kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L27/06 , H01L21/3205
CPC分类号： H01L27/0617 , H01L23/5256 , H01L29/4238 , H01L2924/0002 , H01L2924/00
摘要： A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the semiconductor substrate containing a vertically abutting stack of the metal gate layer and the polycrystalline semiconductor layer. A material stack in the shape of an electrical fuse is formed in another region of the semiconductor substrate containing a vertical stack of the metal gate layer, the dielectric material portion, and the polycrystalline semiconductor layer. After metallization of the polycrystalline semiconductor layer, an electrical fuse containing a polycrystalline semiconductor portion and a metal semiconductor alloy portion is formed over the dielectric material portion that separates the electrical fuse from the metal gate layer.
摘要翻译：在用于金属栅电极的金属栅极层上形成电介质材料层，然后通过光刻图案形成电介质材料部分，随后在其上形成多晶半导体层。在包含金属栅极层和多晶半导体层的垂直邻接堆叠的半导体基板的区域中形成采用金属栅电极的半导体器件。形成有电熔丝形状的材料堆叠形成在半导体衬底的另一区域中，该区域包含金属栅极层，电介质材料部分和多晶半导体层的垂直叠层。在多晶半导体层的金属化之后，在将电熔丝与金属栅极层分离开的电介质材料部分上形成包含多晶半导体部分和金属半导体合金部分的电熔丝。

102. 发明申请

US20110210397A1 One-time programmable semiconductor device 有权
标题翻译：一次性可编程半导体器件
公开(公告)号：US20110210397A1
公开(公告)日：2011-09-01
申请号：US12660603
申请日：2010-03-01
申请人： Frank Hui , Xiangdong Chen
发明人： Frank Hui , Xiangdong Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/112 , H01L27/11206
摘要： According to one embodiment, a one-time programmable (OTP) semiconductor device includes a programming dielectric under a patterned electrode and over an implant region, where the programming dielectric forms a programming region of the OTP semiconductor device. The OTP semiconductor device further includes an isolation region laterally separating the programming dielectric from a coupled semiconductor structure, where the isolation region can be used in conjunction with the patterned electrode and the implant region to protect the coupled semiconductor structure. In one embodiment, the programming dielectric comprises a gate dielectric. In another embodiment, the electrode and implant regions are doped to be electrochemically similar.
摘要翻译：根据一个实施例，一次性可编程（OTP）半导体器件包括在图案化电极下面和注入区域上的编程电介质，其中编程电介质形成OTP半导体器件的编程区域。 OTP半导体器件还包括将编程电介质横向分离成耦合的半导体结构的隔离区，其中隔离区域可与图案化电极和注入区域一起使用以保护耦合的半导体结构。在一个实施例中，编程电介质包括栅极电介质。在另一个实施例中，电极和注入区被掺杂以在电化学上相似。

103. 发明申请

US20110210388A1 Integrated native device without a halo implanted channel region and method for its fabrication 有权
标题翻译：没有光晕注入通道区域的集成本机器件及其制造方法
公开(公告)号：US20110210388A1
公开(公告)日：2011-09-01
申请号：US12660618
申请日：2010-03-01
申请人： Xiangdong Chen , Akira Ito
发明人： Xiangdong Chen , Akira Ito
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823412 , H01L21/26586 , H01L29/1083
摘要： According to one embodiment, a semiconductor structure including an integrated native device without a halo implanted channel region comprises an arrangement of semiconductor devices formed over a common substrate, the arrangement includes native devices disposed substantially perpendicular to non-native devices, wherein each of the native and non-native devices includes a respective channel region. The arrangement is configured to prevent formation of halo implants in the native device channel regions during halo implantation of the non-native device channel regions. In one embodiment, the disclosed native devices comprise native transistors capable of avoiding threshold voltage roll-up for channel lengths less than approximately 0.5 um.
摘要翻译：根据一个实施例，包括没有晕圈注入沟道区的集成本机器件的半导体结构包括形成在公共衬底上的半导体器件的布置，该布置包括基本上垂直于非本地器件设置的天然器件，其中每个天线非本地设备包括相应的信道区域。该配置被配置为在非天然器件沟道区域的晕圈植入期间防止在天然器件沟道区域中形成晕轮植入物。在一个实施例中，所公开的天线装置包括天线晶体管，其能够避免小于约0.5μm的信道长度的阈值电压累加。

104. 发明申请

US20110210384A1 Scalable integrated MIM capacitor using gate metal 有权
标题翻译：使用栅极金属的可扩展集成MIM电容器
公开(公告)号：US20110210384A1
公开(公告)日：2011-09-01
申请号：US12660619
申请日：2010-03-01
申请人： Wei Xia , Xiangdong Chen
发明人： Wei Xia , Xiangdong Chen
IPC分类号： H01L27/06 , H01L21/02 , H01L21/8234
CPC分类号： H01L27/0629 , H01L23/5223 , H01L27/0805 , H01L27/0811 , H01L27/092 , H01L28/60 , H01L28/65 , H01L29/4232 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a scalable integrated MIM capacitor in a semiconductor die includes a high-k dielectric segment over a substrate and a metal segment over the high-k dielectric segment, where the metal segment forms a capacitor terminal of the integrated MIM capacitor. The capacitor further includes a filler laterally separating consecutive capacitor terminals, where the filler can be used as a capacitor dielectric of the integrated MIM capacitor. In one embodiment, the metal segment comprises a gate metal. In another embodiment, the integrated MIM capacitor is formed substantially concurrently with one or more transistors without requiring additional fabrication process steps.
摘要翻译：根据一个实施例，半导体管芯中的可扩展集成MIM电容器包括衬底上的高k电介质段和高k电介质段上的金属段，其中金属段形成集成MIM电容器的电容器端子。电容器还包括横向分离连续的电容器端子的填料，其中填料可以用作集成MIM电容器的电容器电介质。在一个实施例中，金属段包括栅极金属。在另一个实施例中，集成MIM电容器基本上与一个或多个晶体管同时形成，而不需要额外的制造工艺步骤。

105. 发明申请

US20110180883A1 METHOD AND STRUCTURE TO IMPROVE BODY EFFECT AND JUNCTION CAPACITANCE 有权
标题翻译：改善身体效能和结电容的方法和结构
公开(公告)号：US20110180883A1
公开(公告)日：2011-07-28
申请号：US12695565
申请日：2010-01-28
申请人： Xiangdong Chen , Geng Wang , Da Zhang
发明人： Xiangdong Chen , Geng Wang , Da Zhang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1083 , H01L29/665 , H01L29/66575 , H01L29/78
摘要： A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface of the substrate above the channel region; and implant a second-type impurity within the substrate to form source and drain regions within the substrate adjacent the top surface. The channel region is positioned between the source and drain regions. The second-type impurity has an opposite polarity with respect to the first-type impurity. The method and structure implant a greater concentration of the first-type impurity, relative to a concentration of the first-type impurity within the channel region, to form a primary body doping region within the substrate below (relative to the top surface) the channel region; and to form secondary body doping regions within the substrate below (relative to the top surface) the source and drain regions.
摘要翻译：一种方法和结构在衬底内注入第一种杂质以在衬底内邻近衬底的顶表面形成沟道区; 在通道区域上方的衬底的顶表面上形成栅极堆叠; 并且在所述衬底内注入第二类型杂质以在所述衬底内邻近所述顶表面形成源区和漏区。沟道区域位于源区和漏区之间。第二种杂质相对于第一种杂质具有相反的极性。所述方法和结构相对于沟道区域内的第一类型杂质的浓度注入更大浓度的第一类型杂质，以在衬底下方（相对于顶表面）在通道内形成主体掺杂区域地区; 并且在源极和漏极区域之下（相对于顶表面）下方的衬底内形成辅助体掺杂区域。

106. 发明申请

US20110169096A1 BALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERS 失效
标题翻译：使用应变层平衡NFET和PFET性能
公开(公告)号：US20110169096A1
公开(公告)日：2011-07-14
申请号：US12687374
申请日：2010-01-14
申请人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
发明人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
摘要翻译：集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。该对互补晶体管包括第一晶体管和第二晶体管。该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

107. 发明授权

US07911008B2 SRAM cell having a rectangular combined active area for planar pass gate and planar pull-down NFETS 有权
标题翻译：具有用于平面通过栅极和平面下拉NFET的矩形组合有源区的SRAM单元
公开(公告)号：US07911008B2
公开(公告)日：2011-03-22
申请号：US11924059
申请日：2007-10-25
申请人： Xiangdong Chen , Shang-Bin Ko , Dae-Gyu Park
发明人： Xiangdong Chen , Shang-Bin Ko , Dae-Gyu Park
IPC分类号： H01L27/088
CPC分类号： H01L27/1104 , H01L27/11
摘要： A planar pass gate NFET is designed with the same width as a planar pull-down NFET. To optimize a beta ratio between the planar pull-down NFET and an adjoined planar pass gate NFET, the threshold voltage of the planar pass gate NFET is increased by providing a different high-k metal gate stack to the planar pass gate NFET than to the planar pull-down NFET. Particularly, a threshold voltage adjustment dielectric layer, which is formed over a high-k dielectric layer, is preserved in the planar pass gate NFET and removed in the planar pull-down NFET. The combined NFET active area for the planar pass gate NFET and the planar pull-down NFET is substantially rectangular, which enables a high fidelity printing of the image of the combined NFET active area by lithographic means.
摘要翻译：平面通栅NFET被设计成具有与平面下拉NFET相同的宽度。为了优化平面下拉NFET和邻接的平面通过栅极NFET之间的β比率，通过向平面通过栅极NFET提供不同的高k金属栅极堆叠来增加平面栅极NFET的阈值电压，而不是平面下拉NFET。特别地，形成在高k电介质层上的阈值电压调节电介质层保留在平面通过栅极NFET中，并在平面下拉式NFET中去除。用于平面通过栅极NFET和平面下拉NFET的组合NFET有源区域基本上是矩形的，这使得能够通过光刻装置对组合的NFET有源区域的图像进行高保真打印。

108. 发明申请

US20110031585A1 Method for fabricating a MIM capacitor using gate metal for electrode and related structure 有权
标题翻译：用于电极栅极金属和相关结构的MIM电容器的制造方法
公开(公告)号：US20110031585A1
公开(公告)日：2011-02-10
申请号：US12462692
申请日：2009-08-07
申请人： Wei Xia , Xiangdong Chen , Akira Ito
发明人： Wei Xia , Xiangdong Chen , Akira Ito
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L27/0629 , H01L28/60
摘要： According to one exemplary embodiment, a method for fabricating a MIM capacitor in a semiconductor die includes forming a dielectric one segment over a substrate and a metal one segment over the dielectric one segment, where the metal one segment forms a lower electrode of the MIM capacitor. The method further includes forming a dielectric two segment over the dielectric one segment and a metal two segment over the dielectric two segment, where a portion of the metal two segment forms an upper electrode of the MIM capacitor. The metal one segment comprises a first gate metal. The metal two segment can comprise a second gate metal.
摘要翻译：根据一个示例性实施例，一种用于在半导体管芯中制造MIM电容器的方法包括在电介质一段上形成电介质一段并在电介质一段上形成金属一段，其中金属一段形成MIM电容器的下电极。该方法还包括在电介质一段上形成电介质两段，在电介质两段上形成金属二段，其中金属二段的一部分形成MIM电容器的上电极。金属一段包括第一栅极金属。金属二段可以包括第二栅极金属。

109. 发明授权

US07879666B2 Semiconductor resistor formed in metal gate stack 有权
标题翻译：半导体电阻器形成在金属栅极堆叠中
公开(公告)号：US07879666B2
公开(公告)日：2011-02-01
申请号：US12177986
申请日：2008-07-23
申请人： Da Zhang , Chendong Zhu , Xiangdong Chen , Melanie Sherony
发明人： Da Zhang , Chendong Zhu , Xiangdong Chen , Melanie Sherony
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L27/0629 , H01L28/20
摘要： A semiconductor process and apparatus fabricate a metal gate electrode (30) and an integrated semiconductor resistor (32) by forming a metal-based layer (26) and semiconductor layer (28) over a gate dielectric layer (24) and then selectively implanting the resistor semiconductor layer (28) in a resistor area (97) to create a conductive upper region (46) and a conduction barrier (47), thereby confining current flow in the resistor semiconductor layer (36) to only the top region (46) in the finally formed device.
摘要翻译：一种半导体工艺和装置，通过在栅极介电层（24）上形成金属基层（26）和半导体层（28），然后选择性地植入金属栅电极（30）和集成半导体电阻器（32）电阻器区域（97）中的电阻器半导体层（28），以产生导电上部区域（46）和导电屏障（47），从而将电流流入电阻器半导体层（36）中仅限于顶部区域（46）在最终形成的装置。

110. 发明申请

US20100320561A1 Method for forming a one-time programmable metal fuse and related structure 有权
标题翻译：形成一次性可编程金属保险丝及相关结构的方法
公开(公告)号：US20100320561A1
公开(公告)日：2010-12-23
申请号：US12456833
申请日：2009-06-22
申请人： Wei Xia , Xiangdong Chen , Akira Ito
发明人： Wei Xia , Xiangdong Chen , Akira Ito
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure.
摘要翻译：根据一个示例性实施例，一种用于形成一次性可编程金属熔丝结构的方法包括在衬底上形成金属熔丝结构，所述金属熔丝结构包括位于介电段和多晶硅段之间的栅极金属段，栅极金属熔丝形成在栅极金属段的一部分中。该方法还包括掺杂多晶硅段以便形成由未掺杂多晶硅部分分开的第一和第二掺杂多晶硅部分，其中在一个实施例中，栅极金属熔丝与未掺杂的多晶硅部分基本上共同延伸。该方法还可以包括在第一掺杂多晶硅部分上形成第一硅化物部分和在第二掺杂多晶硅部分上形成第二硅化物部分，其中第一和第二硅化物部分形成一次性可编程金属熔丝结构的相应端子。

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