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101. 发明授权

US07667632B2 Quantizing circuits for semiconductor devices 有权
标题翻译：半导体器件的量化电路
公开(公告)号：US07667632B2
公开(公告)日：2010-02-23
申请号：US11818999
申请日：2007-06-15
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： H03M1/12
CPC分类号： H03M1/504 , G11C7/02 , G11C7/04 , G11C7/1006 , G11C7/16 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C2211/5634 , G11C2211/5644 , H03M3/39 , H03M3/43 , H03M3/456
摘要： An electronic device that includes an internal data storage location coupled to an electrical conductor and a quantizing circuit coupled to the internal data storage location via the electrical conductor. In some embodiments, the quantizing circuit includes an analog-to-digital converter having an input and an output, where the input is coupled to the electrical conductor and a digital filter coupled to the output of the analog-to-digital converter.
摘要翻译：一种电子设备，包括耦合到电导体的内部数据存储位置和经由电导体耦合到内部数据存储位置的量化电路。在一些实施例中，量化电路包括具有输入和输出的模数转换器，其中输入耦合到电导体，以及耦合到模数转换器的输出的数字滤波器。

102. 发明授权

US07577044B2 Resistive memory element sensing using averaging 有权
标题翻译：电阻式存储元件感应使用平均
公开(公告)号：US07577044B2
公开(公告)日：2009-08-18
申请号：US12049426
申请日：2008-03-17
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： G11C11/02 , G01R27/14
CPC分类号： G01R27/02 , G11C11/16 , G11C11/1659 , G11C11/1673 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element to maintain a constant voltage across the resistive element. The charge reservoir is connected to the voltage supply to provide a current through the resistive element. The current source is connected to the charge reservoir to repeatedly supply a pulse of current to recharge the reservoir upon depletion of electronic charge from the reservoir, and the pulse counter provides a count of the number of pulses supplied by the current source over a predetermined time. The count represents a logic state of the memory cell element.
摘要翻译：一种用于确定电阻性存储单元元件（例如MRAM电阻单元元件）的逻辑状态的系统。该系统包括受控电压源，电子充电储存器，电流源和脉冲计数器。受控电压源连接到电阻存储单元元件，以在电阻元件两端保持恒定的电压。电荷储存器连接到电压源以提供通过电阻元件的电流。电流源连接到电荷储存器，以在从储存器耗尽电荷时重复地提供电流脉冲以对储存器再充电，并且脉冲计数器在预定时间内提供由电流源提供的脉冲数的计数。计数表示存储单元元件的逻辑状态。

103. 发明申请

US20080310221A1 Reference current sources 有权
标题翻译：参考电流源
公开(公告)号：US20080310221A1
公开(公告)日：2008-12-18
申请号：US11818982
申请日：2007-06-15
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： G11C11/34 , G11C7/02 , H03M1/12
CPC分类号： G11C16/06 , G11C5/147 , G11C7/02 , G11C7/067 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C13/0004 , G11C13/004 , H03M3/39 , H03M3/456 , H04N5/357 , H04N5/376
摘要： Systems, methods, and devices are disclosed, including an electronic device that includes a first data location, a quantizing circuit, and a reference current source, all coupled to an electrical conductor. The reference current source may include a current mirror with a side coupled to the electrical conductor and a second data location coupled to another side of the current mirror.
摘要翻译：公开了系统，方法和设备，包括包括第一数据位置，量化电路和参考电流源的电子设备，全部耦合到电导体。参考电流源可以包括具有耦合到电导体的一侧的电流镜和耦合到电流镜的另一侧的第二数据位置。

104. 发明申请

US20080309540A1 Integrators for delta-sigma modulators 有权
标题翻译：用于Δ-Σ调制器的积分器
公开(公告)号：US20080309540A1
公开(公告)日：2008-12-18
申请号：US11818998
申请日：2007-06-15
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： G06G7/12 , G11C11/34 , G11C7/02
CPC分类号： G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C2211/5634 , G11C2211/5644 , H03K3/0231 , H03M1/60
摘要： Methods, systems and devices are disclosed. Among the disclosed devices is an electronic device that, in certain embodiments, includes a plurality of memory elements or imaging elements connected to a bit-line and a delta-sigma modulator connected to the bit-line. The delta-sigma modulator may include an integrator having a differential amplifier.
摘要翻译：公开了方法，系统和装置。所公开的设备中的电子设备是在某些实施例中包括连接到与位线连接的位线和Δ-Σ调制器的多个存储器元件或成像元件的电子设备。 Δ-Σ调制器可以包括具有差分放大器的积分器。

105. 发明授权

US07151689B2 Adjusting the frequency of an oscillator for use in a resistive sense amp 有权
公开(公告)号：US07151689B2
公开(公告)日：2006-12-19
申请号：US11157140
申请日：2005-06-21
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： G11C11/00
CPC分类号： G11C7/067
摘要： A system and methods optimize the operation of sensing circuitry. In one embodiment, the output of a sensing circuit is stored in a register and processed through logic gates to determine whether the sensing output contains a predetermined string of logic ones or zeroes. If a string of ones is detected, the logic gates activate a counter to increase the operating clock frequency for the sensing circuit. If a string of zeroes is detected, the logic gates activate the counter to decrease the frequency.

106. 发明授权

US07133307B2 Resistive memory element sensing using averaging 有权
公开(公告)号：US07133307B2
公开(公告)日：2006-11-07
申请号：US10674550
申请日：2003-10-01
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： G11C11/21
CPC分类号： G01R27/02 , G11C11/16 , G11C11/1659 , G11C11/1673 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element to maintain a constant voltage across the resistive element. The charge reservoir is connected to the voltage supply to provide a current through the resistive element. The current source is connected to the charge reservoir to repeatedly supply a pulse of current to recharge the reservoir upon depletion of electronic charge from the reservoir, and the pulse counter provides a count of the number of pulses supplied by the current source over a predetermined time. The count represents a logic state of the memory cell element.

107. 发明授权

US06954391B2 Noise resistant small signal sensing circuit for a memory device 有权
公开(公告)号：US06954391B2
公开(公告)日：2005-10-11
申请号：US10993879
申请日：2004-11-19
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： G11C7/06 , G11C11/16 , G11C7/02
CPC分类号： G11C7/02 , G11C7/06 , G11C7/062 , G11C7/067 , G11C11/16 , G11C13/004 , G11C2207/063 , G11C2207/068
摘要： Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

108. 发明授权

US06822892B2 Resistive memory element sensing using averaging 有权
标题翻译：电阻式存储元件感应使用平均
公开(公告)号：US06822892B2
公开(公告)日：2004-11-23
申请号：US10290297
申请日：2002-11-08
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： G11C1121
CPC分类号： G01R27/02 , G11C11/16 , G11C11/1659 , G11C11/1673 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element to maintain a constant voltage across the resistive element. The charge reservoir is connected to the voltage supply to provide a current through the resistive element. The current source is connected to the charge reservoir repeatedly supply a pulse of current to recharge the reservoir upon depletion of electronic charge from the reservoir, and the pulse counter provides a count of the number of pulses supplied by the current source over a predetermined time. The count represents a logic state of the memory cell element.
摘要翻译：一种用于确定电阻性存储单元元件（例如MRAM电阻单元元件）的逻辑状态的系统。该系统包括受控电压源，电子充电储存器，电流源和脉冲计数器。受控电压源连接到电阻存储单元元件，以在电阻元件两端保持恒定的电压。电荷储存器连接到电压源以提供通过电阻元件的电流。电流源连接到充电储存器，在从储存器耗尽电荷时，重复地提供电流脉冲以对储存器再充电，并且脉冲计数器在预定时间内提供由电流源提供的脉冲数量的计数。计数表示存储单元元件的逻辑状态。

109. 发明授权

US06785156B2 Method and apparatus for sensing resistance values of memory cells 有权
标题翻译：用于感测存储单元的电阻值的方法和装置
公开(公告)号：US06785156B2
公开(公告)日：2004-08-31
申请号：US10345384
申请日：2003-01-16
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： G11C1100
CPC分类号： G11C7/065 , G11C11/16
摘要： A method for sensing the resistance value of a resistor-based memory cell. A current is driven through all unused row lines of a memory array while grounding the row line associated with the selected cell, thereby forcing the current through a comparatively low equivalent resistance formed by the parallel coupling of all unselected memory cells and also through a comparatively high resistance of the selected memory cell. The voltage on a column line corresponding to the selected memory cell is then measured to ground. The voltage level corresponds to either one of two resistance values (i.e., signifying either a logic “HIGH” or a logic “LOW”).
摘要翻译：一种用于感测基于电阻器的存储单元的电阻值的方法。电流通过存储器阵列的所有未使用的行线驱动，同时将与所选择的单元相关联的行线接地，从而迫使电流通过由所有未选择的存储器单元的并联耦合形成的相对较低的等效电阻，并且还通过相对较高的所选存储单元的电阻。然后将对应于所选存储单元的列线上的电压测量为接地。电压电平对应于两个电阻值中的任一个（即，表示逻辑“HIGH”或逻辑“LOW”）。

110. 发明授权

US06779126B1 Phase detector for all-digital phase locked and delay locked loops 有权
标题翻译：全数字锁相和延迟锁定环路的相位检测器
公开(公告)号：US06779126B1
公开(公告)日：2004-08-17
申请号：US09652364
申请日：2000-08-31
申请人： Feng Lin , R. Jacob Baker
发明人： Feng Lin , R. Jacob Baker
IPC分类号： G06F104
CPC分类号： G11C7/22 , G11C7/222 , H03L7/0814 , H03L7/089 , H03L7/0995 , H03L2207/50
摘要： A phase detector is comprised of two cross-coupled gates which are capable of phase discrimination down to a level of approximately 10 picoseconds. An arbiter circuit, responsive to the cross-coupled gates, generates mutually exclusive UP and DOWN pulse signals. The UP and DOWN pulse signals may be filtered and used to control the delay line of an all digital delay locked or phase locked loop. Methods of operation are also disclosed.
摘要翻译：相位检测器由两个交叉耦合的栅极组成，它们能相位分辨到大约10皮秒的水平。响应于交叉耦合门的仲裁电路产生互斥的UP和DOWN脉冲信号。 UP和DOWN脉冲信号可以被滤波并用于控制全数字延迟锁定或锁相环的延迟线。还公开了操作方法。

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