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101. 发明授权

US09141389B2 Heterogeneous ISA microprocessor with shared hardware ISA registers 有权
标题翻译：具有共享硬件ISA寄存器的异构ISA微处理器
公开(公告)号：US09141389B2
公开(公告)日：2015-09-22
申请号：US13412888
申请日：2012-03-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F9/30 , G06F9/44
CPC分类号： G06F9/30123 , G06F9/30076 , G06F9/3013 , G06F9/30174 , G06F9/30181 , G06F9/30189 , G06F9/4403
摘要： A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program and a plurality of hardware registers. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, the plurality of hardware registers store x86 ISA architectural state; when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, the plurality of hardware registers store ARM ISA architectural state.
摘要翻译：能够运行x86指令集架构（ISA）机器语言程序和高级RISC机器（ARM）的微处理器ISA机器语言程序包括指示微处理器当前是否正在获取x86 ISA或ARM ISA机器语言程序的指令的模式指示器和多个硬件寄存器。当模式指示灯指示微处理器当前正在获取x86 ISA机器语言程序指令时，多个硬件寄存器存储x86 ISA架构状态; 当模式指示灯指示微处理器当前正在获取ARM ISA机器语言程序指令时，多个硬件寄存器存储ARM ISA架构状态。

102. 发明授权

US08819839B2 Microprocessor having a secure execution mode with provisions for monitoring, indicating, and managing security levels 有权
标题翻译：具有安全执行模式的微处理器，用于监视，指示和管理安全级别
公开(公告)号：US08819839B2
公开(公告)日：2014-08-26
申请号：US12263250
申请日：2008-10-31
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06Q99/00 , G06F21/74 , G06F21/72 , G06F21/79
CPC分类号： G06F21/74 , G06F21/72 , G06F21/79
摘要： An apparatus including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The non-secure application programs are accessed from a system memory via a system bus, and the secure application program is executed in a secure execution mode. The microprocessor has a watchdog manager that monitors environments of the microprocessor by noting and evaluating data communicated by a plurality of monitors, and that classifies the data to indicate a security level associated with execution of the secure application program, and that directs secure execution mode logic to perform responsive actions in accordance with the security level. The secure non-volatile memory is coupled to the microprocessor via a private bus, and stores the secure application program. The secure application program is encrypted. Transactions over the private bus are isolated from the system bus and corresponding system bus resources within the microprocessor.
摘要翻译：一种包括微处理器和安全非易失性存储器的装置。微处理器执行非安全应用程序和安全应用程序。通过系统总线从系统存储器访问非安全应用程序，并且以安全执行模式执行安全应用程序。微处理器具有监视器管理器，其通过注意和评估由多个监视器传送的数据来监视微处理器的环境，并且对数据进行分类以指示与执行安全应用程序相关联的安全级别，并且指导安全执行模式逻辑根据安全级别执行响应动作。安全的非易失性存储器经由专用总线耦合到微处理器，并存储安全应用程序。安全应用程序被加密。专用总线上的交易与系统总线和微处理器内相应的系统总线资源隔离。

103. 发明授权

US08521996B2 Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution 有权
标题翻译：流水线微处理器具有快速非选择性正确的条件分支指令分辨率
公开(公告)号：US08521996B2
公开(公告)日：2013-08-27
申请号：US12481511
申请日：2009-06-09
申请人： G. Glenn Henry , Terry Parks , Brent Bean
发明人： G. Glenn Henry , Terry Parks , Brent Bean
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/30058 , G06F9/3802 , G06F9/3867
摘要： A microprocessor includes a pipeline of stages for processing instructions and first and second types of conditional branch instruction includable by a program. The microprocessor makes a prediction of conditional branch instructions of the first type and flushes the pipeline of instructions if the prediction is subsequently determined to be incorrect, thereby incurring a branch misprediction penalty related to processing of conditional branch instructions of the first type. The microprocessor always correctly resolves conditional branch instructions of the second type without making a prediction of conditional branch instructions of the second type, thereby avoiding ever incurring a branch misprediction penalty related to processing of conditional branch instructions of the second type.
摘要翻译：微处理器包括用于处理指令的级的流水线，以及可由程序包含的第一和第二类型的条件分支指令。如果预测随后被确定为不正确，则微处理器对第一类型的条件转移指令进行预测并刷新指令的流水线，由此产生与第一类型的条件转移指令的处理相关的分支误预算罚款。微处理器总是正确地解析第二类型的条件转移指令，而不进行第二类型的条件转移指令的预测，从而避免与第二类型的条件转移指令的处理有关的分支误预算罚款。

104. 发明申请

US20120260065A1 MULTI-CORE MICROPROCESSOR THAT PERFORMS X86 ISA AND ARM ISA MACHINE LANGUAGE PROGRAM INSTRUCTIONS BY HARDWARE TRANSLATION INTO MICROINSTRUCTIONS EXECUTED BY COMMON EXECUTION PIPELINE 有权
标题翻译：通过硬件翻译进行X86 ISA和ARM ISA机器语言程序指令的多核微处理器由共同执行管道执行的微型操作
公开(公告)号：US20120260065A1
公开(公告)日：2012-10-11
申请号：US13412904
申请日：2012-03-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F9/30174 , G06F9/30025 , G06F9/30076 , G06F9/30101 , G06F9/30123 , G06F9/3017 , G06F9/30189 , G06F9/4401
摘要： A microprocessor includes a plurality of processing cores each including a hardware instruction translator that translates instructions of x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs into microinstructions defined by a microinstruction set of the microprocessor. The microinstructions are encoded in a distinct manner from the manner in which the instructions of the x86 and ARM instruction sets are defined. Each core includes an execution pipeline that executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. Each core uses and associated indicator to determine whether it will boot as an x86 ISA core or an ARM ISA core when reset. The indicators are configurable to indicate that at least one of the cores will boot as an x86 ISA core and at least one other of the cores will boot as an ARM ISA core.
摘要翻译：微处理器包括多个处理核心，每个处理核心包括将x86指令集架构（ISA）机器语言程序和高级RISC机器（ARM）ISA机器语言程序的指令转换成由微处理器的微指令集定义的微指令的硬件指令转换器。微指令以与定义x86和ARM指令集的指令的方式不同的方式进行编码。每个内核都包含一个执行管道，执行微指令以生成由x86 ISA和ARM ISA指令定义的结果。每个核心使用和相关联的指示器来确定在重置时是否将引导为x86 ISA内核或ARM ISA内核。这些指示符是可配置的，表示至少有一个内核将作为x86 ISA内核引导，并且至少另外一个内核将作为ARM ISA内核引导。

105. 发明申请

US20120260042A1 LOAD MULTIPLE AND STORE MULTIPLE INSTRUCTIONS IN A MICROPROCESSOR THAT EMULATES BANKED REGISTERS 有权
标题翻译：加载多个寄存器的微处理器中的多个和存储多个指令
公开(公告)号：US20120260042A1
公开(公告)日：2012-10-11
申请号：US13413314
申请日：2012-03-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F15/76 , G06F9/06 , G06F12/08
CPC分类号： G06F9/22 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F12/0875
摘要： A microprocessor supports an instruction set architecture that specifies: processor modes, architectural registers associated with each mode, and a load multiple instruction that instructs the microprocessor to load data from memory into specified ones of the registers. Direct storage holds data associated with a first portion of the registers and is coupled to an execution unit to provide the data thereto. Indirect storage holds data associated with a second portion of the registers and cannot directly provide the data to the execution unit. Which architectural registers are in the first and second portions varies dynamically based upon the current processor mode. If a specified register is currently in the first portion, the microprocessor loads data from memory into the direct storage, whereas if in the second portion, the microprocessor loads data from memory into the direct storage and then stores the data from the direct storage to the indirect storage.
摘要翻译：微处理器支持指令集架构，其指定：处理器模式，与每种模式相关联的架构寄存器，以及指令微处理器将数据从存储器加载到指定寄存器中的加载多指令。直接存储保持与寄存器的第一部分相关联的数据，并且耦合到执行单元以向其提供数据。间接存储保存与寄存器的第二部分相关联的数据，并且不能将数据直接提供给执行单元。第一和第二部分中的哪些架构寄存器基于当前的处理器模式动态变化。如果指定的寄存器当前位于第一部分，则微处理器将数据从存储器加载到直接存储器中，而如果在第二部分中，微处理器将数据从存储器加载到直接存储器中，然后将数据从直接存储器存储到间接存储。

106. 发明授权

US08090931B2 Microprocessor with fused store address/store data microinstruction 有权
标题翻译：具有融合存储地址/存储数据微指令的微处理器
公开(公告)号：US08090931B2
公开(公告)日：2012-01-03
申请号：US12233261
申请日：2008-09-18
申请人： Gerard M. Col , G. Glenn Henry , Rodney E. Hooker , Terry Parks
发明人： Gerard M. Col , G. Glenn Henry , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/34
CPC分类号： G06F9/30043 , G06F9/30174 , G06F9/3824 , G06F9/3836 , G06F9/3857
摘要： A microprocessor includes an instruction translator that translates PUSHF, POP, and MOVSB x86 macroinstructions into multiple microinstructions that include a fused store microinstruction. For PUSHF, first and second microinstructions moves the x86 EFLAGS register into and mask off bits in a temporary register, and the fused store microinstruction stores it to a memory location. For POP, a first microinstruction loads a first memory location value into a temporary register and the fused store microinstruction stores it to the second memory location. For MOVSB, the first microinstruction loads a first memory location operand into a temporary register and the fused store microinstruction stores it to a second memory location. A reorder buffer receives the fused store microinstruction into exactly one entry. In response to the fused store microinstruction, an instruction dispatcher dispatches store address and store data microinstructions, neither of which occupies a reorder buffer entry, to different respective execution units.
摘要翻译：微处理器包括将PUSHF，POP和MOVSB x86宏指令转换成包括融合存储微指令的多个微指令的指令转换器。对于PUSHF，第一和第二微指令将x86 EFLAGS寄存器移入临时寄存器中并将其屏蔽，并且融合存储微指令将其存储到存储器位置。对于POP，第一微指令将第一存储器位置值加载到临时寄存器中，并且融合存储器微指令将其存储到第二存储器位置。对于MOVSB，第一微指令将第一存储器位置操作数加载到临时寄存器中，并且熔接存储器微指令将其存储到第二存储器位置。重新排序缓冲器将融合存储微指令接收到正好一个条目。响应于融合存储微指令，指令分派器调度存储地址并存储数据微指令（这两个微指令都不占用重排序缓冲器入口）到不同的各个执行单元。

107. 发明授权

US08069339B2 Microprocessor with microinstruction-specifiable non-architectural condition code flag register 有权
标题翻译：具有微指令可指定非架构状态代码标志寄存器的微处理器
公开(公告)号：US08069339B2
公开(公告)日：2011-11-29
申请号：US12469430
申请日：2009-05-20
申请人： G. Glenn Henry , Terry Parks , Gerard M. Col
发明人： G. Glenn Henry , Terry Parks , Gerard M. Col
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30116 , G06F9/30094 , G06F9/30145 , G06F9/30185
摘要： A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set of the microprocessor instructs the microprocessor to update the plurality of condition code flags based on a result of the first instruction. The first instruction includes a field for indicating whether to update the plurality of condition code flags of the architectural or non-architectural register. A second instruction of the microarchitectural instruction set instructs the microprocessor to conditionally perform an operation based on one of the plurality of condition code flags. The second instruction includes a field for indicating whether to use the one of the plurality of condition code flags of the architectural or non-architectural register to determine whether to perform the operation.
摘要翻译：微处理器包括架构寄存器和非架构寄存器，每个都具有多个条件码标志。微处理器的微架构指令集的第一指令指示微处理器基于第一指令的结果来更新多个条件代码标志。第一指令包括用于指示是否更新架构或非架构寄存器的多个条件代码标志的字段。微架构指令集的第二指令指示微处理器基于多个条件代码标志之一有条件地执行操作。第二指令包括用于指示是否使用架构或非架构寄存器的多个条件代码标志中的一个来确定是否执行操作的字段。

108. 发明申请

US20100299504A1 MICROPROCESSOR WITH MICROINSTRUCTION-SPECIFIABLE NON-ARCHITECTURAL CONDITION CODE FLAG REGISTER 有权
标题翻译：带微型可编程非标建筑规范标志寄存器的微处理器
公开(公告)号：US20100299504A1
公开(公告)日：2010-11-25
申请号：US12469430
申请日：2009-05-20
申请人： G. Glenn Henry , Terry Parks , Gerard M. Col
发明人： G. Glenn Henry , Terry Parks , Gerard M. Col
IPC分类号： G06F9/30
CPC分类号： G06F9/30116 , G06F9/30094 , G06F9/30145 , G06F9/30185
摘要： A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set of the microprocessor instructs the microprocessor to update the plurality of condition code flags based on a result of the first instruction. The first instruction includes a field for indicating whether to update the plurality of condition code flags of the architectural or non-architectural register. A second instruction of the microarchitectural instruction set instructs the microprocessor to conditionally perform an operation based on one of the plurality of condition code flags. The second instruction includes a field for indicating whether to use the one of the plurality of condition code flags of the architectural or non-architectural register to determine whether to perform the operation.
摘要翻译：微处理器包括架构寄存器和非架构寄存器，每个都具有多个条件码标志。微处理器的微架构指令集的第一指令指示微处理器基于第一指令的结果来更新多个条件代码标志。第一指令包括用于指示是否更新架构或非架构寄存器的多个条件代码标志的字段。微架构指令集的第二指令指示微处理器基于多个条件代码标志之一有条件地执行操作。第二指令包括用于指示是否使用架构或非架构寄存器的多个条件代码标志中的一个来确定是否执行操作的字段。

109. 发明授权

US07818358B2 Microprocessor with random number generator and instruction for storing random data 有权
标题翻译：具有随机数发生器的微处理器和用于存储随机数据的指令
公开(公告)号：US07818358B2
公开(公告)日：2010-10-19
申请号：US11615994
申请日：2006-12-25
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F7/58
CPC分类号： G06F7/58 , G06F9/30003 , G06F9/3004 , G06F9/30087 , G06F11/27
摘要： A microprocessor includes a storage element that accumulates a variable number of bytes of random data. The microprocessor also includes a counter that maintains a count of the variable number of bytes accumulated in the storage element. The microprocessor also includes an instruction translator that translates an instruction specifying an address in a memory coupled to the microprocessor. The microprocessor also includes a store unit that stores to the memory at the address the variable number of bytes of random data from the storage element in response to the instruction translator translating the instruction. In one embodiment, the microprocessor atomically stores the count and the bytes accumulated in said buffer to the system memory. In one embodiment, an interrupt unit disables interrupts after the instruction translator translates the instruction and enables interrupts after execution of the instruction.
摘要翻译：微处理器包括累积随机数据的可变字节数的存储元件。微处理器还包括计数器，其维持存储元件中累积的可变字节数的计数。微处理器还包括一个指令转换器，该指令转换器转换指定耦合到微处理器的存储器中的地址的指令。微处理器还包括存储单元，其响应于转换指令的指令翻译器，将来自存储元件的随机数据的可变字节数存储在地址处的存储器中。在一个实施例中，微处理器将存储在所述缓冲器中的计数和字节存储在系统存储器中。在一个实施例中，中断单元在指令转换器转换指令之后禁止中断，并且在执行指令之后启用中断。

110. 发明授权

US07802078B2 REP MOVE string instruction execution by selecting loop microinstruction sequence or unrolled sequence based on flag state indicative of low count repeat 有权
标题翻译： REP通过选择循环微指令序列或基于表示低计数重复的标志状态的展开序列来执行字符串指令
公开(公告)号：US07802078B2
公开(公告)日：2010-09-21
申请号：US12270010
申请日：2008-11-13
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F9/22
CPC分类号： G06F9/30032 , G06F9/30018 , G06F9/30065 , G06F9/30167 , G06F9/3017
摘要： A microprocessor REP MOVS macroinstruction specifies the word length of the string in the IA-32 ECX register. The microprocessor includes a memory, configured to store a first and second sequence of microinstructions. The first sequence conditionally transfers control to a microinstruction within the first sequence based on the ECX register. The second sequence does not conditionally transfer control based on the ECX register. The microprocessor includes an instruction translator, coupled to the memory. In response to a macroinstruction that moves an immediate value into the ECX register, the instruction translator sets a flag and saves the immediate value. In response to a macroinstruction that modifies the ECX register in a different manner, the translator clears the flag. In response to a REP MOVS macroinstruction, the instruction translator transfers control to the first sequence if the flag is clear; and transfers control to the second sequence if the flag is set.
摘要翻译：微处理器REP MOVS宏指令指定IA-32 ECX寄存器中字符串的字长。微处理器包括存储器，其被配置为存储微指令的第一和第二序列。基于ECX寄存器，第一序列有条件地将控制转移到第一序列内的微指令。第二个序列没有有条件地转移基于ECX寄存器的控制。微处理器包括耦合到存储器的指令转换器。响应于将即时值移动到ECX寄存器的宏指令，指令转换器设置一个标志并保存立即值。响应以不同方式修改ECX寄存器的宏指令，转换器清除该标志。响应于REP MOVS宏指令，如果标志清零，指令转换器将控制转移到第一个序列; 并且如果设置了标志，则将控制转移到第二序列。

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