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101. 发明授权

US08030734B2 Forming phase change memories with a breakdown layer sandwiched by phase change memory material 有权
标题翻译：形成具有夹层相变记忆材料的击穿层的相变存储器
公开(公告)号：US08030734B2
公开(公告)日：2011-10-04
申请号：US12346507
申请日：2008-12-30
申请人： Charles H. Dennison , George A. Gordon , John Peters
发明人： Charles H. Dennison , George A. Gordon , John Peters
IPC分类号： H01L21/82 , H01L21/20 , H01L29/00
CPC分类号： H01L45/06 , H01L27/2427 , H01L45/1233 , H01L45/1246 , H01L45/126 , H01L45/144 , H01L45/1683
摘要： A phase change memory cell may be formed with a pair of chalcogenide phase change layers that are separated by a breakdown layer. The breakdown layer may be broken down prior to use of the memory so that a conductive breakdown point is defined within the breakdown layer. In some cases, the breakdown point may be well isolated from the surrounding atmosphere, reducing heat losses and decreasing current consumption. In addition, in some cases, the breakdown point may be well isolated from overlying and underlying electrodes, reducing issues related to contamination. The breakdown point may be placed between a pair of chalcogenide layers with the electrodes outbound of the two chalcogenide layers.
摘要翻译：相变存储单元可以由被击穿层分开的一对硫族化物相变层形成。在使用存储器之前可以将击穿层分解，使得在击穿层内限定导电击穿点。在某些情况下，故障点可能与周围大气良好隔离，减少热损失和降低电流消耗。此外，在某些情况下，击穿点可能与上覆电极和下层电极很好地隔离，从而减少与污染有关的问题。击穿点可以放置在一对硫族化物层之间，其中两个硫族化物层的电极出发。

102. 发明授权

US07804082B2 Phase change memory system 有权
标题翻译：相变存储器系统
公开(公告)号：US07804082B2
公开(公告)日：2010-09-28
申请号：US11998899
申请日：2007-12-03
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L29/02
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144
摘要： A thin film phase change memory may be provided with a layer which changes between amorphous and crystalline states. The threshold voltage of that layer may be increased in a variety of fashions. As a result of the threshold increase, it is possible to transition cells, initially fabricated in the set or low resistance state, into the reset or high resistance state. In one advantageous embodiment, after such initialization and programming, the threshold voltage increase is eliminated so that the cells operate thereafter without the added threshold voltage.
摘要翻译：薄膜相变存储器可以设置有在非晶态和晶态之间变化的层。该层的阈值电压可以以各种方式增加。作为门限增加的结果，可以将初始以设定或低电阻状态制造的电池转换成复位或高电阻状态。在一个有利的实施例中，在这样的初始化和编程之后，消除阈值电压增加，使得在没有增加的阈值电压的情况下，电池工作。

103. 发明申请

US20100197120A1 Forming Phase Change Memory Cell With Microtrenches 审中-公开
标题翻译：形成相变存储器细胞与微螺旋
公开(公告)号：US20100197120A1
公开(公告)日：2010-08-05
申请号：US12756392
申请日：2010-04-08
申请人： Fabio Pellizzer , Charles H. Dennison
发明人： Fabio Pellizzer , Charles H. Dennison
IPC分类号： H01L21/20
CPC分类号： H01L45/06 , H01L27/2427 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1691
摘要： A semiconductor substrate is covered by a dielectric region. The dielectric region accommodates a memory element and a selection element forming a phase change memory cell. The memory element is formed by a resistive element and by a storage region of a phase change material extending on and in contact with the resistive element at a contact area. The selection element is formed by a switching region of chalcogenic material embedded in the dielectric region and belonging to a stack extending on the resistive element and including also the storage region. A mold region extends on top of the resistive element and delimits a trench having a substantially elongated shape. At least one portion of the storage region extends in the trench and defines a phase change memory portion over the contact area.
摘要翻译：半导体衬底被电介质区域覆盖。电介质区域容纳存储元件和形成相变存储单元的选择元件。存储元件由电阻元件和在接触区域处延伸并与电阻元件接触的相变材料的存储区域形成。选择元件由嵌入在电介质区域中的属于在电阻元件上延伸并且还包括存储区域的堆叠的金属的切换区域形成。模具区域在电阻元件的顶部延伸并限定具有基本细长形状的沟槽。存储区域的至少一部分在沟槽中延伸并限定了接触区域上的相变存储部分。

104. 发明授权

US07729162B2 Semiconductor phase change memory using multiple phase change layers 有权
标题翻译：半导体相变存储器使用多个相变层
公开(公告)号：US07729162B2
公开(公告)日：2010-06-01
申请号：US11973565
申请日：2007-10-09
申请人： Charles H. Dennison , Stephen J. Hudgens
发明人： Charles H. Dennison , Stephen J. Hudgens
IPC分类号： G11C11/00
CPC分类号： H01L45/065 , G11C13/0004 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , Y10S977/754
摘要： In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
摘要翻译：根据一些实施例，可以形成相变存储器，其中减少了编程体积相变材料之外的区域中的热导率。这可能会降低所得相变存储器的功耗。功耗的降低可以通过在编程体积之外形成很少或不混合的相变材料的不同层来实现。例如，在一个实施例中，可以在两个不同的相变层之间保持扩散阻挡层。在另一个实施方案中，可以使用面心立方硫属元素化合物结构。

105. 发明申请

US20090230505A1 Self-aligned memory cells and method for forming 有权
标题翻译：自对准存储单元及其形成方法
公开(公告)号：US20090230505A1
公开(公告)日：2009-09-17
申请号：US12075913
申请日：2008-03-14
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L29/06 , H01L21/764
CPC分类号： H01L45/126 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
摘要： The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.
摘要翻译：本发明提供了一种基于可变电阻材料存储元件的存储单元，其包括具有柱结构的存取装置，所述柱结构还可包括保护侧壁层。支柱存取装置选择并隔离其他存储器阵列单元的存储单元，并且适于将形成在其上的任何存储元件自对准，并将适当的编程电流传送到存储元件。柱结构由堆叠在字线上方和存储元件下方的一个或多个访问器件层形成。可选择性地在柱结构内形成可选的电阻层，以最小化存取器件层和存储元件中的电阻。柱式存取装置可以是二极管，晶体管，Ovonic阈值开关或能够调节流向上覆可编程存储器材料的电流的其他装置。

106. 发明授权

US07491574B2 Reducing oxidation of phase change memory electrodes 有权
标题翻译：减少相变记忆电极的氧化
公开(公告)号：US07491574B2
公开(公告)日：2009-02-17
申请号：US11904557
申请日：2007-09-27
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L21/06
CPC分类号： H01L45/06 , H01L27/2427 , H01L45/1233 , H01L45/141 , H01L45/1675
摘要： A phase change memory may be formed in a way which reduces oxygen infiltration through a chalcogenide layer overlying a lower electrode. Such infiltration may cause oxidation of the lower electrode which adversely affects performance. In one such embodiment, an etch through an overlying upper electrode layer may be stopped before reaching a layer which overlies said chalcogenide layer. Then, photoresist used for such etching may be utilized in a high temperature oxygen plasma. Only after such plasma treatment has been completed is that overlying layer removed, which ultimately exposes the chalcogenide.
摘要翻译：相变存储器可以以减少氧气穿过覆盖在下电极上的硫属化物层的方式形成。这种渗透可能导致下部电极的氧化，这对性能有不利影响。在一个这样的实施例中，通过覆盖的上电极层的蚀刻可以在到达覆盖所述硫族化物层的层之前停止。然后，可以在高温氧等离子体中使用用于这种蚀刻的光致抗蚀剂。只有在这样的等离子体处理完成之后，去除了上层，最终暴露了硫族化物。

107. 发明授权

US07350018B2 Method and system for using dynamic random access memory as cache memory 有权
标题翻译：使用动态随机存取存储器作为高速缓冲存储器的方法和系统
公开(公告)号：US07350018B2
公开(公告)日：2008-03-25
申请号：US11595370
申请日：2006-11-08
申请人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
发明人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
IPC分类号： G06F12/16
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0897 , G11C7/1006 , G11C7/1042 , G11C11/406 , G11C11/409 , G11C15/043
摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAMs are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
摘要翻译：高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且还包括2个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。在操作中，从DRAM的存储体中读取的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

108. 发明授权

US07348268B2 Controlled breakdown phase change memory device 有权
标题翻译：受控击穿相变存储器件
公开(公告)号：US07348268B2
公开(公告)日：2008-03-25
申请号：US10939237
申请日：2004-09-10
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L21/44
CPC分类号： H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/16
摘要： A phase change memory material may be deposited over an electrode in a pore through an insulator. The adherence of the memory material to the insulator may be improved by using a glue layer. At the same time, a breakdown layer may be formed in the pore between the memory material and electrode.
摘要翻译：相变记忆材料可以通过绝缘体沉积在孔中的电极上。可以通过使用胶层来改善记忆材料对绝缘体的粘附性。同时，可以在存储材料和电极之间的孔隙中形成击穿层。

109. 发明授权

US07282440B2 Integrated circuit contact 失效
标题翻译：集成电路接触
公开(公告)号：US07282440B2
公开(公告)日：2007-10-16
申请号：US10136544
申请日：2002-05-01
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L21/4763 , H01L21/461 , H01L21/302
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.
摘要翻译：提供了在制造集成电路和如此制造的器件的制造中形成垂直触点的工艺。该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。该方法包括在基板的表面上形成绝缘层的步骤; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。在形成多级金属集成电路期间，可以重复上述过程一次或多次。

110. 发明授权

US07119397B2 Double blanket ion implant method and structure 有权
标题翻译：双层离子注入法和结构
公开(公告)号：US07119397B2
公开(公告)日：2006-10-10
申请号：US10768081
申请日：2004-02-02
申请人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
发明人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
IPC分类号： H01L29/06
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28247 , H01L29/6656
摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.
摘要翻译：公开了一种用于在诸如MOSFET访问装置的存储器阵列器件中形成扩散区的双层覆盖离子注入方法。该方法提供了在其表面上形成栅极结构的半导体衬底。接下来，通过第一覆盖离子注入工艺在与沟道区相邻的区域中形成第一对扩散区。第一次毯式离子注入工艺具有第一能级和剂量。该器件经受氧化条件，其在栅极结构上形成氧化的侧壁。在与第一离子注入工艺相同的位置处进行第二覆盖离子注入工艺，向扩散区域添加额外的掺杂剂。第二次毯子离子注入过程具有第二能量水平和剂量。所得到的扩散区域提供了比现有技术的装置更好的静态刷新性能的装置。此外，第一和第二能量水平和剂量基本上低于现有技术单一植入过程中使用的能级和剂量。

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