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101. 发明授权

US08242561B2 Semiconductor devices with improved self-aligned contact areas 有权
标题翻译：具有改善的自对准接触面积的半导体器件
公开(公告)号：US08242561B2
公开(公告)日：2012-08-14
申请号：US12702684
申请日：2010-02-09
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L29/786
CPC分类号： H01L29/41791 , H01L29/66795 , H01L29/785 , H01L2029/7858
摘要： A field effect device includes a channel region disposed on a silicon on insulator (SOI) layer, a gate portion disposed on the channel region, a source region disposed on the SOI layer and connected to the channel region having a horizontal surface and a vertical surface, the vertical surface arranged perpendicular to a linear axis of the device, a silicide portion that includes the horizontal surface and vertical surface of the source region, a contact including a metallic material in contact with the horizontal surface and vertical surface of the source region, and a drain region connected to the channel region disposed on the SOI layer.
摘要翻译：场效应器件包括设置在绝缘体上硅（SOI）层上的沟道区域，设置在沟道区上的栅极部分，设置在SOI层上的源极区域，并连接到具有水平表面和垂直表面的沟道区域垂直于装置的线性轴排列的垂直表面，包括源区域的水平表面和垂直表面的硅化物部分，包括与源区域的水平表面和垂直表面接触的金属材料的触点，以及连接到设置在SOI层上的沟道区的漏极区。

102. 发明申请

US20120056264A1 METHOD FOR FORMING AND STRUCTURE OF A RECESSED SOURCE/DRAIN STRAP FOR A MUGFET 有权
标题翻译：用于形成和结构的用于大量生长的源/排水带的方法
公开(公告)号：US20120056264A1
公开(公告)日：2012-03-08
申请号：US12876343
申请日：2010-09-07
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/7848 , H01L29/785 , H01L2029/7858
摘要： A method and semiconductor structure includes an insulator layer on a substrate, a plurality of parallel fins above the insulator layer, relative to a bottom of the structure. Each of the fins comprises a central semiconductor portion and conductive end portions. At least one conductive strap may be positioned within the insulator layer below the fins, relative to the bottom of the structure. The conductive strap can be perpendicular to the fins and contact the fins. The conductive strap further includes recessed portions disposed within the insulator layer, below the plurality of fins, relative to the bottom of the structure, and between each of the plurality of fins, and projected portions disposed above the insulator layer, collinear with each of the plurality of fins, relative to the bottom of the structure. The conductive strap is disposed in at least one of a source and a drain region of the semiconductor structure. A gate insulator contacts and covers the central semiconductor portion of the fins, and a gate conductor covers and contacts the gate insulator.
摘要翻译：一种方法和半导体结构包括在衬底上的绝缘体层，相对于该结构的底部在绝缘体层之上的多个平行的鳍。每个翅片包括中心半导体部分和导电端部。至少一个导电带可以相对于结构的底部定位在翅片下方的绝缘体层内。导电带可以垂直于翅片并接触翅片。导电带还包括设置在绝缘体层内的凹陷部分，相对于结构的底部在多个翅片之下，并且在多个翅片中的每一个之间，以及设置在绝缘体层上方的突出部分，多个翅片相对于结构的底部。导电带设置在半导体结构的源极和漏极区域中的至少一个中。栅极绝缘体接触并覆盖翅片的中心半导体部分，并且栅极导体覆盖并接触栅极绝缘体。

103. 发明授权

US08115251B2 Recessed gate channel with low Vt corner 有权
标题翻译：嵌入门通道低Vt角
公开(公告)号：US08115251B2
公开(公告)日：2012-02-14
申请号：US11741898
申请日：2007-04-30
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/66
CPC分类号： H01L29/665 , H01L29/1083 , H01L29/4236 , H01L29/517 , H01L29/66621 , H01L29/78
摘要： A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate electrode defining a surrounding channel region and having a gate dielectric material layer lining and including a conductive material having a top surface recessed to reduce overlap capacitance with respect to the source and drain diffusion regions formed at an upper substrate surface at either side of the gate electrode. There is optionally formed halo implants at either side of and abutting the gate electrode, each halo implants extending below the source and drain diffusions into the channel region. Additionally, highly doped source and drain extension regions are formed that provide a low resistance path from the source and drain diffusion regions to the channel region. The recessed gate FET device suppresses short channel effects and exhibits improved threshold voltage (Vt) characteristics at corners of the trench bottom.
摘要翻译：凹陷栅极FET器件包括具有上部和下部的衬底，下部具有比上部更低的掺杂剂材料的浓度; 限定周围通道区域并且具有衬底的栅介质材料层的沟槽型栅电极，并且包括具有凹陷的顶表面的导电材料，以减少相对于在上基板表面处形成的源极和漏极扩散区域的重叠电容侧电极。在栅电极的任一侧和邻接栅电极处可选地形成卤素植入物，每个卤素注入物延伸到源极和漏极扩散到沟道区域之内。此外，形成高掺杂的源极和漏极延伸区域，其提供从源极和漏极扩散区域到沟道区域的低电阻路径。凹陷栅极FET器件抑制短沟道效应并且在沟槽底部的拐角处表现出改进的阈值电压（Vt）特性。

104. 发明授权

US08053314B2 Asymmetric field effect transistor structure and method 有权
标题翻译：不对称场效应晶体管结构及方法
公开(公告)号：US08053314B2
公开(公告)日：2011-11-08
申请号：US12985060
申请日：2011-01-05
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7834 , H01L29/7835
摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).
摘要翻译：公开了非对称场效应晶体管结构的实施例和形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即提供改进的驱动电流，电路延迟最小）。具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定的电容值）。

105. 发明授权

US07915670B2 Asymmetric field effect transistor structure and method 有权
公开(公告)号：US07915670B2
公开(公告)日：2011-03-29
申请号：US11778185
申请日：2007-07-16
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/336 , H01L29/76
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7834 , H01L29/7835
摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).

106. 发明授权

US07902625B2 Metal-gate thermocouple 有权
标题翻译：金属栅极热电偶
公开(公告)号：US07902625B2
公开(公告)日：2011-03-08
申请号：US12106557
申请日：2008-04-21
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L31/058
CPC分类号： H01L35/32 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A metal gate thermocouple is provided. The thermocouple is configured to measure local temperatures of a device. The thermocouple is a passive device which senses temperature using the thermoelectric principle that when two dissimilar electrically conductive materials are joined, an electrical potential (voltage) is developed between the two materials. The voltage between the materials varies with the temperature of the junction (joint) between the materials. The thermocouple device includes a first conductor comprising a first material formed over a thin oxide layer or a shallow trench isolation (STI) structure and a second conductor comprising a second material formed over the thin oxide layer or the STI structure. The second conductor overlaps with the first conductor to form a thermocouple junction or dimension at least more than an alignment tolerance. The first and second materials are chosen such that the thermocouple junction formed between them exhibits a non-zero Seebeck coefficient. A conductive film formed over the first conductor and the second conductor and a non-conductive void or film is formed over the thermocouple junction.
摘要翻译：提供金属栅极热电偶。热电偶被配置为测量设备的局部温度。热电偶是使用热电原理感应温度的无源器件，当两种不同的导电材料接合时，两种材料之间产生电位（电压）。材料之间的电压随着材料之间的接头（接头）的温度而变化。热电偶装置包括第一导体，其包括在薄氧化物层或浅沟槽隔离（STI）结构上形成的第一材料，以及包括在薄氧化物层或STI结构上形成的第二材料的第二导体。第二导体与第一导体重叠以形成至少大于对准公差的热电偶结或尺寸。选择第一和第二材料使得它们之间形成的热电偶结点呈现非零塞贝克系数。形成在第一导体和第二导体上的导电膜和不导电的空隙或膜形成在热电偶结上。

107. 发明授权

US07902608B2 Integrated circuit device with deep trench isolation regions for all inter-well and intra-well isolation and with a shared contact to a junction between adjacent device diffusion regions and an underlying floating well section 有权
标题翻译：具有深沟槽隔离区域的集成电路器件，用于所有阱间和阱内隔离，并且与相邻器件扩散区域和下面的浮动阱部分之间的连接处共享接触
公开(公告)号：US07902608B2
公开(公告)日：2011-03-08
申请号：US12473324
申请日：2009-05-28
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/772 , H01L21/70
CPC分类号： H01L27/0207 , H01L21/823481 , H01L21/823493 , H01L27/092 , H01L27/11 , H01L27/1104
摘要： Disclosed are embodiments of an improved integrated circuit device structure (e.g., a static random access memory array structure or other integrated circuit device structure incorporating both P-type and N-type devices) and a method of forming the structure that uses DTI regions for all inter-well and intra-well isolation and, thereby provides a low-cost isolation scheme that avoids FET width variations due to STI-DTI misalignment. Furthermore, because the DTI regions used for intra-well isolation effectively create some floating well sections, which must each be connected to a supply voltage (e.g., Vdd) to prevent threshold voltage (Vt) variations, the disclosed integrated circuit device also includes a shared contact to a junction between the diffusion regions of adjacent devices and an underlying floating well section. This shared contact eliminates the cost and area penalties that would be incurred if a discrete supply voltage contact was required for each floating well section.
摘要翻译：公开了改进的集成电路器件结构（例如，并入P型和N型器件的静态随机存取存储器阵列结构或其他集成电路器件结构）的实施例，以及形成使用DTI区域的结构的方法从而提供了一种低成本的隔离方案，可避免由于STI-DTI失准导致的FET宽度变化。此外，由于用于井内隔离的DTI区域有效地创建了一些浮动阱区段，其必须各自连接到电源电压（例如Vdd）以防止阈值电压（Vt）变化，所公开的集成电路器件还包括与相邻设备的扩散区域和下面的浮动井段之间的连接处共享接触。这种共享联系消除了如果每个浮动井段需要离散的电源电压接触将导致的成本和面积罚款。

108. 发明授权

US07851865B2 Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure 有权
标题翻译：具有合并源极/漏极硅化物的鳍型场效应晶体管结构和形成结构的方法
公开(公告)号：US07851865B2
公开(公告)日：2010-12-14
申请号：US11873521
申请日：2007-10-17
申请人： Brent A. Anderson , Andres Bryant , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.
摘要翻译：这里公开了多鳍片式场效应晶体管（即，多鳍式双栅极或三栅极场效应晶体管）的设计结构的实施例，其中多个散热片部分或完全由高导电材料（例如，金属硅化物）。以这种方式合并散热片使串联电阻最小化，栅极和源极/漏极区之间的寄生电容几乎不增加。以这种方式合并半导体散热片也允许每个源极/漏极区域通过单个触点通孔接触，以及该触点通孔的更灵活的放置。

109. 发明授权

US07709313B2 High performance capacitors in planar back gates CMOS 失效
标题翻译：平面后门CMOS中的高性能电容器
公开(公告)号：US07709313B2
公开(公告)日：2010-05-04
申请号：US11160999
申请日：2005-07-19
申请人： Andres Bryant , Edward J. Nowak , Richard Q. Williams
发明人： Andres Bryant , Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0811 , H01L28/40 , H01L29/78648 , Y10T436/235 , Y10T436/25125 , Y10T436/2525 , Y10T436/25375
摘要： A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.
摘要翻译：一种双栅极CMOS结构的制造方法和器件。该结构包括绝缘层中的第一板和与第一板电对应的绝缘层之上的第二板。隔离结构在第一板和第二板之间。

110. 发明授权

US07659155B2 Method of forming a transistor having gate and body in direct self-aligned contact 失效
标题翻译：形成具有直接自对准接触的门和体的晶体管的方法
公开(公告)号：US07659155B2
公开(公告)日：2010-02-09
申请号：US11683470
申请日：2007-03-08
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
IPC分类号： H01L29/78
CPC分类号： H01L29/78615 , H01L29/783
摘要： A transistor having a directly contacting gate and body and related methods are disclosed. In one embodiment, the transistor includes a gate; a body; and a dielectric layer extending over the body to insulate the gate from the body along an entire surface of the body except along a portion of at least a sidewall of the body, wherein the gate is in direct contact with the body at the portion. One method may include providing the body; forming a sacrificial layer that contacts at least a portion of a sidewall of the body; forming a dielectric layer about the body except at the at least a portion; removing the sacrificial layer; and forming the gate about the body such that the gate contacts the at least a portion of the sidewall of the body.
摘要翻译：公开了一种具有直接接触门和体的晶体管及相关方法。在一个实施例中，晶体管包括栅极; 身体; 以及电介质层，其延伸到所述主体上，以沿着所述主体的至少一个侧壁的一部分沿着所述主体的整个表面使所述门与所述主体绝缘，其中所述门在所述部分处与所述主体直接接触。一种方法可以包括提供身体; 形成与身体的侧壁的至少一部分接触的牺牲层; 在所述至少一部分之外形成围绕所述主体的介电层; 去除牺牲层; 以及围绕所述主体形成所述门，使得所述门接触所述主体的侧壁的至少一部分。

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