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    • 101. 发明申请
    • Reduced cross-talk signaling circuit and method
    • 减少串扰信号电路和方法
    • US20070046389A1
    • 2007-03-01
    • US11209549
    • 2005-08-23
    • Daniel DrepsAnand HaridassBao TruongJoel Ziegelbein
    • Daniel DrepsAnand HaridassBao TruongJoel Ziegelbein
    • H01P5/00
    • H04L25/0272H04B3/32
    • Signaling between two or more ICs use a signaling scheme wherein a reference signal is generated at the driver side and the receiver side. The driver side reference signal is coupled to the receiver side reference signal with a transmission line channel forming a reference channel. Data signal channels are paired with a reference channel between each two adjacent data channels. Adjacent pairs of data signal channels are each separated with an empty wiring channel. The paired data signals are received in one input of a differential receiver. The reference signal of the reference channel between the two paired data channels is coupled to the other input of the two differential receivers. Coupling from the paired data channels to the reference channel appears a common mode noise and is rejected by the differential receivers. The number of channels is reduced from a full differential signaling scheme.
    • 两个或多个IC之间的信令使用信令方案,其中在驱动器侧和接收机侧产生参考信号。 驱动器侧参考信号通过形成参考通道的传输线路通道耦合到接收机侧参考信号。 数据信号通道与每两个相邻数据通道之间的参考通道配对。 相邻的数据信号通道对都分开一个空的布线通道。 成对的数据信号在差分接收机的一个输入端被接收。 两个成对数据信道之间的参考信道的参考信号耦合到两个差分接收机的另一个输入端。 从配对数据通道耦合到参考通道出现共模噪声,并被差分接收器拒绝。 信道数量从全差分信令方案中减少。
    • 102. 发明申请
    • Programmable driver delay
    • 可编程驱动器延时
    • US20070046335A1
    • 2007-03-01
    • US11211955
    • 2005-08-25
    • Wiren BeckerAnand HaridassBao Truong
    • Wiren BeckerAnand HaridassBao Truong
    • H03K19/00
    • H03K5/00H03K5/135H04L25/0276
    • Data busses are configured as N differential channels driven by a data signal and its complement through two off-chip drivers (OCDs). Each OCD is preceded by a programmable delay element and a two way MUX. The two data channels either transmit the data signals or a common clock signal as determined by a select signal from a skew controller. The differential signals are received in a differential receiver and a phase detector. The output of the phase detector in each differential channel is routed through an Nx1 MUX. The Nx1 MUX is controlled by the skew controller. The output of the Nx1 MUX is fed back as a phase error feedback signal to the skew controller. Each differential data channel is sequentially selected and the programmable delays are adjusted until the phase error feedback signal from the selected phase detector reaches a predetermined minimum allowable value. Periodic adjustment may be implemented for calibration.
    • 数据总线被配置为由数据信号驱动的N个差分信道及其通过两个片外驱动器(OCD)的补码。 每个OCD之前都有可编程延迟元件和双向MUX。 两个数据通道传输数据信号或由偏斜控制器的选择信号确定的公共时钟信号。 差分信号在差分接收机和相位检测器中被接收。 每个差分信道中的相位检测器的输出通过Nx1 MUX进行路由。 Nx1 MUX由偏斜控制器控制。 Nx1 MUX的输出作为相位误差反馈信号反馈到歪斜控制器。 顺序地选择每个差分数据通道,并且调整可编程延迟,直到来自所选相位检测器的相位误差反馈信号达到预定的最小允许值。 可以进行定期调整以进行校准。
    • 104. 发明申请
    • System and method for automatic insertion of on-chip decoupling capacitors
    • 自动插入片上去耦电容的系统和方法
    • US20060190892A1
    • 2006-08-24
    • US11054916
    • 2005-02-10
    • Anand HaridassAndreas HuberErich KlinkJochen Supper
    • Anand HaridassAndreas HuberErich KlinkJochen Supper
    • G06F17/50
    • G06F17/5045G06F2217/78
    • A system and method for automatic insertion of on-chip decoupling capacitors are provided. With the system and method, an integrated circuit design is partitioned into cells and the noise distribution per cell of an integrated circuit is determined. This noise distribution may be generated using any of a number of different known mechanisms and generally results in a noise-map being generated for the integrated circuit. Thereafter, a mapping function is applied to the noise map for each cell to determine a required capacitance for the cells of the integrated circuit. From this required capacitance per cell, the necessary decoupling capacitors may be identified as well as the location for insertion of these decoupling capacitors. In a similar manner, decoupling capacitors may be removed from cells of the integrated circuit based upon the determined required capacitance per cell.
    • 提供一种用于自动插入片上去耦电容器的系统和方法。 利用该系统和方法,将集成电路设计划分为单元,确定集成电路的每个单元的噪声分布。 该噪声分布可以使用多个不同的已知机构中的任何一个产生,并且通常导致为集成电路产生噪声映射。 此后,将映射函数应用于每个单元的噪声图,以确定集成电路的单元所需的电容。 根据每个电池所需的电容,可以识别必要的去耦电容以及插入这些去耦电容器的位置。 以类似的方式,可以基于每个单元所确定的所需电容从集成电路的单元去除去耦电容器。
    • 105. 发明授权
    • Boundary scannable one bit precompensated CMOS driver with compensating pulse width control
    • 边界可扫描一位预补偿CMOS驱动器,具有补偿脉宽控制
    • US06772250B2
    • 2004-08-03
    • US09810058
    • 2001-03-15
    • Daniel Mark DrepsAnand HaridassBao Gia-Harvey Truong
    • Daniel Mark DrepsAnand HaridassBao Gia-Harvey Truong
    • G06F1300
    • G06F13/4077H03K19/00346H03K19/017581
    • An improved data driver, method, and system for driving data with an improved slew rate and eye opening is provided. In one embodiment, the data driver includes a non-precompensating data driver and a precompensating data driver. The non-precompensating driver generates a non-precompensating output data pulse corresponding to input data. The non-precompensating data driver generates a pulse in response to every input data bit received. The precompensating driver generates the precompensating pulse only in response to a transition from one data state to a second data state between consecutive data bits. The precompensating data pulse is shorter in duration than the non-precompensating output data. The output data from the data drive is the sum of the non-precompensating output data pulse and the precompensating output data pulse.
    • 提供了一种改进的数据驱动程序,方法和系统,用于驱动具有改进的压摆率和眼睛开度的数据。 在一个实施例中,数据驱动器包括非预补偿数据驱动器和预补偿数据驱动器。 非预补偿驱动器产生对应于输入数据的非预补偿输出数据脉冲。 非预补偿数据驱动器响应于接收的每个输入数据位产生脉冲。 预补偿驱动器仅响应于在连续数据位之间从一个数据状态到第二数据状态的转变而产生预补偿脉冲。 预补偿数据脉冲的持续时间比非预补偿输出数据短。 来自数据驱动器的输出数据是非预补偿输出数据脉冲和预补偿输出数据脉冲之和。