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101. 发明申请

US20100044769A1 METHOD OF MANUFACTURE OF CONTACT PLUG AND INTERCONNECTION LAYER OF SEMICONDUCTOR DEVICE 有权
标题翻译：触点插头和半导体器件互连层的制造方法
公开(公告)号：US20100044769A1
公开(公告)日：2010-02-25
申请号：US12610022
申请日：2009-10-30
申请人： Hiroyuki KUTSUKAKE , Yasuhiko MATSUNAGA , Shoichi MIYAZAKI
发明人： Hiroyuki KUTSUKAKE , Yasuhiko MATSUNAGA , Shoichi MIYAZAKI
IPC分类号： H01L29/78
CPC分类号： H01L23/485 , H01L27/0207 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas.
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底的第一表面上沿着第一方向形成两个第一栅电极和在每个第一栅电极下夹着沟道区的源/漏区，形成第一层间绝缘层以填充在所述第一栅电极之间的区域中，降低所述第一层间绝缘层的顶部，在所述第一层间绝缘层上沉积第二层间绝缘层和所述第一栅电极，使所述第二层间绝缘层的表面平坦化，以及形成互连层和第一层间绝缘层和第二层间绝缘层中的接触塞，使得接触插塞与互连层和源极/漏极区之一接触。

102. 发明申请

US20090239365A1 NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20090239365A1
公开(公告)日：2009-09-24
申请号：US12480383
申请日：2009-06-08
申请人： Yasuhiko MATSUNAGA
发明人： Yasuhiko MATSUNAGA
IPC分类号： H01L21/71 , H01L21/28
CPC分类号： H01L27/115 , H01L27/11526 , H01L27/11529
摘要： A nonvolatile semiconductor memory that allows simultaneous implementation of high performance transistors in a low-voltage circuit region and transistors with high withstand voltages in a high-voltage circuit region. The nonvolatile semiconductor memory includes a cell array region that comprises aligned memory cell transistors, each including a control gate electrode, which includes a metal silicide film, an inter-gate insulating film below the control gate electrode, a floating gate electrode below the inter-gate insulating film, and a tunnel insulating film under the floating gate electrode; a high-voltage circuit region arranged in a periphery of the cell array region and including a high voltage transistor, which includes a first gate insulating film thicker than the tunnel insulating film; and a low-voltage circuit region that is arranged in a different position than the high-voltage circuit region arranged in the periphery of the cell array region and that includes a low-voltage transistor, which includes a gate electrode and a second gate insulating film thinner than the first gate insulating film below the gate electrode.
摘要翻译：一种非易失性半导体存储器，其允许在高压电路区域中同时实现低电压电路区域中的高性能晶体管和在高压电路区域中具有高耐受电压的晶体管。非易失性半导体存储器包括：单元阵列区域，其包括排列的存储单元晶体管，每个存储单元晶体管包括控制栅电极，其包括金属硅化物膜，位于控制栅极电极下方的栅极间绝缘膜，栅极绝缘膜和在浮栅电极下方的隧道绝缘膜; 布置在电池阵列区域的外围并包括高压晶体管的高压电路区域，其包括比隧道绝缘膜厚的第一栅极绝缘膜; 以及低压电路区域，其布置在与布置在电池阵列区域周围的高电压电路区域不同的位置，并且包括低电压晶体管，该低压晶体管包括栅极电极和第二栅极绝缘膜比栅电极下方的第一栅绝缘膜薄。

103. 发明申请

US20090167520A1 COMMUNICATION NETWORK FAILURE DETECTION SYSTEM, AND COMMUNICATION NETWORK FAILURE DETECTION METHOD AND FAILURE DETECTION PROGRAM 有权
标题翻译：通信网络故障检测系统和通信网络故障检测方法和故障检测程序
公开(公告)号：US20090167520A1
公开(公告)日：2009-07-02
申请号：US11994954
申请日：2006-07-11
申请人： Yoshinori Watanabe , Yasuhiko Matsunaga
发明人： Yoshinori Watanabe , Yasuhiko Matsunaga
IPC分类号： G08B29/00
CPC分类号： H04L41/064 , H04L41/065 , H04L43/00 , H04L43/022 , H04L43/16
摘要： The system for detecting a failure on a communication network according to an objective basis by analyzing an alarm log output by a management server of the communication network and evaluating a degree of abnormality of the communication network tracing back to a more significant factor causing the alarm, calculates an occurrence intensity of the more significant factor 500 causing an alarm based on the recording contents of the alarm, and detects a failure derived from the more significant factor of the communication network based on the calculated intensity of occurrence of said more significant factor 500.
摘要翻译：通过分析由通信网络的管理服务器输出的告警日志并且将通信网络跟踪的异常程度评估回到导致报警的更重要因素，根据客观基础来检测通信网络上的故障的系统，基于所述警报的记录内容计算所述更重要因素500的发生强度，并基于计算出的所述更重要因子500的出现强度来检测从通信网络的更重要因素导出的故障。

104. 发明申请

US20090021982A1 SEMICONDUCTOR MEMORY DEVICE AND DATA ERASE METHOD THEREOF 有权
标题翻译：半导体存储器件及其数据擦除方法
公开(公告)号：US20090021982A1
公开(公告)日：2009-01-22
申请号：US12175008
申请日：2008-07-17
申请人： Yasuhiko MATSUNAGA , Fumitaka ARAI
发明人： Yasuhiko MATSUNAGA , Fumitaka ARAI
IPC分类号： G11C16/04 , G11C16/06 , G11C7/00
CPC分类号： G11C16/0483 , G11C11/5635 , G11C16/16 , G11C2211/565
摘要： A semiconductor memory device includes a memory cell array which includes a plurality of memory cell strings each including a plurality of memory cells and a first dummy cell, which have current paths connected in series at one end and the other end thereof, a plurality of first and second select transistors, a source line, and a bit line, wherein the first dummy cell is disposed on the source line side such that one end and the other end of the current path thereof are connected between the first select transistor and the memory cell, and a threshold voltage of the first dummy cell is higher than a neutral threshold voltage.
摘要翻译：半导体存储器件包括存储单元阵列，该存储单元阵列包括多个存储单元串，每个存储单元串包括多个存储单元和第一虚单元，该第一虚单元具有在一端串联连接的电流通路和另一端，多个第一以及第二选择晶体管，源极线和位线，其中第一虚设单元设置在源极侧，使得其电流通路的一端和另一端连接在第一选择晶体管和存储单元之间并且第一虚拟单元的阈值电压高于中性阈值电压。

105. 发明申请

US20080290396A1 SEMICONDUCTOR MEMORY 审中-公开
标题翻译：半导体存储器
公开(公告)号：US20080290396A1
公开(公告)日：2008-11-27
申请号：US12125546
申请日：2008-05-22
申请人： Yasuhiko MATSUNAGA , Yuji Takeuchi , Takashi Shigeoka
发明人： Yasuhiko MATSUNAGA , Yuji Takeuchi , Takashi Shigeoka
IPC分类号： H01L29/00
CPC分类号： H01L27/105 , H01L27/0207 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory according to an aspect of this invention comprises a semiconductor substrate which includes a memory cell array region and an interconnect line region adjoining the memory cell array region, memory cells which are provided in the memory cell array region, contact plugs which are provided in the interconnect line region, and control gate lines which are provided so as to extend from the interconnect line region to the memory cell array region and which connect the contact plugs with the memory cells, wherein the control gate lines provided in the memory cell array region include metal silicide and the control gate lines provided in the interconnect line region include no metal silicide at any part of the interconnect line region.
摘要翻译：根据本发明的一个方面的半导体存储器包括半导体衬底，其包括存储单元阵列区域和与存储单元阵列区域相邻的互连线区域，设置在存储单元阵列区域中的存储单元，提供的接触插头以及控制栅极线，其设置为从互连线区域延伸到存储单元阵列区域，并将接触插头与存储器单元连接，其中设置在存储单元阵列中的控制栅极线区域包括金属硅化物，并且设置在互连线区域中的控制栅极线在互连线区域的任何部分不包括金属硅化物。

106. 发明申请

US20080251881A1 SEMICONDUCTOR DEVICE WITH DOUBLE BARRIER FILM 失效
标题翻译：具有双屏障膜的半导体器件
公开(公告)号：US20080251881A1
公开(公告)日：2008-10-16
申请号：US12143597
申请日：2008-06-20
申请人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
发明人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
IPC分类号： H01L29/00
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.
摘要翻译：一种半导体器件，包括第一绝缘层，第二绝缘层，第一阻挡膜，第二阻挡膜，扩散层。该装置还包括上接触孔，下接触孔和接触塞。上接触孔穿透第二绝缘层，并且在第二阻挡膜中具有底部。底部的宽度大于在与沟槽宽度方向交叉的方向上测量的在第一绝缘层中形成的沟槽。下接触孔穿过第一绝缘层和第一阻挡膜，经由沟槽与第一接触孔连通并设置在扩散层上。下接触孔的上部具有与沟槽相同的宽度。接触塞设置在上接触孔和下接触孔中。

107. 发明授权

US07382649B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07382649B2
公开(公告)日：2008-06-03
申请号：US11148336
申请日：2005-06-09
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
IPC分类号： G11C11/34
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes memory cell units, each having memory cell transistors aligned in a column direction and capable of writing and erasing electronic data; and contacts on active areas, arranged on both sides of memory cell unit arrays in which the memory cell units are serially connected in the column direction, and the contacts on active areas are shared by the memory cell unit arrays; wherein, the respective memory cell unit arrays are located having a periodical shift length equal to and or more than the integral multiple length of the periodical length of the memory cell units aligned in the column direction so as to be staggered from each other as compared with neighboring memory cell unit arrays aligned in the row direction.
摘要翻译：非易失性半导体存储器包括存储单元单元，每个存储单元单元具有在列方向上排列的存储单元晶体管，并且能够写入和擦除电子数据; 以及布置在存储单元单元在列方向上串联连接的存储单元单元阵列的两侧的有源区上的触点，并且有源区上的触点由存储单元单元阵列共享; 其中，各个存储单元单元阵列的周期性移位长度等于或大于沿列方向排列的存储单元单元的周期长度的整数倍长度，以便与第相邻的存储单元单元阵列在行方向上排列。

108. 发明授权

US07149116B2 Nonvolatile semiconductor memory and programming method for the same 有权
公开(公告)号：US07149116B2
公开(公告)日：2006-12-12
申请号：US11337653
申请日：2006-01-24
申请人： Makoto Sakuma , Fumitaka Arai , Riichiro Shirota , Yasuhiko Matsunaga
发明人： Makoto Sakuma , Fumitaka Arai , Riichiro Shirota , Yasuhiko Matsunaga
IPC分类号： G11C11/34
CPC分类号： G11C16/10
摘要： A semiconductor memory has a memory cell matrix including a plurality of first and second cell columns alternately arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors, and peripheral circuits configured to drive the memory cell matrix and to read information from the memory cell matrix. The peripheral circuit encompasses (a) a leading program circuit configured to write first data into memory cell transistors in the first cell columns, (b) a lagging program circuit configured to write second data into memory cell transistors in the second cell columns after the first data are written, and (c) a voltage controller configured to control variation of threshold voltages for the memory cell transistors of the first cell columns.

109. 发明授权

US07064049B2 Ion implantation method, SOI wafer manufacturing method and ion implantation system 有权
标题翻译：离子注入法，SOI晶片制造方法和离子注入系统
公开(公告)号：US07064049B2
公开(公告)日：2006-06-20
申请号：US10630293
申请日：2003-07-30
申请人： Hiroyuki Ito , Yasuhiko Matsunaga
发明人： Hiroyuki Ito , Yasuhiko Matsunaga
IPC分类号： H01L21/26
CPC分类号： H01J37/08 , H01J2237/0817 , H01J2237/31701 , H01L21/26506 , H01L21/76254
摘要： The present invention provides an ion implantation method which can achieve sufficient throughput by increasing a beam current even in the case of ions with a small mass number or low-energy ions, an SOI wafer manufacturing method, and an ion implantation system. When ions are implanted by irradiating a semiconductor substrate with an ion beam, predetermined gas is excited in a pressure-reduced chamber to generate plasma containing predetermined ions, a magnetic field is formed by a solenoid coil or the like along an extraction direction when the ions are extracted to the outside of the chamber, and the ions are extracted from the chamber with predetermined extraction energy. The formation of the magnetic field promotes ion extraction, but this magnetic field has no influence on an advancing direction of the extracted ions. Therefore, the ion beam current can be kept at a high level-to contribute to the ion implantation.
摘要翻译：本发明提供了一种离子注入方法，其即使在具有小质量或低能量离子的离子，SOI晶片制造方法和离子注入系统的情况下也可以通过增加射束电流来实现足够的通过量。当通过用离子束照射半导体衬底来注入离子时，在减压室中激发预定的气体以产生含有预定离子的等离子体，当离子的离子沿着提取方向由螺线管线圈等形成磁场时被提取到室的外部，并且以预定的提取能从室抽出离子。磁场的形成促进离子提取，但是该磁场对提取的离子的前进方向没有影响。因此，离子束电流可以保持在高水平 - 有助于离子注入。

110. 发明申请

US20050249121A1 Optimization of packet transmission path 有权
标题翻译：分组传输路径的优化
公开(公告)号：US20050249121A1
公开(公告)日：2005-11-10
申请号：US10515263
申请日：2003-05-21
申请人： Yasuhiko Matsunaga
发明人： Yasuhiko Matsunaga
IPC分类号： H04W40/04 , H04L12/28 , H04L12/721 , H04L12/733 , H04L29/06 , H04W4/16 , H04W12/06 , H04W28/06 , H04W40/02 , H04W40/34 , H04W84/12 , H04W88/08 , H04Q7/20
CPC分类号： H04L45/00 , H04L45/04 , H04L45/12 , H04L63/04 , H04L63/08 , H04W12/06 , H04W40/02
摘要： A method is disclosed for optimizing packet transmission paths in a mobile communication network (400) in which packets are transmitted and received between mobile stations (10-14) or between a mobile station and a fixed network (120) by way of a plurality of packet transmission device (60-64, 70-72, 80, and 81) and radio base stations (50-57). When a mobile station uses a service that is provided by a fixed network (300), imposed are applied on the packet transmission path such that packets pass by way of specific packet transmission devices (80 and 81) depending on the fixed network (external network) 300. When the mobile station uses a service that is provided by the mobile communication network (400), on the other hand, no restrictions are imposed on the packet transmission path, and the packet transmission path is thus set such that the link costs are a minimum.
摘要翻译：公开了一种用于优化移动通信网络（400）中的分组传输路径的方法，其中分组在移动站（10-14）之间或在移动站和固定网络（120）之间通过多个分组传输设备（60-64,70-72,80和81）和无线电基站（50-57）。当移动站使用由固定网络（300）提供的服务时，施加在分组传输路径上，使得分组根据固定网络（外部网络）通过特定分组传输设备（80和81））300.当移动台使用由移动通信网络（400）提供的服务时，另一方面对分组传输路径没有限制，并且分组传输路径被设置为使得链路成本是最小的。

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