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101. 发明申请

US20100162216A1 WORKLOAD PERFORMANCE PROJECTION VIA SURROGATE PROGRAM ANALYSIS FOR FUTURE INFORMATION HANDLING SYSTEMS 失效
标题翻译：通过对未来信息处理系统进行现场程序分析的工作负载性能预测
公开(公告)号：US20100162216A1
公开(公告)日：2010-06-24
申请号：US12343467
申请日：2008-12-23
申请人： Robert H. Bell, JR. , Luigi Brochard , Donald Robert DeSota , Venkat R. Indukuru , Rajendra D. Panda , Sameh S. Sharkawi
发明人： Robert H. Bell, JR. , Luigi Brochard , Donald Robert DeSota , Venkat R. Indukuru , Rajendra D. Panda , Sameh S. Sharkawi
IPC分类号： G06F9/44
CPC分类号： G06F11/3419 , G06F11/3414 , G06F11/3457 , G06F2201/865 , G06F2201/88
摘要： A performance projection system includes a test IHS and multiple currently existing IHSs. The performance projection system includes user application software and surrogate programs that execute on currently existing IHSs. The performance projection system measures user application software and surrogate program performance during execution on currently existing IHSs. The performance projection systems measures runtime program performance during execution of surrogate programs on a future semiconductor die IC design model or virtualized future system. Designers normalize and compare surrogate program runtime performance data with user application software performance data. Designers un-normalize the normalized runtime performance data to generate a projection of runtime performance on the future system.
摘要翻译：性能投影系统包括测试IHS和多个当前存在的IHS。性能投影系统包括在当前存在的IHS上执行的用户应用软件和代理程序。性能投影系统在目前现有的IHSs的执行过程中测量用户应用软件和代理程序性能。性能投影系统在未来的半导体芯片IC设计模型或虚拟化未来系统执行替代程序期间测量运行时程序性能。设计师将代理程序运行时性能数据与用户应用软件性能数据进行规范化和比较。设计师对规范化的运行时性能数据进行非规范化，以生成对未来系统的运行时性能的投影。

102. 发明申请

US20100161282A1 WORKLOAD PERFORMANCE PROJECTION FOR FUTURE INFORMATION HANDLING SYSTEMS USING MICROARCHITECTURE DEPENDENT DATA 有权
标题翻译：使用微观依赖数据的未来信息处理系统的工作表现投影
公开(公告)号：US20100161282A1
公开(公告)日：2010-06-24
申请号：US12343482
申请日：2008-12-24
申请人： Robert H. Bell, JR. , Luigi Brochard , Donald Robert DeSota , Venkat R. Indukuru , Rajendra D. Panda , Sameh S. Sharkawi
发明人： Robert H. Bell, JR. , Luigi Brochard , Donald Robert DeSota , Venkat R. Indukuru , Rajendra D. Panda , Sameh S. Sharkawi
IPC分类号： G06F15/00
CPC分类号： G06F11/3612 , G06F11/3428 , G06F11/3457 , G06F11/3466 , G06F2201/88
摘要： A performance projection system includes a test IHS and a currently existing IHS. The performance projection system includes surrogate programs and user application software. The test IHS or simulator includes a processor with hardware (HW) counter(s) and an L1 cache. The test IHS employs a memory that includes a virtual future IHS, currently existing IHS, surrogate programs, and user application software for determination of runtime and HW counter performance data. The user application software and surrogate programs execute on the currently existing IHS to provide designers with runtime data and HW counter or microarchitecture dependent data. Designers execute surrogate programs on the future IHS to provide runtime and HW counter data. Designers normalize and weight the runtime and HW counter data to provide a representative surrogate program for comparison to user application software performance on the future IHS. Using a scaling factor, designers may generate a projection of runtime performance for the user application software executing on the future IHS.
摘要翻译：性能投影系统包括测试IHS和当前存在的IHS。性能投影系统包括代理程序和用户应用软件。测试IHS或模拟器包括具有硬件（HW）计数器和L1高速缓存的处理器。测试IHS采用包含虚拟未来IHS，现有IHS，替代程序和用户应用软件的存储器，用于确定运行时和硬件计数器性能数据。用户应用软件和代理程序在当前现有的IHS上执行，为设计人员提供运行时数据和HW计数器或微体系结构依赖数据。设计人员在未来的IHS上执行代理程序来提供运行时和硬件计数器数据。设计师对运行时和HW计数器数据进行规范化和加权，以提供代表性的代理程序，以便与未来IHS的用户应用软件性能进行比较。使用缩放因子，设计人员可以为未来IHS上执行的用户应用软件生成运行时性能的投影。

103. 发明申请

US20100153700A1 Multicore Processor And Method Of Use That Configures Core Functions Based On Executing Instructions 有权
标题翻译：基于执行指令配置核心功能的多核处理器和使用方法
公开(公告)号：US20100153700A1
公开(公告)日：2010-06-17
申请号：US12335921
申请日：2008-12-16
申请人： Louis B. Capps, JR. , Michael J. Shapiro , Robert H. Bell, JR. , Thomas E. Cook , William E. Burky
发明人： Louis B. Capps, JR. , Michael J. Shapiro , Robert H. Bell, JR. , Thomas E. Cook , William E. Burky
IPC分类号： G06F9/22 , G06F9/318
CPC分类号： G06F9/5061 , G06F9/3842 , G06F9/3851 , G06F9/3887
摘要： A processor having multiple cores coordinates functions performed on the cores to automatically, dynamically and repeatedly reconfigure the cores for optimal performance based on characteristics of currently executing software. A core running a thread detects a multi-core characteristic of the thread and assigns one or more other cores to the thread to dynamically combine the cores into what functionally amounts to a common core for more efficient execution of the thread.
摘要翻译：具有多个核的处理器协调在核上执行的功能，以基于当前执行的软件的特性自动，动态地和重复地重新配置核以获得最佳性能。运行线程的核心检测线程的多核特性，并为线程分配一个或多个其他内核，以将内核动态组合到功能上相当于共同核心的内核，从而更有效地执行线程。

104. 发明申请

US20100049963A1 Multicore Processor and Method of Use That Adapts Core Functions Based on Workload Execution 有权
标题翻译：多核处理器和基于工作负载执行的核心功能的使用方法
公开(公告)号：US20100049963A1
公开(公告)日：2010-02-25
申请号：US12197357
申请日：2008-08-25
申请人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
IPC分类号： G06F9/00
CPC分类号： G06F15/7871
摘要： A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.
摘要翻译：处理器具有多个核心，每个核心具有相关功能以支持处理器操作。通过平衡应用于每个功能的资源，选择性地改变由核执行的功能以改善处理器操作。例如，每个核心包括一个现场可编程阵列，该阵列可以根据使用每个功能的操作次数，选择性地和动态地编程来执行诸如浮点函数或固定点功能的功能。作为另一示例，处理器被构建为具有比可以同时供电的更多数量的核，每个核与功能相关联，使得具有较低利用率的功能的核被选择性地关机。

105. 发明申请

US20090276190A1 Method and Apparatus For Evaluating Integrated Circuit Design Performance Using Basic Block Vectors, Cycles Per Instruction (CPI) Information and Microarchitecture Dependent Information 有权
标题翻译：使用基本块向量，每个指令周期（CPI）信息和微架构依赖信息来评估集成电路设计性能的方法和装置
公开(公告)号：US20090276190A1
公开(公告)日：2009-11-05
申请号：US12112034
申请日：2008-04-30
申请人： Robert H. Bell, JR. , Thomas W. Chen , Venkat R. Indukuru , Alexander E. Mericas , Pattabi M. Seshadri , Madhavi G. Valluri
发明人： Robert H. Bell, JR. , Thomas W. Chen , Venkat R. Indukuru , Alexander E. Mericas , Pattabi M. Seshadri , Madhavi G. Valluri
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/318357 , G01R31/318364
摘要： A test system or simulator includes an integrated circuit (IC) benchmark software program that executes workload program software on a semiconductor die IC design model. The benchmark software program includes trace, simulation point, basic block vector (BBV) generation, cycles per instruction (CPI) error, clustering and other programs. The test system also includes CPI stack program software that generates CPI stack data that includes microarchitecture dependent information for each instruction interval of workload program software. The CPI stack data may also include an overall analysis of CPI data for the entire workload program. IC designers may utilize the benchmark software and CPI stack program to develop a reduced representative workload program that includes CPI data as well as microarchitecture dependent information.
摘要翻译：测试系统或模拟器包括在半导体芯片IC设计模型上执行工作负载程序软件的集成电路（IC）基准软件程序。基准软件程序包括跟踪，仿真点，基本块向量（BBV）生成，每个指令周期（CPI）错误，聚类和其他程序。测试系统还包括生成CPI堆栈数据的CPI堆栈程序软件，包括工作负载程序软件的每个指令间隔的微架构依赖信息。 CPI堆栈数据还可以包括整个工作负载程序的CPI数据的总体分析。 IC设计人员可以利用基准软件和CPI堆栈程序来开发一个减少代表性的工作量程序，其中包括CPI数据以及微架构依赖信息。

106. 发明申请

US20090164759A1 Execution of Single-Threaded Programs on a Multiprocessor Managed by an Operating System 有权
标题翻译：在操作系统管理的多处理器上执行单线程序
公开(公告)号：US20090164759A1
公开(公告)日：2009-06-25
申请号：US11959821
申请日：2007-12-19
申请人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Michael A. Paolini , Michael Jay Shapiro
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/505 , G06F2209/5017
摘要： A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.
摘要翻译：一种用于在多核处理器内推测性地执行单线程程序的方法和装置，其包括识别所述多核处理器内的空闲核心，对所述单线程指令执行向前操作以识别所述单线程指令内的推测指令，并分配空闲核心以执行推测性指令。

107. 发明授权

US07543109B1 System and method for caching data in a blade server complex 失效
标题翻译：用于在刀片服务器组合中缓存数据的系统和方法
公开(公告)号：US07543109B1
公开(公告)日：2009-06-02
申请号：US12122448
申请日：2008-05-16
申请人： Robert H. Bell, Jr. , Jose R. Escalera , Octavian F. Herescu , Vernon W. Miller , Michael D. Roll
发明人： Robert H. Bell, Jr. , Jose R. Escalera , Octavian F. Herescu , Vernon W. Miller , Michael D. Roll
IPC分类号： G06F12/02
CPC分类号： G06F12/126 , G06F12/0888
摘要： A method for caching data in a blade computing complex includes providing a storage blade that includes a disk operative to store pages of data and a cache memory operative to store at least one of the pages. A processor blade is provided that includes a first memory area to store at least one of the pages and a second memory area configured to store an address of each of the pages and a hint value that is assigned to each of the pages. An address of each of the pages is stored in the second memory area, and a hint is assigned to each of the pages, where the hint is one of: likely to be accessed, may be accessed, and unlikely to be accessed. The page is then stored in storage blade cache memory based on the hint.
摘要翻译：一种用于在刀片计算复合体中缓存数据的方法包括提供包括可操作以存储数据页的盘的存储刀片和可存储至少一个页的高速缓冲存储器。提供了一种处理器刀片，其包括用于存储所述页面中的至少一个的第一存储器区域和被配置为存储每个页面的地址的第二存储器区域以及分配给每个页面的提示值。每个页面的地址被存储在第二存储器区域中，并且提示被分配给每个页面，其中提示是可能被访问的，可能被访问并且不可能被访问。然后基于提示将该页面存储在存储刀片缓存中。

108. 发明申请

US20090138683A1 Dynamic instruction execution using distributed transaction priority registers 审中-公开
标题翻译：使用分布式事务优先级寄存器的动态指令执行
公开(公告)号：US20090138683A1
公开(公告)日：2009-05-28
申请号：US11946615
申请日：2007-11-28
申请人： Louis B. Capps, JR. , Robert H. Bell, JR.
发明人： Louis B. Capps, JR. , Robert H. Bell, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30101 , G06F9/5011 , G06F2209/507 , Y02D10/22
摘要： A method, system and program are provided for dynamically assigning priority values to instruction threads in a computer system based on one or more predetermined thread performance tests, and using the assigned instruction priorities to determine how resources are used in the system. By storing the assigning priority values in thread priority registers distributed throughout the computer system, instructions from different threads that are dispatched through the system are allocated system resources based on the priority values assigned to the respective instruction threads. Priority values for individual threads may be updated with control software which tests thread performance and uses the test results to apply predetermined adjustment policies. The test results may be used to optimize the workload allocation of system resources by dynamically assigning thread priority values to individual threads using any desired policy, such as achieving thread execution balance relative to thresholds and to performance of other threads, reducing thread response time, lowering power consumption, etc.
摘要翻译：提供了一种方法，系统和程序，用于基于一个或多个预定的线程性能测试来动态地为计算机系统中的指令线程分配优先级值，并且使用所分配的指令优先级来确定如何在系统中使用资源。通过将分配的优先级值存储在整个计算机系统中分配的线程优先级寄存器中，基于分配给各个指令线程的优先级值，分配来自系统调度的不同线程的指令被分配给系统资源。可以使用测试线程性能的控制软件更新各个线程的优先级值，并使用测试结果来应用预定的调整策略。测试结果可用于通过使用任何期望的策略动态地将线程优先级值分配给各个线程来优化系统资源的工作量分配，例如实现相对于阈值的线程执行平衡以及其他线程的性能，减少线程响应时间，降低功耗等

109. 发明申请

US20090055153A1 Augmenting of Automated Clustering-Based Trace Sampling Methods by User-Directed Phase Detection 有权
标题翻译：通过用户定向相位检测来增强基于自动聚类的跟踪采样方法
公开(公告)号：US20090055153A1
公开(公告)日：2009-02-26
申请号：US11842337
申请日：2007-08-21
申请人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Pattabi R. Seshadri , John-David Wellman
发明人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Pattabi R. Seshadri , John-David Wellman
IPC分类号： G06F9/455
CPC分类号： G06F9/455 , G06F11/3636 , G06F11/3664
摘要： Computer implemented method, system, and computer usable program code for simulating processor operation in a data processing system. An instruction trace is generated, wherein the instruction trace includes markers specified by a user for identifying interval boundaries for at least one interval of the instruction trace. The instruction trace is divided into a plurality of intervals in consideration of the markers, and the plurality of intervals are formed into a plurality of interval clusters, wherein each interval cluster represents one phase of execution of the instruction trace. At least one interval from each of the plurality of interval clusters is selected as a trace sample to provide a plurality of trace samples, wherein each selected interval is of at least a minimum size, a simulation is performed using the plurality of trace samples, and a result of the simulation is provided to the user.
摘要翻译：用于在数据处理系统中模拟处理器操作的计算机实现的方法，系统和计算机可用程序代码。生成指令轨迹，其中指令轨迹包括由用户指定的用于识别指令轨迹的至少一个间隔的间隔边界的标记。考虑到标记，指令轨迹被分成多个间隔，并且多个间隔被形成为多个间隔簇，其中每个间隔簇表示指令轨迹的执行的一个阶段。选择来自多个间隔群集中的每一个的至少一个间隔作为跟踪样本以提供多个跟踪样本，其中每个选择的间隔至少为最小尺寸，使用多个迹线样本进行模拟，以及向用户提供模拟的结果。

110. 发明申请

US20080307203A1 Scaling Instruction Intervals to Identify Collection Points for Representative Instruction Traces 失效
标题翻译：缩放指令间隔以识别代表性指令跟踪的收集点
公开(公告)号：US20080307203A1
公开(公告)日：2008-12-11
申请号：US11758031
申请日：2007-06-05
申请人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
发明人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
IPC分类号： G06F9/30
CPC分类号： G06F11/36
摘要： A method, system, and computer program product are provided for identifying instructions to obtain representative traces. A phase instruction budget is calculated for each phase in a set of phases. The phase instruction budget is based on a weight associated with each phase and a global instruction budget. A starting index and an ending index are identified for instructions within a set of intervals in each phase in order to meet the phase instruction budget for that phase, thereby forming a set of interval indices. A determination is made as to whether the instructions within the set of interval indices meet the global instruction budget. Responsive to the global instruction budget being met, the set of interval indices are output as collection points for the representative traces.
摘要翻译：提供方法，系统和计算机程序产品用于识别指令以获得代表性迹线。针对一组阶段中的每个阶段计算相位指令预算。相位指令预算基于与每个阶段相关联的权重和全局指令预算。为了满足该阶段的相位指令预算，为每个阶段的一组间隔内的指令识别开始索引和结束索引，从而形成一组间隔索引。确定区间指标集内的指令是否符合全球指令预算。响应于满足全球指令预算，间隔指数的集合作为代表性跟踪的收集点输出。

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