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101. 发明授权

US08099620B2 Domain crossing circuit of a semiconductor memory apparatus 失效
标题翻译：半导体存储装置的域交叉电路
公开(公告)号：US08099620B2
公开(公告)日：2012-01-17
申请号：US12346675
申请日：2008-12-30
申请人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： G06F1/00 , G06F1/04 , G06F12/00 , H03K19/00 , H03L7/00 , G11C8/00
CPC分类号： G11C7/1051 , G06F1/12 , G11C7/1072 , G11C7/222
摘要： A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal.
摘要翻译：半导体存储器装置的域交叉电路，域交叉电路包括在基本上相同的时钟周期产生的第一和第二计数信号，并且相对于相同位组合数据参考内部时钟信号表示预定的时钟差，以及数据处理单元，被配置为响应于与外部时钟信号同步的输入数据，基于第二计数信号提供对应于输入数据的输出数据。

102. 发明授权

US08035431B2 Delay locked loop and delay locking method having burst tracking scheme 有权
标题翻译：具有脉冲串跟踪方案的延迟锁定环路和延迟锁定方法
公开(公告)号：US08035431B2
公开(公告)日：2011-10-11
申请号：US12494509
申请日：2009-06-30
申请人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/093
摘要： A Delay Locked Loop (DLL) includes a replica delay unit configured to delay an output clock to generate a feedback clock; a phase detector configured to measure a phase difference between the feedback clock and an input clock; a quantization unit configured to quantize the phase difference measured by the phase detector; and a delay unit configured to delay the input clock based on a quantization result from the quantization unit to generate the output clock.
摘要翻译：延迟锁定环（DLL）包括复制延迟单元，其被配置为延迟输出时钟以产生反馈时钟; 相位检测器，被配置为测量反馈时钟和输入时钟之间的相位差; 量化单元，被配置为量化由相位检测器测量的相位差; 以及延迟单元，被配置为基于来自量化单元的量化结果来延迟输入时钟，以产生输出时钟。

103. 发明申请

US20110241726A1 ON-DIE TERMINATION CIRCUIT 有权
标题翻译：端子终止电路
公开(公告)号：US20110241726A1
公开(公告)日：2011-10-06
申请号：US13012972
申请日：2011-01-25
申请人： Yong Ju KIM , Hyung Soo KIM , Hae Rang CHOI , Jae Min JANG
发明人： Yong Ju KIM , Hyung Soo KIM , Hae Rang CHOI , Jae Min JANG
IPC分类号： H03K19/003
CPC分类号： H04L25/0298
摘要： An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.
摘要翻译：片上终端电路包括：参考周期信号生成电路，其根据参考电压的电平生成基准周期信号;第一周期信号生成电路，其根据电压的电平生成第一周期信号; 周期比较电路，其将第一周期信号的周期与基准周期信号的周期进行比较，并计数多个驱动信号;以及驱动器电路，其响应于多个驱动信号而驱动该焊盘。

104. 发明授权

US08023356B2 Voltage level comparison circuit of semiconductor memory apparatus, voltage adjustment circuit using voltage level comparison circuit, and semiconductor memory apparatus using the same 失效
标题翻译：半导体存储装置的电压电平比较电路，使用电压电平比较电路的电压调整电路和使用其的半导体存储装置
公开(公告)号：US08023356B2
公开(公告)日：2011-09-20
申请号：US12336423
申请日：2008-12-16
申请人： Ic-Su Oh , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Ic-Su Oh , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal and to output the external voltage as the output voltage.
摘要翻译：半导体存储装置的电压调整电路包括：控制电压生成部，其被配置为响应于控制信号分配用于选择性地输出多个分配电压的外部电压作为控制电压，所述多个分配电压各自具有不同的电压电平，比较单元，被配置为包括电压供应单元，其被配置为响应于所述电平的电平而控制提供给第一节点的外部电压和第二节点，如果输出电压的电平高于参考电压的电平以及检测信号生成单元，被配置为根据输出电压和参考电压的电平来降低第一和第二节点的电位电平，并输出第二节点的电位电平作为检测信号，以及电压产生单元，被配置为根据检测信号的电位来驱动外部电压并输出外部电压作为输出电压。

105. 发明授权

US07990785B2 Delay locked loop circuit of semiconductor device 有权
标题翻译：半导体器件的延迟锁定环路
公开(公告)号：US07990785B2
公开(公告)日：2011-08-02
申请号：US12262517
申请日：2008-10-31
申请人： Hee-Woong Song , Kun-Woo Park , Yong-Ju Kim , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
发明人： Hee-Woong Song , Kun-Woo Park , Yong-Ju Kim , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C7/22 , G11C7/222 , G11C29/023 , G11C29/028 , H03L7/0812 , H03L7/089 , H03L7/095
摘要： A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference between an internal clock and a reference clock to output a state signal having a pulse width corresponding to the detected phase difference, a phase adjuster configured to generate a digital code for determining a delay time corresponding to the state signal for locking a phase of the internal clock, a digital-to-analog converter configured to convert the digital code to an analog voltage, and a multiphase delay signal generator configured to delay the internal clock according to a bias voltage corresponding to the analog voltage to feed back the delayed internal clock as the internal clock and generate multiphase delay signals.
摘要翻译：半导体存储器件包括可以根据高频系统时钟控制数据的输入/输出定时的延迟锁定环电路。半导体存储装置包括：相位比较器，被配置为检测内部时钟和参考时钟之间的相位差，以输出具有与检测到的相位差相对应的脉冲宽度的状态信号;相位调整器，被配置为生成用于确定对应于用于锁定内部时钟的相位的状态信号的延迟时间，配置成将数字代码转换为模拟电压的数模转换器，以及被配置为根据偏置来延迟内部时钟的多相延迟信号发生器对应于模拟电压的电压反馈延迟的内部时钟作为内部时钟，并产生多相延迟信号。

106. 发明授权

US07868663B2 Receiver circuit for use in a semiconductor integrated circuit 失效
标题翻译：用于半导体集成电路的接收器电路
公开(公告)号：US07868663B2
公开(公告)日：2011-01-11
申请号：US12171214
申请日：2008-07-10
申请人： Ic-Su Oh , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
发明人： Ic-Su Oh , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： G01R19/00 , G11C7/00 , H03F3/45
CPC分类号： H04L7/0337
摘要： A receiver circuit for sensing and transmitting input data in sync with a plurality of clock signals having mutually different phase sequentially enabled comprising a sense amplifier configured to receive, as offset voltages, first signals which can be obtained by amplifying the input data in sync with a first clock signal of the plurality of clock signals, being driven in sync with a second clock signal enabled subsequently to the first clock signal, and outputting second signals, and a discharging controller configured to control a discharging speed of the sense amplifier according to the offset voltages to control a driven speed of the sense amplifier.
摘要翻译：一种接收机电路，用于与具有相互不同相位的多个时钟信号同步地感测和发送输入数据，其顺序地使能，包括读出放大器，其被配置为接收作为偏移电压的第一信号，所述第一信号可以通过与所述多个时钟信号的第一时钟信号与与所述第一时钟信号之后使能的第二时钟信号同步地驱动，并输出第二信号;以及放电控制器，被配置为根据所述偏移来控制所述读出放大器的放电速度电压来控制读出放大器的驱动速度。

107. 发明申请

US20100315139A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100315139A1
公开(公告)日：2010-12-16
申请号：US12494403
申请日：2009-06-30
申请人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03L7/06
CPC分类号： H03L7/0816 , G11C7/1066 , G11C7/222 , H03L7/0805
摘要： A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.
摘要翻译：半导体存储器件能够响应于读取命令和CAS延迟信息而产生输出使能信号。半导体存储器件包括：延迟锁定环，被配置为检测外部时钟信号和反馈时钟信号的相位差，产生对应于检测到的相位差的延迟控制信号，并通过延迟外部时钟信号产生DLL时钟信号延迟一段时间对应于延迟控制信号，延迟配置为响应于延迟控制信号而输出有效信号作为输出使能复位信号;以及输出使能信号发生器，其被配置为响应于输出使能复位信号复位;以及通过对外部时钟信号和DLL时钟信号进行计数，响应于读取信号和CAS等待时间信号产生输出使能信号。

108. 发明授权

US07852132B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US07852132B2
公开(公告)日：2010-12-14
申请号：US12340912
申请日：2008-12-22
申请人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： H03L7/06
CPC分类号： H03K3/0322 , H03K5/1504 , H03K2005/00208 , H03L7/083 , H03L7/24
摘要： A semiconductor integrated circuit comprises a PLL (Phase Locked Loop (PLL) circuit configured to generate a control voltage in response to a frequency of a reference clock signal, and to generate a PLL clock signal having a frequency that corresponds to a level of the control voltage, and a voltage controlled oscillator configured to oscillate an output clock signal in response to the PLL clock signal, and to allow the PLL clock signal to have a frequency that corresponds to a level of the control voltage.
摘要翻译：半导体集成电路包括PLL（锁相环）电路，其被配置为响应于参考时钟信号的频率产生控制电压，并且产生具有对应于控制电平的频率的PLL时钟信号电压和被配置为响应于PLL时钟信号而振荡输出时钟信号的压控振荡器，并且允许PLL时钟信号具有对应于控制电压电平的频率。

109. 发明授权

US07808841B2 Data output circuit for semiconductor memory apparatus 有权
标题翻译：半导体存储装置的数据输出电路
公开(公告)号：US07808841B2
公开(公告)日：2010-10-05
申请号：US12169568
申请日：2008-07-08
申请人： Hae-Rang Choi , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee
发明人： Hae-Rang Choi , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee
IPC分类号： G11C7/10 , G11C7/06 , G11C7/00
CPC分类号： G11C7/1051 , G11C7/1057 , G11C29/028 , G11C29/1201 , G11C29/50
摘要： A data output circuit for a semiconductor memory apparatus includes a driver control signal generating unit that has a plurality of control signal generating units, each of which generates a driver unit control signal in response to a test signal during a test, and generates the driver unit control signal according to whether or not a fuse is cut after the test is completed, a first driver that has a plurality of driver units, each of which is activated in response to the driver unit control signal to drive a first data signal as an input signal and to output the driven first data signal to an output node, a signal combining unit that generates a first driver control signal in response to the driver unit control signal and an enable signal, and a second driver that has a plurality of driver units, each of which is activated in response to the first driver control signal to drive a second data signal as an input signal and to output the driven second data signal to the output node, and the number of driver units being two or more times as much as the number of driver units in the first driver. A voltage level on the output node is the voltage level of an output signal.
摘要翻译：一种用于半导体存储装置的数据输出电路，包括具有多个控制信号生成单元的驱动器控制信号生成单元，每个控制信号生成单元响应于测试期间的测试信号生成驱动单元控制信号，并且生成驱动单元根据在测试完成之后是否切断熔丝的控制信号，具有多个驱动单元的第一驱动器，每个驱动器单元响应于驱动单元控制信号被激活以驱动第一数据信号作为输入信号并将驱动的第一数据信号输出到输出节点;响应于驱动单元控制信号和使能信号产生第一驱动器控制信号的信号组合单元，以及具有多个驱动器单元的第二驱动器，其中的每一个响应于第一驱动器控制信号被激活，以驱动第二数据信号作为输入信号，并将驱动的第二数据信号输出到输出节点;以及驱动器单元的数量是第一驱动器中的驱动器单元的数量的两倍或更多倍。输出节点上的电压电平是输出信号的电压电平。

110. 发明申请

US20100164568A1 LOW POWER VARIABLE DELAY CIRCUIT 有权
标题翻译：低功耗可变延迟电路
公开(公告)号：US20100164568A1
公开(公告)日：2010-07-01
申请号：US12636901
申请日：2009-12-14
申请人： Hae-Rang CHOI , Yong-Ju KIM , Sung-Woo HAN , Hee-Woong SONG , Ic-Su OH , Hyung-Soo KIM , Tae-Jin HWANG , Ji-Wang LEE , Jae-Min JANG , Chang-Kun PARK
发明人： Hae-Rang CHOI , Yong-Ju KIM , Sung-Woo HAN , Hee-Woong SONG , Ic-Su OH , Hyung-Soo KIM , Tae-Jin HWANG , Ji-Wang LEE , Jae-Min JANG , Chang-Kun PARK
IPC分类号： H03L7/00
CPC分类号： G11C19/28
摘要： A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units.
摘要翻译：可变延迟电路至少包括固定延迟单元，第一选择单元和可变延迟单元。固定延迟单元接收表示第一延迟的输入信号和第一延迟选择信号，并且输出基本上延迟了第一延迟的输入信号的第一延迟信号。第一选择单元接收输入信号，第一延迟信号和第二延迟选择信号，并且基于第二延迟选择信号将输入信号或第一延迟信号输出到可变延迟单元。可变延迟单元还接收表示第三延迟的第三延迟选择信号，并且输出基本上延迟了第三延迟的选择单元的输出信号的输出信号。第一个延迟是M个延迟单位的0或X倍。第三延迟是从0到N个延迟单元中选择的延迟。

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